MODULE – 5

COUNTERS
Primary purpose of a counter is to produce a specified output pattern sequence. It is also called
a pattern generator Each stored 0/1 combination is called the state of the counter. The total
number of states is called its modulus. If a counter has m distinct states then it is called a
mod-m counter The order in which states appear is referred to as its counting sequence.
Depicted by a directed graph called a state diagram.
State Diagram of a Counter:
• 𝑆𝑖 denotes one of the states of the counter.

• Arrows in the graph denote the order in which the states occur.
DESIGN OF BINARY COUNTERS:
A counter is a sequential circuit that goes through a prescribed sequence of states up on the
application ofinput pulse. Counters are in two categories –
Ripple (Asynchronous) Counter – consists of a series connection of complementing flip-flops,
with the output of each flip-flop connected to the clock-pulse input of the next higher-order
flip- flop. The flip-flop holding the LSB receives the clock-pulse.

Synchronous Counter – the input pulses/ clock-pulses are applied to all clock-pulse inputs of
all the flip-flops simultaneously.

Asynchronous Counters:
3-Bit Binary Ripple Counter, Waveforms & Truth Table
The above Figure shows three negative-edge-triggered, JK flip-flops connected in
cascade to form a 3-bit ripple counter. The system clock (a square wave), drives flip-
flop A. The output of flip-flop A drives B, and the output of B drives flip-flop C.
All the J and K inputs are tied to +VCC. Hence, flip-flops will toggle with a
negative transition at its clock input.
Assume that, the flip-flops are all initially reset to 0 outputs. For every clock NT, flip-
flop A will change state. Notice that, the waveform at the output of flip-flop A is one-
half the clock frequency.
Since, A acts as clock for B, each time the waveform at A goes low, flip-flop B will
toggle. Notice that, the waveform at the output of flip-flop B is one-half the frequency
of A and one-fourth the clock frequency.
Since, B acts as clock for C, each time the waveform at B goes low, flip-flop C will
toggle. The waveform at the output of flip-flop C is one-half the frequency of B and
one-eighth the clock frequency.

Problem: What is the clock frequency of a 3-bit ripple counter, if the period of the
MSB waveform is 24 µs?

Solution: Since there are eight clock cycles in one cycle of MSB, the period of the
clock must be 24/8 = 3µs. The clock frequency must be 1/(3*10–6) = 333 KHz.
1. A binary ripple counter in straight binary sequence will be as shown in the above table. A
ripple counter having n flip-flops will have 2n output conditions. For example, the three-flip-
flop counter has 23 = 8 output conditions (000 to 111).
2. A three-flip-flop counter is often referred to as modulus-8 (or Mod-8)
counter, since it has eight states. The modulus of a counter is the total number
of states through which the counter can progress.

No. of Flip-Flops 1 2 3 4 5 n
No. of States 2 4 8 16 32 2n
 Problem: How many flip-flops are required to construct a mod-128 counter? A mod-
32 counter? What is the largest decimal number that can be stored in a mod-64
counter?

Solution: A mod-128 counter must have seven flip-flops, since 27 = 128. Five flip-
flops are needed to construct a mod-32 counter. The largest decimal number that can
be stored in a mod-64 (six flip-flops) counter is 111111 = 63.
The 54/7 493A The logic diagram, DIP pinout, and truth table for a 5417493A are given in Fig. This
TTL MSI circuit is a 4-bit binary counter that can be used in either a mod-8 or a mod-16 configuration.
If the clock is applied at input CKB, the outputs will appear at Qs, Qc, and Qn, and this is a mod-8
binary ripple counter exactly like that in Fig. 10.L In this case, flip-flop QA is simply unused.

On the other hand, if the clock is applied at input CKA and flip-flop QA is connected to input CKB, we
have a mod-16, 4-bit binary ripple counter. The outputs are QA, QB, Qc, and QD. The proper truth table
for this connection is given in Fig. 10.2c. All the flip-flops in the 7493A have direct reset inputs that are
active low. Thus a high level at both reset inputs of the NAND gate, R o(I) and Ro(2), is needed to reset all
flip-flops simultaneously. Notice that this reset operation will occur without regard to the clock.
An interesting and useful variation of the 3~bit ripple counter is shown in Fig. The system clock is still
used at the clock input to flip-flop A, but the complement of A, A, is used to drive flipflop B, likewise;
B is used to drive flip-flop C. Take a look at the resulting waveforms. Flip-flop A simply toggles with
each negative clock transition as before. But flip-flop B will toggle each time A goes high! Notice that
each time A goes high, A goes low, and it is this negative transition on A that triggers B. On the time
line, B toggles at points a, c, e, g and i. Similarly, flip-flop C is triggered by B and so C will toggle each
time B goes high. Thus C toggles high at point a on the time line, toggles back low at point e and goes
back high again at point i. The counter contents become ABC= 111 at point a on the time line, change
to 110 at point b, and change to 101 at point c. Notice that the counter contents are reduced by one
count with each clock transition! In other words, the counter is operating in a count-down mode. The
results are summarized in the truth table in Fig. 10.4c. This is still a mod-8 counter, since it has eight
discrete states, but it is connected as a down counter.

A 3-bit asynchronous up-down counter that counts in a straight binary sequence is shown in Fig. It is
simply a combination of the two counters discussed previously. For this counter to progress through a
count-up sequence, it is necessary to trigger each flip-flop with the true side of the previous flip-flop
(as opposed to the complement side.). If the count-down control line is low and the count-up control
line high, this will be the case, and the counter will have count-up waveforms such as those shown in
Fig. for up counter.

On the other hand, if count-down is high and count-up is low, each flip-flop will be triggered from the
complement side of the previous flip-flop. The counter will then be in a count-down mode and will
progress through the waveforms as shown in Fig. for down counter.

DECODING GATES:
A decoding gate can be connected to the outputs of a counter in such a way that the output of the
gate will l,t high (or low) only when the counter contents are equal to a given state. For instance, the
decoding gate connected to the 3-bit ripple counter in Fig. a will decode state 7 ( CBA = 111 ). Thus the
gate output will be high only when A = 1, B = I, and C = 1 and the waveform appearing at the output of
the gate is labeled 7. The Boolean expression for this gate can be written 7 = CBA. A comparison with
the truth table for this counter will reveal that the condition CBA = 111 is true only for· state 7. The
other seven states of the counter can be decoded in a similar fashion. It is only necessary to examine
the truth table for the counter and then the proper Boolean expression for each gate can be written.
For instance, to decode state 5, the truth table reveals that CBA = 101 is the unique state. For the gate
output to be high during this time, we must use C, B, and A at the gate inputs. Notice carefully that if
B = 0, then B The correct Boolean expression is then 5 = CB A, and the desired gate is that given in Fig.
c.

All eight gates necessary to decode the eight states of the 3-bit counter are shown in Fig. a. The gate
outputs are shown in Fig. b. These decoded waveforms are a series of positive pulses that occur in a
strict time sequence and are very useful as control signals throughout a digital system. If we consider
state O as the first event, then state 1 will be the second, state 2 the third, and so on, up to state 7.
Clearly the counter is counting upward in decimal notation from O to 7 and then beginning over again
at 0.
Synchronous Counters
The ripple counter is the simplest to build, but there is a limit to its highest operating frequency. As
previously discussed, each flip-flop has a delay time. In a ripple counter these delay times are additive,
and the total "settling" time for the counter is approximately the delay time times the total number
offlip-flops. Furthermore, there is the possibility of glitches occurring at the output of decoding gates
used with a ripple counter. The first problem fully and the second problem, to some extent can be
overcome by the use of a synchronous parallel counter. The main difference here is that every flip-flop
is triggered in synchronism with the clock.

The construction of one type of parallel binary counter is shown in Fig. along with the truth table and
the waveforms for the natural count sequence. Since each state corresponds to an equivalent binary
number ( or count), we refer to each state as a count from now on.

The basic idea here is to keep the J and K inputs of each flip-flop high, such that the flip-flop will toggle
with any clock NT at its clock input. We then use AND gates to gate every second clock to flip-flop B,
every fourth clock to flip-flop C, and so on. This logic configuration is often referred to as "steering
logic" since the clock pulses are gated or steered to each individual flip-flop. The clock is applied
directly to flip-flop A. Since the JK flip-flop used responds to a negative transition at the clock input
and toggles when both the J and K inputs are high, flip-flop A will change state with each clock NT.
Whenever A is high, AND gate X is enabled and a clock pulse is passed through the gate to the clock
input of flip-flop B. Thus B changes state with every other clock NT at points b, d,f, and hon the time
line. Since, there is an additional AND gate delay for the clock at B flip-flop in comparison to A flip-flop,
it is not a parallel counter in a strict sense of the term. Since AND gate Y is enabled and will transmit
the clock to flip-flop Conly when both A and B are high, flip-flop C changes state with every fourth clock
NT at points d and h on the time line. Examination of the waveforms and the truth table reveals that
this counter progresses upward in a natural binary sequence from count 000 up to count 111,
advancing one count with each clock NT; This is a mod-8 parallel or synchronous binary counter
operating in the count-up mode. Let's see if this counter configuration has cured the glitch problem
discussed previously. The waveforms for this counter are expanded and redrawn in Fig. 10.11, and we
have accounted for the individual flip-flop propagation times.

The counter in Fig. is a synchronous 4-bit up-down counter. To operate in the count-up mode, the
system clock is applied at the count-up input, while the count-down input is held low. To operate in
the countdown mode, the system clock is applied at the count-down input while holding the count-up
input low.
Holding the count-down input low (at ground) will disable AND gates Y1, Y2, and Y3• The clock applied
at count-up will then go directly into flip-flop A and will be steered into the other flip-flops by AND
gates Xi, X2, and X3. This counter will then function exactly as the previously discussed parallel counter
shown in up counter The only difference here is that this is a mod-16counter that advances one count
with each clock NT, beginning with 0000 and ending with 1111. The correct waveforms are shown in
Fig. b. If the count-up line is held low, the upper AND gates X1, X2, and X:1 are disabled. The clock
applied at input count-down will go directly into flip-flop A and be steered into the following flip-flops
by AND gates Y1, Y2, and Y3. Flip-flop A will toggle each time there is a clock NT as shown in Fig. c.
Each time A is high, AND gate Y1 will be enabled and the clock NT will toggle flip-flop Bat points a, c,
e, g, and so on. Whenever both A· and B are high, AND gate Y2 is enabled, and thus a clock will be
steered into flip-flop C at points a, e, i, m, and q. Similarly, AND gate Y3 will steer a clock into flip-flop
D only when A, B, and C are all high. Thus flip-flop D will toggle at points a and i on the time line. The
waveforms in Fig.c clearly show that the counter is operating in a count-down mode, progressing one
count at a time from 1111 to 0000. If you examine the logic diagram for the 54/74193 TTL circuit shown
in Fig. ,This MSI circuit is a synchronous 4-bit up-down counter that can also be cleared and preset to
any desired count-attributes that we discuss later. For now, you should carefully examine the steering
logic for each flip-flop and study the OR gate and the two AND gates at the input of the OR gate used
to provide the clock to each flip-flop