SHARP LM32010P Features @ 12cm [4.7"] QVGA format Wi Black & white display Medium Size Graphic Type LCD Module I High brightness (80 cd/m?) 1 Mechanically compatible with LM32P10 and LM32k101 Specifica' [Parameter J Parameter _ _ Display size 147] Brightness - “eo Dot format (Hx V) 20 x 240 Duty ratio i240 Dot pitch (Hx V) 0.00.30 Backlight icoFTEE) Active area (H x V) 96.0 x 72.0 Power consumplion panel 178 Panel type STN : Backlight 30 Panel mode “Transmissive ‘Outline dimensions (WxHxD) 1480 196011070)" 80" Color Bw color} |Woignt 140 Contrast ratio ya =| [Operating temperature | Oto +45 Response time ‘4001 ms] [Storage temperature -25 to +60 Outline Dimensions rotee 7-4 ae waa | 10 - vata | 061 ps ia E Pry | Lf t = nit: mm nuGooSPEC Wo. MODEL N.C PAGE SHARE _ ree2ze24 | LM32010P 1 | Le dpoticatio i This deta sheet is to introduce the specification of IM320(0F, Passive Metrix type LCD Unit. 1329240 dot, TSTH, negstive type, with backlight system by cold cathode fluorescent tube (CCFT).} . Consiraction sad Outline Consutruction : 320x240 iuil dot graphic displey unit outline eet & Sonmeetion See Fir &. and Table 5. There shel! be ag sertckes, steins, chips, distortions snd other exterael | drawbacks that say effect the display function. Rejection criteria shell be noted in {nspection Standard $ 012-01.[SPEC Wo WOE Wo. =SSS*«*rCPAGE SHARP Leg2924 LM22010P | 2 4. Wecbanicn) Specifications, Tablet —— | Specification ! Gutijae dimensions 148 (9)_x 96 (8) x SMAX (D) : tive viewing erea | 10000 ¥ 716i) =m Displey torset (aaa x 240m) full dot t [Bispler tort eee {tot LO Te mx 0. 2618) 0.02 an - Wite | | Back Approx. 140 — - | Novel © Excluded the uousting tab. (See Fig. #] Note? : Due to the characteristics of the LC Materi with environsental tenperatar , the colors vary ig ow 1 wn Te ! wot pels OFF > Black 4 Absolute Matiaus Retizes 4-1, Tleetrical Absolute Maxizua Ratings Tshle 2 o Parameter Symbol [ Hin [MAX [ Sunpiy voltage (oeic) Too Ves] 0 | 80 | {Supply voltage (LOD Driver) |Veo—Vex |" 0 [20.0 | Input voitare Yim o | wm | Back Liat voort o_| 1300 | i ICCrT a [65 [ eres[SPHE Ne. [RODE No. ~ [Psst SHARP 7 Los2924 , LM32010P | 2 r S | | | 4-2, Environmental Coadition | [teat Toor Femrt win, [vat [OMT [Max | “25°C | +60°C orc | 445°C | Tabient temperat Escidity “TWote 1 | Wote 1 [No condensation [Vibratioa Woe 2 Note? {8 directions (/T/4 | Shoex Wote 3 Wote 3 [6 directions i 7 (ev/at/in Note I] 0% BR Max | | | { i i | Ta=40'C / 90% BR i ; Note 2) These test conditions are in accordance with “IRC 8-2-8" jon width : 1. Sum Interval : 10H2 ~ SSH2~ 1082 (1 sia 2 boure for each direction of X/1/2 (6 hours as total) Note a) Accerel 4gon/s? ($06) Pulse width ; [ins a tines tor each direction of $1/1/22.3H | HODEL We. SHARF Les2924 | LM32010P BDleckrical Specifications 5.1 Electrical characteristics ‘Table 4 _ = Te=254C, VD "Praneter ~[srabol [Conditions “7 win T tys. * Vsupply valtege (Lorie) Voo-Vas - 475 | 8.0 ‘Supply voltace (CD drives | Yrx-Ves] Vaoe6¥ Mole 1) 16.0 | (Taput signal voltace \Viw [| “R leved : i “Flevel i (Toput leakage current yt (Supply correat (osi Toe _|Vanea¥, Vae=-18¥ ora i Supply current (LCD) TeV [Power consumpution (LCD) PALCD |F=80R2 (Note 2) | (Start il Lats [Taverter (Supply voltere (b/M) | Witl |iwoooios I ves Supply current (8/U THE |lnpat voltere 12 | 8 | 6 | adras [Power cousuaption (@/1) | RAFT taf] rest ona be set Note L) The viewing ancle(@) where obtains the eaxinua coi by adjusting variable resistor between V2i and TR Refer to Fig, 4 for the difinttion of 6. Note 2) Display high trequeney pattern. LOD unit 200k a7SPEC No. MODEL Wo. ==SSSCS*C*~SCS AG SHIARS Los2924 LM3zo10P | 5 Se2, Interiace signals CNL (Fin No | Syebols| Description Level i + $ Seam start~oo sigvel "a 2 CPi | Input date lated signa] | Wer [| Data input clock signal WL pply for logic Grocod potential (Ov) Pover supply for LtD (- Display data signel ie Ra Used Connector ; 52103-1217 [Molex] Mating Cable : 1Gum pick , 1pfas REG Srebols Deseriptlon Vti__[ Pover supply for CCFT back Vit2 | Power eupply for COPT back light "i Pin No. and ite location are shova in The 8,ee [HODEL Ro. Fie] SHARE L¢92924 | LM32010P . 10 Gufnit Driving Hetbod fel. Cirouit Coatiguration Fig. 7 shows the block disgran of the Unit‘s circuitry. 6-2. Display Face Configuration the displey face electrically consists of signe] display segment of ! 20 x 240 dats, | | | 6-3. Input Date and Control Signal i “ke 0D driver is 80 bits LSL, cousisting of shift registers, Intech cireuite { ead LD driver cirenits i Clspiay date which ere extertally divides into date for exch row (320 dots] will be sequentially transferred in the form of 4-bit pereilel data through tt resisters by Clock Signal CP2 from the left top of the displey face, Shen date of one row (220 dots) Aave besa inputted, then leched in the frot of parallel! data for 320 lines of signe! electrodes by Latch Stews! CPi. ‘hen the corresponding drive signal will be transnitted to the 32) lines of colvaa electrodes of the LCD pene] by the LCD drive cirevits, this Sime, scan start-up signal § has been transferred trom the scan au] driver te the Ist row of scaz electrodes, and the contents of the data signels ere displayed on the Ist rove of the display face according to the combinations of Yolteges applied to the sean and sienal electrodes of the 103. Wile the Ist rows of dete are being displayed, tbe 2ad rovs of date are eaterad. When 320 doty of date bave bee transferred then latched op the dalling adge of CPL clock, the displey face proceeds to the 2nd revs of display. . Such date input will be repeated up to the 240th ro of each display segment, cron upper to lower rove, to couplete one frens of display by time sharing uethod, Then date input proceeds to the next display face. Sean start-up Signal § cenerates scan signtl to drive horizontal electrodes, The unit shall be driven et the speed of 10~80Rz/frane to avoid flickering.SPEC No. NOEL We. PASE SHARE Los2924 __LM32010P. 11] | i Since DC voliage if applied to LCD panel, causes chemical reaction which wis! | jeteriorate LC) paael, drive waveform shall be inverted to prevent the gene: ration of such DC voltage, Aud to prevent such problea, AC wevefora circus! | generated by counting CPL M generator) is built in this circuit Fecuute of tae caeracteristics of the CMOS driver LSi, the power consumption ‘he unit ense ap ar he operating frequency CP2 incresses, This the ériv applies the system of transferring 4-bit palallei deta throush the « S:ars shift resistors to reduce the date transfer speed CP2. Thenks to the LST, lhe power consumption of the uait vill be einimized, st in shis cironi! configuration, d-bit display data sell be therefore ixputtec to date input pins of DO~D3. \ Surthermote the SCD unit adopts bus line systes for data input to ainisize ube power consuupiion. In this systex data input tereins] of each driver iS] is activated only when relevant data input is fed. pate input for colum electrodes of both the upper and the lower displey ceguent and chip select of driver LST sre made as fol Low: The driver 1ST at the left end of the display face is first selected, } sad the adjacent driver LST of the right elde is selected when 80 dels i dats (20 (Pl) is fed. Thig process is sequentially continued until dete is ted to the driver LST at the right end of the display face. This process is simelteneously followed at the coluen driver LSI'a of both the upper and the lower display seguenty. Thus date input throogh sobit bus Ling cocuentially trom the left end of the display face, Since this graphic displey unit containe no reflesh 2AM, it requires dete end tining pulse inputs even for static display. Tho tining chart of input stenals are shove in Pig. 3.SPEC No, HODEL We, RAGE SHARr LOS2924 LM32010P {| 12 e L Opticnl Characteristics (Table 1 shows the optica! characteristics whea the viewing a: obtaining the aaxieum contrast (@) fs adjusted to 0 derrees.) ‘able YDDSSY, Te=251C [Beran [Sratol [Condition x (thi! [Rraark] ' oo [teRhd den | Rote i 61162 [Comat der, [Note t | Viewsag angle | | range sso" 3s | 225 | der. he a wl as z wep So i Re] [340 ms u ory Viewing direction ER_t Definition of Viewing Angie Note 2] Contrast ratio way be defined as follows: Contrast ratio is ealeurated by nsing the fol when the wareforg voltae (Fie $} is applied in opi: test method (is. 8), Photovdetector gutpat voltage vith Select vaveforg being svslied Contrast ratio= ees Photo-detector ontput valt, soraelect marstore becag eppited to? formals PAGE * Angles 61,82 and # shell fall withia the reage overvbich the ispleyed charecter each be reed. al characteristicsi { 1 test cethod showa in Pie, 5, Note 4) Table 1 showa the optics characteristics detected when the LCD applied voltage wavetorus are in the highest frequency * * The sost critical condition for the charecteristics of LCD. Mae i i i i i i i | i ® | | Light souree Hik_i finties Chamuctatistice Test Method MODEL Wo. | PAGE SPEC Mo. SHARPE Los2s24 | LM32010P Wote a} The respouse ebarecteristics of photo-detector output are seasurec as shown in Fig. 8, assuming that Input signelc are applide so as to select and deselect the dots to be measured, in the optical characteristics Lh Photo-detector : (Incladed « viewing sensi- Viewing sensitivity aodurator Ne 13SPEC No. MODEL Me. TPA PAGE SHARrF Les2a24 LM32010P_ | 14 { (Brive wavatora] | aka iy ni ~~ avatars PF —— wayetora ——>}e— savetors —— i | | | Response | wavetars . a 1 | le | ae to 10x | autput | y I | i KCSPEC No. MODEL Ne. | PAQE SHARPE _|_teo2e24 | LM3zo10p | 15 TOR. Characteristics of Bucklightit Brightness pferaneter Min] te] _tait Brightaess | 60 [| 80 = edn | Rating are deflaed as the average brightness at § measurement points, | ly | | N Bot aren 40 160 280 Det {b) Neesuroment condition CCHY taverter + LM000L08 IMPOT voltace : 12.0V LYT : Sma Led unit Condition : LOD ig full dot ON (White) VIE=-18..07, Tenperatare ; Tee2HC, a0 minutes after turaing on Measureneat equipneat : BM-7 (TOPCON Corporation) (C) Operating Lite time ~The oprating lite tine is 10,000 hours nore ender ihe following conditions. crt Aaverter is I7T=Snaras tetets°C The operating lite time is do! das heving ended vhen suy of the following ee or quantity of light has decreased to 30% of the initial valve. When the Light of CFT goes to flicker reaarkble.SHArRrFS Wp, WSS WE i Hies Voitace | Generator va | | Lo va SPEC Ho. SY MOPRL Ne. Annee. LM32010P LcobD | 3208240 Dot J Hi HG:M GENERATOR Tage | 16RE We WHEL We. SHARP Lo97306A) LM32019P COLUMN tdot. 2dot dot ROW téot. 2dot Bdot 2A0dot. (3-lo lor 2s0dot Fig. 1 Dot chart of display area 320dotFT We WIE We PIE SHARP Lo97306a| LM32019P 9 cP 1 ~ M7 Nn cp JL TLS SL 03 40 317 Tiwalig TT 15 XX 1 arNlval dX CT 02 240, 318 Invalid 12 XTX XT wal 2X KCB D1 X240, 319 \Invalid Ls LT X Tai9XIvalid Y___2.9 2319 YX Do \2a0, 320 Minvaliey 7.4 To Care Zax | X23 s L - 0P2 x 320/4 pulses R cpr J] - mn e d | ~3 Yim = Bet u | D0~3 Xr 9320) 240, (1~320) X17, (1~920) ce e | | d L sll TL Li i +L CP! x 240 pulses Fig.2 Data input timing chartFEE Ke WEL fo. Fite SHARP LC97306A) LM32019P 10 tr) thHH tf cP! oP2 : J } DATA [tssu, | {tsi | 1\ _ CP2_x (320/4) pulses | s C » JN inst second jline' s line’ s Reduced ta data transfer s L L cP1_x 240 pulese | Vit=0, 800 ViL=0. 2400 Fig.3 Interface timing chartEC ho WHEL Wo PIE SHARP L097306A) LM32019P a Table 7 Interface timing ratings Teen ‘Symbor Rating Thit WIN TYP._[ WAK Frame cycle Tera [125 [= | 143 [ns (P2 clock cycle top2_ [130 [= = [1s] H” Tevel clock width. — - CHE 60, = = ns “U7 level clock width 6 | [ns] *H level latch clock width ee = ns_| Data set up time tu | 50 = [1s Data hold tine _ tsH_| 40 = = [ons (P21 clock allowance tine from CPI T esi2_ [0 = = [ns (P11 clock allowance time from CPZ! ~_|_ tsar 0 = =| ns Input signal rise/fall tine (Note 1) —_| tr. tf_T = = tf [ns ['S Signal Data set up time tssu [40 = = ns_| S Signal Data hold time tsi 6 | - = ns | Note 1) Owing to the characteristics of this LCD module, “shadowing” will becone more eminent as frame frequency goes up. flicker wil! become more eminent as flame frequency goes down. So it is recommended that the module should be driven according to the specified ! imit. Note 2) trf=50 in case tCT=(TCP2-tCWH-tCHL) /2250 trf=t0T in case tl (CP2-tCHH-tCHL) /2<0FED We WHEL Fe PRE SHARP LC973064| LM32019P 12 5-3 Supply voltage sequence condition The power ON/OFF sequence shown on Fig. 4 shall be followed to avoid latch-up of drive LSIs and appl ication of DC voltage to LOD panel. 500 ms WIN. (Note 1) - A en Active s “L" level a Speration | Lu" tevel OPI. oP2 X\__Interface timing itis opgration xX DATA. 7 | 2 a | -—- Dis | | k | co La | ko} kL | £ aaa | VEE ena, a | Fig.4 Power ON/OFF sequence Table 8 Sequence timing ratings POWER ON POWER OFF ] ‘SYWBOL[ With DISP Without DISP SYMBOL With DISP without DISP [| controt control . control control 0 ms WIN, ms WIN. | 7 20 ms MAK oe 25 ms WA b O ms WIN 20 ms HIN. i Oms WIN. | 20 ms IN. ce | _20 ms WIN a [7 [20 ms MIN. = d O ms WIN. S Pk O ms WIN. a e = ms MIN. I = O ms WIN, f Oms NIN. ote 2) m | Oms MIN Wote 2 e = 20 ms WIN. [=n = Ons WIN, Note 1) Power ON/OFF cycle time. Al! signals and poner line shall be in accordance with above sequence in case of power ON/OFF. Note 2) VEE to be set at “VSS level”FETT THIEL Wo THE SHARP LO97306a) LM32019P 13 6. Module driving method 6-1 Circuit configuration Fig.5 shows the block diagram of the module’ s circuitry. Fig.5 Cirouit block diagram ea Control oe Ls! | j = | in $f | LCD GENERATOR BIAS GENERATOR VDD, VSS, VEESHARP L6973064| LM32019P PEE We TWOOEL Wo PRE 14 6-2 Display face configuration The display consists of 320x240 dots as shown in Fig.1. The interface is to be driven at 1/240 duty ratio. 6-3 Input Data and Control! Signal The LCD driver is 80 bits LSI, consisting of shift registers, latch circuits and LOD driver circuits. Input data for each row (320 dot) will be sequentially transferred in the form of 4 bit parallel data through shift registers from top left of the display together with clock signal (¢P2) When input of one row (320 dots) is completed. the data wil! be latched in the form of parallel data corresponding to the signal electrodes by the falling edge of latch signal (CPI). Then, the corresponding drive signals will be transmitted to the 320 lines of column electrodes of the LCD pane! by the LCD drive circuits ‘At this time, scan start-up signal (S) has been transferred from the scan signal driver to the Ist row of scan electrodes, and the contents of the data signals are displayed on the Ist row of the display face according to the combinations of voltages applied to the scan and signal electrodes of the LOD. While the data of Ist row are being displayed, the data of 2nd row are entered. When data for 320 dots have been transferred, they wil! be latched by the falling edge of LP, switching the display to the 2nd row. Such data input will be repeated up to the 240th row of each display segment. from upper row to lower rows. to complete one frame of display by time sharing method S generates scan signal to drive horizontal electrodes. Since DC voltage. if applied to LCD panel, causes chemical reaction in LC materials. causing deterioration of the materials, drive wave-form shall be inverted at every display frame to prevent the generation of such DC voltage. Control Signal W plays such a role.