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DC/AC Conversion

Chapter · January 2010

DOI: 10.4018/978-1-61520-647-6.ch007

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DC/AC CONVERSION

Basic Indicators

The operational principle of converters from DC into AC electrical powers, so-called

inverters, is based on the idea studied in Chapter 3. In this chapter, the autonomic or
independent inverters are studied, whose operational frequency is determined in general by
their control system (Bedford, 1964). These inverters can be separated in the following basic
groups:
1. Current-source inverters – their special feature is a presence of an inductance with a
very high value connected in series with the DC source and thus the source become a
current generator. As a result, the current through the devices and in the non-branched
part of the output circuit have waveforms close to a square one. Voltage across the
load is specified by its type and parameters.
2. Voltage-source inverters – their name comes from the waveform of their output
voltage – it has a specific form which depends only on the control algorithm of the
power devices of the inverter circuit and on the type of the circuit at the side of the DC
source. More often a capacitor with a high value is connected in parallel to the DC
source and thereby the source is a voltage generator. Since a voltage with a specific
waveform is applied to the inverter output, waveform of the inverter output current
depends on type and parameters of the load.
3. Resonant inverters – Their common feature is the use of resonance processes to switch
the power devices. Dependent on the power device type and a topology of the power
schema, switching at zero current or zero voltage may be realized decreasing the
commutation losses and making the use of the resonant inverters in high frequency
appropriate. The supplies of the resonant inverters are more often voltage-sources. The
inverter load is a part of the resonance circuit, in which resonance processes develop.
These processes are developed at the switching of the power devices and thus the DC
source voltage appears to be applied to a series oscillating circuit causing the currents
through the power devices and the load to have waveforms close sinusoidal.
4. Z-source inverters – Their special feature is a presence of inductances and capacitors
connected in Z-circuit in the input circuit at the DC source side. A special control
algorithm is used as a result of which the total source voltage applied to the inverter is
higher than the voltage of the DC source.

Different power devices have implementation in inverter realizations. The relative part of the
devices has been change during the time. Nowadays, thyristors are applied in the current-
source inverters and resonant inverters in comparatively high powers. Power IGBTs are the
basic devices applied in the voltage-source inverters and Z-source inverters. The IGBTs have
also found a wider implementation in resonant inverters. Power MOSFETs are applied in high
frequencies in the resonant inverters. The MOSFET implementation is more limited in the
voltage-source inverters.
In general, a tendency of expanding the use of the transistors in DC/AC conversion regardless
of the inverter applied is imposed. Therefore, the main attention in this chapter is paid to the
transistor inverter circuits.
A fundamental indicator of a conversion is efficiency coefficient showing the ratio of the AC
power in the load to the DC power consumed from the source:
 

P U K
L .I LK . cos K
(7.1)   L  K 1

Pd U d .I d
where in U LK , I LK are effective values of the k-th harmonics of the load voltage and load
current, respectively, and  K - is displacement angle between them. In this definition, it is
assumed that in general both the load voltage and load current are of non-sinusoidal
waveform. Applications and loads, which allow this assumption to be made, exist. In other
cases, it is important to supply the load with a voltage whose waveform is as closed as
possible to the sinusoidal one. Then only a multiplier of k=1 rest in the numerator of (7.1).
This is a characteristic mostly of the voltage-source inverters. Therefore, it is usually
necessary to separate only the fundamental harmonic from a non-sinusoidal voltage at the
inverter output. In this case, the harmonic spectrum of the output inverter voltage is important.
The harmonics following the fundamental are preferable to be of a higher possible frequency
to simplify their filtering.
Additional important parameters of the inverters in particular applications may be indicators
as volume, size, level of noise, electromagnetic radiations in the environment, etc.

Single-Phase and Three-Phase Converters

Single-Phase Converters

Current - source inverter

Electrical schematic of a single-phase bridge current-source inverter implemented by

thyristors, waveforms describing inverter operation and vector diagram for the first harmonics
of inverter currents and voltages are presented in Fig.7.1. When thyristors VS1 and VS 3
conduct after the commutation, the current flowing through them ( iVS1  iVS 3 ) is equal to the
current flowing through the non-branched part of the output circuit i . Part of this current
charges the capacitor iC and the rest of it flows through the load i L . At the beginning of the
next half-period (in our case the negative half-period) for the current i , firing pulses are
passed to turn on the thyristors VS 2 and VS 4 . For a short time all four thyristors are on; the
capacitor voltage is applied as a reverse voltage to VS1 (through VS 2 ) and to VS 3 (through
VS 4 ). Capacitor discharging current flows through the circuit including VS1 and VS 2 in an
opposite direction to the anode current of VS1 , causing a turning off of the last thyristor.
Analogical process is developed in the circuit including VS 3 and VS 4 leading to a turning off
of VS 3 . Recharging of the capacitor begins through VS 2 and VS 4 with current iVS 2  iVS 4 and
to a voltage whose polarity is opposite to this of the previous half-period. The current in the
output circuit only changes its direction. It appears in Fig.7.1.b and Fig.7.1.c that the first
harmonic of the output current leaves behind the output voltage at a leading angle ,  which
determines the circuit reverse recovery time of the thyristors t qc (   .tqc ) if the
commutation processes are neglected.
 Ld


VS1 UC  U L VS 2
Id U VS 1
IC
C

Ud RL
LL
I

IL
VS3
VS 4


а)
iG1  iG 3 iG 2  iG 4 iG1  iG 3
iG

iVS 

iVS1  iVS 3 Ld   iVS 2  iVS 4 Id


i, u L
uL
i UL
i1
Ld  
Id  I
IL
I La
 
IC I Lr
uVS1

t qc
(     t qc )
b) c)
Fig.7.1. A single-phase bridge parallel current-source inverter: a) electrical circuit; b)
operational waveforms; c) vector diagram

Therefore, part of the capacitor value has to compensate the inductive type of the load and the
other part to secure reactive type of the output circuit and circuit recovery time t qc for a pair
of the diagonally connected thyristors that has been conducting till that moment. If this time is
less than the required catalogue time for the chosen type of the thyristors - t q , a breakdown
regime happens. In this mode the four thyristors are on simultaneously and the inverter is a
short - circuit for the supply source. The current through the thyristors in a steady state would
be limited only by the parasitic resistance in the circuit and thus an irresistible break of the
devices takes place. The velocity of the current increase is limited by the large value of the
input inductance. To preserve the break in this breakdown mode, special methods and
protection schemas are provided.
Using vector diagram for the first harmonics of the voltages and currents in Fig.7.1.c, basic
characteristics connected with the inverter operation are derived:
(7.2) Pd  PL
(7.3) U d .I d  U L .I . cos 
After transforming (7.3), it is found:
U L .I 1
(7.4) 
U d .I d cos 
Since the current waveform in the inverter diagonal is a square one with a maximum value of
I d and I is the effective value of its first harmonic, then using Furrier series the following
equation is valid:
I 2. 2
(7.5)   KI
Id 
where in К I is an inverting coefficient. Its substitution in (7.3) leads to:
U L .K I 1
(7.6) 
Ud cos 
Therefore, the output voltage can be regulated by changing either the supply voltage or the
angle  .

U~ 
Id FP
ACS VCO PD Drivers
UT

Id UT
tasks
a)
U ~ 
FP
Id
ACS TSC PD Drivers
UT

Id UT UT
tasks synchronizastion
b)
Fig.7.2. Block schemas illustrating a) independent excitation and b) load dependent
excitation in current-source inverters

Two methods for excitation exist in the thyristors current-source inverters – independent
excitation and load dependent excitation or self-excitation. The methods are illustrated in
Fig.7.2 by block schemas.
In both methods, it is possible to realize stabilization of some of variables – input current I d
or load voltage U L . The type of the stabilizing variable depends on the particular purpose of
the inverter. To be able to stabilize a variable, an automatic control system (ACS) is provided.
In the independent excitation – Fig.7.2.a, the firing pulses are generated by a voltage
controlled oscillator VCO. The control voltage is proportional to the error  in ACS. Thus,
the output parameter is inverter operational frequency  , and a consequence from it is the
angle  , the input current and the load voltage, which of course also depend on load
parameters and power inverter circuit. In self-excitation – Fig.7.2.b, a synchronization to the
load voltage (more rare to the current through the bridge diagonal) is required. The firing
pulses are generated by so-called time set circuits, which assistance determines the angle  ,
which is an output parameter. The operational frequency  , the input current and the load
voltage that also depend on the load parameters and the power schema are consequences of
the angle  . Pulse distributors to separate the series of the pulses in different channels for
simultaneously turning on of the thyristors, as well as drivers used to form the required power
of the firing pulses so the thyristors to be able to turn on, are needed in both methods. It is
worthy to be mentioned, that the control systems with independent excitation have higher
inertia which at a sharp change of the load may lead to break of the inverter operation and to
turning on of the protection systems. The control systems with self-excitation are
characterized with faster operation but with significantly more complex schema and
technology. Special interest in them is the possibility to regulate and stabilize the load voltage
within some range, without a need of regulation of the controlled rectifier to change the
supply voltage U d of the inverter, by regulation and stabilization of the angle  because of
the equation (7.6).

Resonant inverter

The electrical schematic of a resonant inverter is shown in Fig.7.3. The value of the input
inductance LC is lower than this in the current inverter. Here, the thyristors of the pairs of the
diagonally connected devices VS1,VS 3 or VS 2,VS 4 are simultaneously turned on to conduct.
The control system secures the switching with a control frequency  C . The self-resonance
1
frequency of the load circuit is  L  . Dependent on the ratio between the two
LL C L
frequencies, the inverter operates in resonance -  C   L , inductive mode  C   L or
capacitive mode -  C   L . The load circuit is presented by different equivalent schematic in
the different operational modes. Regardless the pair of the conducting thyristors, a resonance
circuit of LC , C C and the equivalent load circuit is connected to the supply voltage. Let us
mark the elements of this series formed circuit as L, C and R. The parameters of this circuit
should satisfy the following equation for the condition of a oscillation mode to be valid:
L
(7.7) R  2 
C
 LC


id
VS1
VS2
uCC CL
Ud
LL RL
CC
iCC
uL
VS4 VS3 uVS3


Fig.7.3. Electrical schematic of a bridge resonant inverter loaded with parallel resonance
circuit

Fig.7.4 displays the waveforms illustrating the inverter operation in capacitive (Fig.7.4.a) and
inductive (Fig.7.4.b) modes of the parallel load circuit.
Input current id with average value I d is formed of the thyristor currents iVS1  iVS 3 and
 1
iVS 2  iVS 4 . The duration of each current pulse is , 0    2 , after a pulse, a pause
o L.C
follows till the firing of the next thyristor pair. Therefore, the distance between the beginnings

of the current pulses is . The second waveform is the current through the bridge diagonal
C
i L , feeding the parallel oscillating circuit. Dotted line presents its first harmonic. An
assumption for a sinusoidal waveform of the current pulses through the thyristors is usually
made. Thus, the voltage across the series connected capacitor U CC changes according to a
cosinusoidal law during the conduction intervals and it stays DC with its maximum value
U CC max during the pauses. The waveform of the load voltage is illustrated at the fourth
diagrams. In capacitive mode it lags in phase to the first harmonic of the load current
(Fig.7.4.a) and in the inductive mode it goes ahead of the first harmonic (Fig.7.4.б).
 id id
IM IM
iVS 2  iVS 4 iVS 1  iVS 3 Id iVS 2  iVS 4 iVS 1  iVS 3 Id
0   .t 0   .t
iL iL
i1L i1L
IM IM

0  IM   .t 0  IM   .t

u CC
u CC
U CC max U CC max

0   .t 0   .t

uL
uL
U L max U L max

0   .t 0
L   .t
L
uVS 3 U F max uVS 3 U F max
 3 4  3 4

0   .t 0   .t
1  2 U R max 1 2 U R max

qc qc
a) b)
Fig.7.4. Waveforms illustrating the inverter operation in two modes: a) capacitive mode; b)
inductive mode

The waveform of the thyristors in both modes is of interest. A special feature of series
resonance circuit load is the change of the voltage across the power devices during the pauses
1   2 and 3   4 . This happens because the load voltage changes at these moments. It
appears in Fig.7.4 that in capacitive mode the transitory value of the load voltage at 3 is
negative, while in inductive mode it may become positive. Therefore, in inductive mode, the
voltage across the thyristhor, when a reverse voltage is applied, is lower and also a possibility
the voltage to become positive during the interval 3   4 exists. This worse case is shown in
Fig.7.4.b. Thus, the angle  qc and the reverse recovery time t qc are reduced. In capacitive
mode, the reverse recovery time increases but the thyristor voltages also increases, which is
not appreciated because a possibility of break arises.

Voltage - source inverters

Different schemas of single-phase voltage-source inverters, as well as different algorithms for
controlling the power devices and forming a waveform of the output voltage exist. They may
be controlled and uncontrolled inverters dependent on the permission of the used algorithm to
change the effective value of the load voltage. Several of the most widely spread voltage-
source inverters are:
- Single-phase inverters with a square form of the output voltage;
 - Single-phase inverters with sinusoidal pulse-width modulation of the output voltage;
- Single-phase inverters with selective elimination of harmonics in the waveform of
the output voltage;
- Single-phase inverters with multi-leveled modulation of the output voltage –
multilevel inverters;
- Resonant DC-link single-phase inverter.
The last mentioned inverters have not found a wide implementation and thereby they are not
examined in this chapter.
Fig.7.5 displays a bridge electrical schematic of a single-phase voltage-source inverter, where
Z L is the impedance of the load. It may be of different type but it is more often of active-
inductive type as it is additionally shown in Fig.7.5. This is because between points A and B,
where the output voltage is obtained, a primary winding of a transformer or input of a
smoothing filter to remove the higher harmonics of the output voltage are usually connected.
Each pair of lower and upper transistors forms so-called phase-leg transistors and it is offered
by the producer companies in a common body. Sometimes all four transistors are produced in
a common body. The legs are marked as leg A and leg B. The transistor symbols include
subscript of the leg to which it belongs and upperscript “+” or “-“ indicating whether the
transistor has a common point with the positive or the negative source lines. The gate signals
to the transistors in a leg are inverted to one another because the two phase-leg transistors can
not be on simultaneously. This would be a break-mode represented a short - circuit through
the transistors for the supply source.

id

VT A VTB

a b
iL
ZL
+
Ud A B
Cd
LL RL
-

a b
VT A VT B

N
Fig.7.5. Bridge schema of a single-phase voltage-source inverter

Fig.7.6 depicts the waveforms illustrating the schema operation in both cases – uncontrolled
inverter Fig.7.6.a and controlled inverter with a waveform of the output voltage undependable
on the load Fig.7.6.b. At the top of the load voltage, the power switches, which conduct
during the corresponding intervals are marked. Now, the uncontrolled inverter will be studied.
The transistors turn on two by two and diagonally connected ones. For example, when
VTA , VTB are on, the voltage at point A regarding point B is positive and equal to the source
voltage (the voltage drop across the transistors are neglected). The current flows from left to
right through the load. At    control pulses to turn off VTA , VTB and to turn on VTB , VTA
are delivered. VTA , VTB turn off but because of the stored energy in the load inductance
VTB , VTA do not immediately turn on. A certain time interval during which the current
maintain its direction is necessary. During it the diodes VDB , VDA conduct, the load voltage
changes its sign and through the diodes the load energy is accumulated in capacitor C d . Only
when the load current decreases to 0, the transistors VTB , VTA begin to conduct (they have
turning on pulses since    ) and the load current begins to flow from right to left.
Analogical processes are also repeated afterwards, i.e. before the next pair of the diagonally
connected transistors star conducting, their antiparallel diodes conduct. The conducting
intervals of the diodes depend only on the load parameters – time constant and value of the
load current. Fig.7.6 displays the waveform of the current id , whose place in the inverter
schema is marked in Fig.7.5. This current always flows from left to right when a pair of
diagonally connected transistors conducts, and it is always flows from right to left when a
diagonally connected diodes conduct. The average value of the current id is equal to the DC
current consumed from the supply source U d . Its value corresponds to the DC power from the
source. If the load is active, then the waveforms of the current and the output voltage will be
identical and the conducting intervals of the antiparallel diodes will miss. In practice, the ideal
pure active load is hardly met. It appears from the schema operation that the output voltage
value regulation can not be fulfilled in the chosen control algorithm for the power devices.
The output voltage is equal either to + U d in the positive half-period or to  U d in the negative
half-period.
 VD A VT A  
 VD A VT A

uL,uABVD B VT B VD B VT

B

Ud
0  Ud 2   .t

iL

0  .t

id

0
 .t
a)
VD A VT A VT A VDA VD A
VT A
VD B VT B VD B VDB VT B
VT B
or or
uL,u AB VD A

VT A
Ud VTB 
VD B
0  Ud 2   .t
 
iL

  .t

id

  .t

b)
Fig.7.6. Waveforms of a) uncontrolled inverter; b) controlled inverter

The effective value of the output voltage for uncontrolled inverter can be derived from the
graphic in Fig.7.6.a as:
 1 
(7.8) U L   U d .d Ud
2
 0

The effective value of the first harmonic of its output voltage is:
U 1LM 2. 2
(7.9) U 1L   .U d
2 
Single-phase uncontrolled inverter is applicable when changes of the output voltage caused by
changes of the source voltage stay within a range, which is permitted for particular consumer.
The voltage drops across the power devices, which increase with an increase of their current,
as well as the load current, have been neglected in the already made study. Very often a range
of the change of the source voltage is wide, for example accumulation batteries, fuel cells,
photovoltaics, and causes high change in the output voltage values in a combination with a
change of the load current. Thus, normal operation of the consumer will be disturbed and
because of that a regulation and stabilization of the output voltage is required. The primary idea
is to make a delay between a moment of turning off of a transistor pair and a moment of turning
on the next pair, as it is shown in Fig.7.7. For example, if transistors VTA , VTB are turning off
at   1 then VTB , VTA are turning on at    2 . Thus a controlled voltage-source inverter
with an output voltage waveform dependable on the load parameters is realized. As it appears,
at every turning off of transistors, which have been conducting till the moment, antiparallel
diodes of the other two transistors are turning on because of the stored energy in the load
inductance. The output voltage alters its sing and stays in that state till the load current decreases
to 0. These intervals depend only on the load parameters and in practice both harmonic spectrum
and regulation are disturbed because the pauses in the waveform of the output voltage may not
appear in particular loads.

iL

UL

Ud
1 2

Ud


Fig.7.7 Waveforms of the output variable dependent on the load

A controlled inverter with a waveform of the output voltage undependable on the load
parameters is realized using a control algorithm for the power devices operating as it is
illustrated in Fig.7.6.b. Duration of a pause, which is changeable to be able to implement the
regulation, is marked as  . As it is seen form the figure, only one of the transistors of a
diagonally conducting pair is turned off after their interval of conductivity. The load current
flows through the continuing conducting transistor and the antiparallel diode of its neighbor in
the other leg. The output voltage becomes equal to 0 and also a circuit for the load current is
secured. At the passing of pulses to turn on the other pair diagonally connected transistors, the
processes are analogical to those studied in the uncontrolled inverter.
The effective value of the output voltage may be derived from the waveform shown in Fig.7.6.b
as:
1   
(7.10) U L  .  U d2 .d  U d . 1 
 0 
The effective value of the first harmonic of its output voltage is:
U 1LM 2. 2 
(7.11) U 1L   .U d . cos
2  2

Two additional topologies of single-phase inverter with square form of the output voltage are
shown in Fig.7.8. Fig.7.8.a displays a half-bridge electrical schematic, and Fig.7.8.b depicts
the schema with a middle point of the output transformer or so-called push-pull schematic.

The half-bridge inverter schema contains only one transistor leg and the supply voltage is
divided in half by the use of two capacitors. The purpose of the antiparallel diodes is the same
as this in already studied bridge schematic. The transistors are turned on in sequence to form
each of the half-period of the output voltage. In active-inductive load, when a control pulse to
turn on a transistor is passed, its antiparallel diode conducts at first securing a return of the
part of the reactive load energy on the corresponding input capacitor. Only when the current
decreases to 0, the transistor begins to conduct and the load current alters its direction. When
an upper device VTA or VDA is on, the voltage of the upper capacitor C d 1 is applied to the
load with the positive terminal at the right end of the load. When a lower device VTA or VDA
is on, the voltage of the lower capacitor Cd 2 is applied to the load with the negative terminal
at the right end of the load. The effective value of the output voltage and its first harmonic
are:
2
1  Ud  U
(7.12) U L    .d  d
 0  2  2
U 1LM 2. 2 U d
(7.13) U 1L   . .
2  2
In this schema a regulation of the form of the output voltage dependent on the load parameters
can be realized. Also, a regulation undependable on the load parameters can be implemented
if a bidirectional controlled device is connected in parallel to the load. The controlled device
is turned on when a main transistor turns off and it maintains the same load current direction
and zero voltage across it. In practice, the already studied bridge schematic is preferable.
The output transformer with a middle point is a special feature of the push-pull inverter
schematic – Fig.7.8.b. The transistors turn on in sequence and thus the supply voltage is
applied to each half of the primary winding. Therefore, the secondary voltage alters its sign
each time and changes its value according to the corresponding transform ratio n . The
effective value of the output voltage and its first harmonic are:

(7.14) U L 
1
 n.U d 2 .d  n.U d
 0

U 1LM 2. 2
(7.15) U 1L   .n.U d
2 
The purpose of the antiparallel diodes is analogical to this in the already studied schematics.
The diodes begin to conduct at the moments when control pulses for turning on the transistors
are delivered. The transistors turn on only when the current through the antiparallel diodes
decreases to 0. The above written about the regulation of the half-bridge schema is also valid
here with the only difference that bidirectional controlled power switch has to be connected in
parallel to the primary winding of the transformer. However, this schema is usually used to
implement uncontrolled inverter. The maximum value of the voltage across each power
device in the push-pull schema is equal to 2.U d . For example, when VTA1 turns on the sum of
the supply voltage and the inductive voltage of the right half of the primary winding, also
equal to the source voltage is applied to VTA2 .
Low-number harmonics following the fundamental one – all odd harmonics 3,5,7…
characterize the waveforms of the output voltage of the uncontrolled inverter and of the
controlled inverter in фиг.7.6. This is disadvantage because the inverters require filters of a
large volume and size.
 VT A
Cd1 Ud a
2 iL
ZL
+
Ud O A

-
Cd 2 Ud
2 a
VT A

N
a)
iL
ZL

w2
w2
n
w1

w1 w1

Ud
+
Cd VTA1 VT A2
- a a

N
b)
Fig.7.8. Schema topologies of single-phase voltage-source inverters: a) half-bridge and b)
push-pull schematics

A method of sinusoidal pulse-width modulation is used to eliminate the lower number

harmonics and to improve the harmonic spectra (Mohan, 1995). This method is illustrated in
Fig.7.9 for the half-bridge schema in Fig.7.8.a. Here, the modulation is bipolar because within
a half-period the output voltage changes its polarity. Turning on and off of the power switches
is based on a comparison in the control system of a control sinusoidal voltage uC with
frequency equal to the frequency of the first harmonic of the output voltage (with a period T1 )
to a saw voltage u SAW (with a period TS ), as it is shown in the figure. If the control voltage is
higher than the saw one, the upper device turns on, otherwise the lower switch turns on.
When a switch is on, the load voltage is equal to the half of the source one. The regulation of
the first harmonic value of the output voltage is obtained by changing the ratio of the
amplitudes M A , which can be between 0 and 1. For this purpose, the amplitude of the control
voltage U CM is changed. The maximum value of the first harmonic of the output voltage is
derived using Fig.7.9, as:
Ud
(7.16)
1
U LM  M A.
2
Therefore, the maximum value of the first harmonic of the output voltage depends on the
value of the source voltage and the voltage amplitude ratio.
An important parameter determining the harmonic spectrum is the frequency ratio M f , which
must be an odd number in bipolar modulation. The harmonic spectrum depends on the
coefficient M f and it is presented in Fig.7.10 when M A  0.8 . Lower number harmonics
miss. It appears that with an increase of the switching frequency of the power devices
(increase of M f ), the harmonics shift to the direction of higher frequencies, i.e. their filtering
becomes easier.

uC u SAW U SAW M

t
0
TS U CM
T1
U C  USAW

VТ on , VТ off
 U SAW
U f S T1
U AO  U L
U C MA 
Cм
 0 .8 Mf    15
U L1 U SAW M f 1 Ts
VТ  on , VТ  off

Ud
2
Ud t

0 2

Fig.7.9. Waveforms explaining bipolar sinusoidal pulse-width modulation for the half-bridge
schema in Fig.7.8.a
 ULKM
1.0 Ud
2
0.8

0.6

0.4

0.2 fK
f1

0.0 1 Mf 2 Mf Mf 2 2M f  3 2M f 2M f  3 3M f

2M f 1 2M f 1 3M f 1 3M f 1
Fig.7.10. Harmonic spectrum for bipolar sinusoidal pulse-width modulation

The harmonic values change with a change of M A , i.e. at regulation of the output voltage.
Therefore the shown ratios in Fig.7.10 are valid only when M A  0.8 . The most influence has
always the harmonic with frequency M f . In this amplitude ratio, it is almost equal to the
fundamental harmonic, but in a low values of M A , it may appear higher in value than the
fundamental harmonic. Bipolar sinusoidal pulse-width modulation can be also realized in the
bridge schema in Fig.7.5. The operational algorithm is the following – when the control
voltage is higher than the saw voltage VTA and VTB turn on, otherwise VTB and VTA turn
on. When a pair of power devices is on the whole supply voltage is applied to the load. The
maximum value of the output fundamental harmonic is:
(7.17)
1
U LM  M A .U d
 uC u SAW U SAWM
UC M

0 t

TS
u C T1
U C  U SAW
 
U C  U SAW 
U C  U SAW VTA on, VTA off VTB on, VTB off
U C  U SAW
VTA on, VTA off VTB on, VTB off
U CM f S T2
MA   0.8 Mf    14
U AN U SAWM f 1 T1

Ud
0
t

U BN

Ud
0 t

U AB  U L  U AN  U BN U 1L

0 t

Fig.7.11. Waveforms explaining unipolar pulse-width modulation for the bridge schema in
Fig.7.5

Further improvement of the harmonic spectrum can be achieved by using uni-polar

modulation applied in the bridge voltage-source inverter circuit – Fig.7.11. Here, the
coefficient M f has to be an even number. The operational algorithm is: when the control
 
voltage is higher than the saw voltage VT A turns on, otherwise - VT A . When the control
 
voltage displaced at 180 is higher than the saw voltage VTB turns on, otherwise - VTB .
There are intervals during which the two upper or the two lower devices are simultaneously
on. These are the intervals of the pauses in the output voltage when a power devise conducts
with an antiparallel diode of the devise connected to the same pole of the source voltage
dependent on the load current direction. The equation (7.17) for the maximum value of the
first harmonic of the output voltage is also valid in this case.
Fig.7.12 displays the harmonic spectra for uni-polar sinusoidal PWM. It appears in Fig.7.12
that the harmonics are shifted to the higher frequencies and thus their filtering is simplified.
Compared to Fig.7.10, a frequency bandwidth around M f , 3.M f , etc, misses.

U LKM
1.0 Ud
0.8

0.6

0.4

0.2 fK
f1

0.0 1 Mf 2M f  3 2M f 2M f  3 3M f
2M f  1 2M f  1
Fig.7.12. Harmonic spectrum for uni-polar sinusoidal pulse-width modulation

The method of a selective elimination of harmonics will be examined for the bridge schema in
Fig.7.5 (Chiasson, 2004). The method is designed to eliminate bad harmonic spectrum of the
square waveform of the output voltage and high commutation losses of the sinusoidal pulse-
width modulation. The purpose of this method is to obtain comparatively good harmonic
spectrum of the output voltage using comparatively low commutations and some of lowest odd
harmonics typical for the square waveform of the output voltage to be selectively removed
during this commutations – see Fig.7.13.

UL 1 2 3

U L1
Ud

3
2 

0   2
2
Ud

1 2 3   3   1 4 5 6
  2
Fig.7.13. Waveform of the load voltage in selectively harmonic elimination
Fig.7.13 depicts the waveform of the load voltage. The commutation number and their angles
are chosen in such a way that specific harmonics of the waveform of the output voltage to be
eliminated. Three cuts into negative directions are made at the positive half-period – 1, 2, 3.
Analogical, three cuts are made into positive directions at negative half-period - 4, 5, 6. The
fifth and seventh harmonics of the output voltage waveform are eliminated using three cuts in
a half-period. Using five cuts in a half-period – the fifth, seventh, eleventh and thirteenth
harmonics are eliminated. This method may be applied also in three-phase inverters. As it will
be clarified at the study of the three-phase inverters, the third harmonic and harmonics
divisible to three are mutually compensated and do not exist in the output voltages of the
three-phase inverter because of the properties of a symmetric three-phase system. A special
ratio among the angels 1 ,  2 , 3 in Fig.7.13 has to be observed for the so-studied harmonic
spectrum at regulation of the output voltage to be kept the same. Fig.7.14 explains this ratio.
The ratio of the maximum value of the first harmonic to its maximum possible value is put at
X-axis in Fig.7.14.
1 ,2 ,3
deg
60
3
50

40 2

30
1
20 22,06 
16,24 
10
U 1L
,%
(U 1L ) M
0 20 40 60 80 100
Fig.7.14. Change of the output voltage dependent on angles 1 ,2 ,3 shown is Fig.7.13

The maximum possible value of the first harmonic is:

(7.18) (U 1L ) M  1,188.U d
Disadvantage of the method of the selective elimination of harmonics is that different ratio
among the angles (see Fig.7.14) is required in order to maintain the harmonic spectrum constant
at every change of the output voltage. Contemporary control systems implemented on the basis
of microcontroller or programming logic allow removing this disadvantage. Also, artificial
neuron nets are used (Haque, 2005).

Another method to improve harmonic spectra in voltage-source inverters is modulation of the

output voltage in several levels (Skvarenina, 2002). The electrical schematic of a single-phase
inverter with modulation of the output voltage in several levels is shown in Fig.7.15. Their
U U
number is five - (U d ), ( d ), 0, d , U d . Fig.7.16 depicts the waveform of the output
2 2
voltage across Z L .
Disadvantage of the method of the modulation of the output voltage in several levels is the
increased number of power devices and because of that it has not found a wide
implementation in single-phase inverters. The implementation of the method is wider in three-
phase inverter schemas and in higher powers.

id

VTA1 VT B1

VD A
VDB
Ud
2

Cd1 VTA2 VT 
B2

ZL
+
Ud B
A
-

 
VTA1 VT B1
Ud
2
N
Cd2 VD B
VD A


VT A2 VT B2

Fig.7.15 Bridge schema of a single-phase voltage-source inverter with five levels of

modulation and limiting diodes

U AB

U 1AB
Ud
Ud
2 

Ud

2
Ud
Fig.7.16. The output voltage of the inverter shown in Fig.7.12

Three-Phase Converters

Fig.7.17 displays an electrical schematic of a three-phase voltage-source inverter containing 6

transistors; their antiparallel diodes are also presented. The legs are leg R, leg S and leg T
corresponding to the common point of the two transistors. The transistor symbols are as those
in the single-phase inverters - symbols include subscript of the leg to which it belongs and
upperscript “+” or “-“ indicating whether the transistor has a common point with the positive
or the negative line with the source. Some producers offer the six transistors in the same body.
The control signals of the transistors are marked with low letters corresponding to the leg.
According to the control algorithm the following inverters can be realized by the shown
schematic:
- Three-phase voltage-source inverters with a square waveform of the output voltage;
- Three-phase voltage-source inverters with sinusoidal pulse-width modulation of the
output voltage;
- Three-phase voltage-source inverters with a space-vector pulse-width modulation of the
output voltage;
- Three-phase voltage-source inverters with hysteresis-current control;
- Using a change in the power schema or a combination of several schemas, three-phase
voltage-source inverters with modulation of the output voltage in several levels is
implemented – multilevel inverters.

id

VTR VT S

VT T

r s t

+
Ud Cd R S T

r s t
VT R

VT S VT T

N
ZR ZS ZT

O
Fig.7.17. Electrical schematic of a three-phase voltage-source inverter
Three-phase inverters with square waveform of the output voltage. Let r , s, t as binary
variables are the control signals for the upper transistors. When a signal is 1 than the
corresponding transistor is on, and when a signal is 0 – the transistor is off. Since it is
impossible both phase-leg connected transistors to be simultaneously on, because this would
_ _ _
be a break-mode represented a short-circuit through the transistors to the supply source, r, s, t
are the signals for controlling the lower transistors. Of course, the logical levels of 1 and 0
correspond to the required voltage values to turn on and to maintain the off states of the
transistors – they are usually +15V and -5V. Possible combinations of these three binary
variables are 8, but two of them are not used in the case of a square waveform of the output
voltage. These combinations are 111 – all upper transistors are on, and 000 – the three lower
transistors are on.
Fig.7.18 depicts the six possible combinations of the control signals. Also, the first harmonics
of the corresponding phase and phase-to-phase voltages forming a symmetrical three-phase
system are shown.
It has to be mentioned that the waveforms of the phase voltages regarding point O can be
monitored only if the load is with a taken out star center, which is not available in all loads.
Fig.7.19 shows the equivalent connection schemas of the three-phase loads to the source
voltage corresponding to the six possible combinations of the control signals. Taking in mind
that the load is symmetrical, the values of the phase voltages in each interval are easily found
from the equivalent schematics. For example, in a combination 001 the voltage across Z R is
2 1
.U d , and the voltages across Z S and Z T are (  U d ) . If only a voltage across particular
3 3
loads is studied consequently in all intervals, then the corresponding waveforms in Fig.7.18
can be obtained. The maximum value of the first harmonic of the phase-to-phase voltage can
be derived as:
4  4 3
(7.19) U 1STM  .U d . cos  . .U d  1,1.U d
 6  2
The maximum value of the phase voltage is:
U 1RS M 4 3 1 2
(7.20) U 1ROM   . . .U d  .U d  0,637.U d
3  2 3 
Based on the three phase voltages a space voltage vector can be defined. It is made by
multiplying each phase voltage by an operator giving its space orientation. The space voltage
vector is:
2 4
 
(7.21) VS t   V RO t .e jo  VSO .e
j j
3  VTO .e 3

It is known that:
V RO  V RN  V NO

(7.22) V SO V SN  V NO

VTO  VTN  V NO
The space voltage vector can be also defined on the basis of the three voltages in respect to
the minus of the supply source point N after substituting (7.22) in (7.21) and taking in
2 4
j j
consideration that e j 0  e 3
e 3
 0:
2 4

(7.23) VS t   V RN t .e j 0  VSN e
j j
3  VTN .e 3
 tsr 101 001 011 010 110 100

u RN
VTR VTR
Ud

0  2 
u SN VTS
VTS VTS
Ud
0 
VTT VTT
uTN
VTT Ud

0 
u RS u 1RS
Ud

0 U d 
3
u ST
u 1ST
Ud
0
U d


1
u TR uTR

Ud
0 U d 

u RO 1
Ud u 1RO
3 1
 Ud  2U
3 d
3
0 2
Ud 
u SO 3 1
1 Ud u 1SO
2  Ud 3
 Ud 3
3
0 2
Ud 
3 2
uTO 1
1
uTO Ud
1
 Ud  3Ud
Ud
2 3
3 3
0 
Fig.7.18. Voltage waveforms for the schema in Fig.7.17
 tsr  001 tsr  010
R S

ZR ZS
 
Ud _ O
Ud _ O
Z S ZT Z R ZT

S T R T
tsr  011 tsr  100
R S T

ZR ZS ZT

 O Ud _
Ud _ O
ZT ZR ZS

T R S
tsr  101 tsr  110
R T S T

Z R ZT Z S ZT
 O  O
Ud _ Ud _
ZS ZR

S R
Fig.7.19. Equivalent schematics of a three-phase load for the schema in Fig.7.17

The values of the space voltage vector in the possible combinations of the control signals of
the upper transistors are put in Table.7.1. As it has already been mentioned the first and the
last combinations are not used in the inverters with square waveform of the output voltage.
Thus, the space vector always takes one of the set six positions and its apexes form a regular
hexagon shown in Fig.7.20. The module of the vector is always equal to the source voltage:

(7.24) VS t   U d
2
The maximum value of each phase voltage is equal to of the space vector module or it is
3
2
U d . This coincides with the waveforms in Fig.7.18.
3
Table.7.1.
Control variable Basic vector Value

t s r


0 0 0 V0 (000) 0


0 0 1 V1 (001) U d .e j 0
2
 j
3
0 1 0 V2 (010) Ude
 
j
3
0 1 1 V3 (011) Ude
4
 j
3
1 0 0 V4 (100) Ude
5
 j
3
1 0 1 V5 (101) Ude

1 1 0 V6 (110) U d e j

1 1 1 V7 (111) 0

 
V2 (010 ) V3 (011)

 
V6 (110 ) V1 (001)

 
V4 (100) V5 (101)
Fig.7.20. Positions of the space vector in the case of a square shape of the output voltage

In symmetrical systems the harmonics divisible by 3 are mutually compensated, thus they are
missing in Fig.7.21 that displays the harmonic spectrum of the phase-to-phase voltage of the
three-phase inverter with square waveform of the output voltage. The harmonic numbers in
the figure are determined in accordance with:
(7.25) k  6.n  1 , n  1,2,3.......
The maximum and effective values of the harmonics are:
U 1ABM U 1AB
(7.26) U
K
ABM  U K
AB 
k k
 K
U RSM

Ud
1.2
1.0
0.8
0.6
0.4 fK
0.2 f1
0.0 1 5 7 11 13
Fig.7.21. Harmonic spectrum in the case of a square shape of the output voltage of a three-
phase voltage inverter

The method of the sinusoidal pulse-width modulation illustrated in Fig.7.22 is applied to

improve the harmonic spectra of the output voltage of the electrical schematic in Fig.7.17.
The saw voltage with a high frequency is compared to three control voltages displaced at 120
to each other (one for a phase) with a frequency of the first harmonic of the output voltage.

UC U CR U CS U CT

U RN

U SN

U RS  U RN  U SN
U RS  first harmonic
t

Fig.7.22. Waveforms of a sinusoidal pulse-width modulation in a three-phase voltage-source

inverter
When the control voltages U CА , U CВ , U CС are higher than the saw voltage, the upper
transistors of the corresponding phase turn on and when they are lower – the lower transistors
turn on. In these inverters, the first and the last combination of the control signals are used –
000 – pulses to turn on the three lower transistors and 111 – pulses to turn on the three upper
transistors. Fig.7.22 also depicts the voltages in points A and B in accordance with the minus
of the supply source point N, as well as the phase-to-phase voltage found as a difference
between the two phase voltages. There are three types of conductivity of the power devices
for the three-phase inverters with a sinusoidal pulse-width modulation and active-inductive
load. The two of these types are as in the inverters with a square waveform of the output
voltage. The first is when only transistors conduct – the current id flows from left to right and
active energy is consumed from the supply source. The second is when antiparallel diodes
conduct – the current id flows from right to left and reactive energy is passed back to the
supply source. The third is when all phase voltages in accordance with point N are equal to
U d or 0. In this conductivity type, simultaneously conduct only devices connected to the
positive pole of the source or only devices connected to the negative pole of the source. Thus
the current id is 0, therefore reactive power of the load circulates in the inverter schema.
Similar to the single-phase inverter with sinusoidal pulse-width modulation, here, also the
coefficient M f has to be odd and moreover divisible to 3. Therefore, the harmonic spectrum
of each voltage of point A and point B are identical to those of the single-phase inverter with
bipolar pulse-width modulation – Fig.7.10.
The maximum value of the first harmonic of the phase voltages in accordance with point N is:
Ud Ud
(7.27) U RN M  M A . and U SN M  M A .
1 1
2 2
The first harmonics are displaced at 120. The effective value of the first harmonic of the
phase-to-phase voltage is:
3 U
(7.28) U RS  .M A . d  0.612.M A .U d
1
2 2
Since the switching is with a high frequency, the space vector rotates in spite of setting in one
of the fixed six positions.
Rotating, the apex of the space vector forms a circumference shown in Fig.7.23. In the figure
the hexagonal shape of the output voltage is also shown. The value of the space vector for the
six fixed position in square waveform of the output voltage of inverter is U d , and in
3
sinusoidal pulse-width modulation it is .U d .
4
  
V2 (010 ) V3 (011)

VS t M SINPWM
 
V6 (110 ) V1 (001)

 
V4 (100) V5 (101)
Fig.7.23. Positions of the space vector in sinusoidal pulse-width modulation of the output
voltage

Space-vector pulse-width modulation of the output voltage is realized using the basic
schematic in Fig.7.5 applying an appropriate control. The voltage space vector is defined by
its average value in a switching period for the power devices TS :
2 4

(7.29) VS t   V RN t .e j 0  VSN t .e 3  VTN t .e 3
j j

The six vectors corresponding to the voltage space vector positions in square waveform of the
output voltage form six sectors shown in Fig.7.20. Also, the combination of the control
 
variables corresponding to zero vector V0 (000)  0 and V7 (111)  0 are used.

 Y
axis

V2 (010) V3 (011)

II 
 I VS t 
III
V6 (110)
 X axis
 V1 (001)
V0 (000)  0 IV VI

V7 (111)  0 V
 
V4 (100) V5 (101)
Z axis
Fig.7.24. Explanation of the principle of the space-vector pulse-width modulation of a three-
phase voltage-source inverter

Let us mark as M f the ratio of the period of the first harmonic of the output voltage to the
switching period:
T
(7.30) M f 
TS
2
Then, the space vector will take positions over rad . For a sector the positions will be
Mf
2
over rad . How to determine the module and phase of the space vector in each sector is
6.M f
explained in Fig.7.25 for sector I .
  
i
V3 (011)  Vd .e 3


VS t M

z   
.V0 y.V3 VS
2

V0 (000)  0 S
V7 (111)  0  
z  x.V1 V ( 001)  Vd .e j 0
.V7 1
2
Fig.7.25. Explanation of determining the module and phase of the space-vector
 
The combinations of the control variables corresponding to the basic vectors V1 and V3
bordering the sector are applied for times [Link] and [Link] , respectively. The combinations of
  z
the control variables corresponding to V 0 and V 7 are applied for .TS each. The following
2
equation is valid:
(7.31) x  y  z  1
The average value of the space vector for interval TS is:
 n 1TS 
 
    
1
  1
TS nTS
V
(7.32) S  V S t .dt  [Link] .V 1  [Link] .
V 3  z .0  x.V 1  y .
V 3
TS
After substituting the basic vectors with their values in Table.7.1, it is found:

  j0 j 
(7.33) VS  Vd . x.e  y.e 3 
 
It appears from the equations and in Fig.7.25 that changing z  1  x  y  will change the
y
module of the vector and through changing the ratio - its phase angle  S will change.
x
It is obvious that the space vector has a maximum value in x  y  1 . Fig.7.25 depicts its
1
position in x  y  . After substituting in (7.33) and transformation, the maximum value is
2
found as:

(7.34) VS t M 
3
.U d
2
The apex of this maximum in value space vector will trace a circumference which tangents in
each sector are the lines connected the apexes of the basic vectors of the corresponding sector.
So-formed circumference is shown in Fig.7.26.
  
V2 (010 ) V3 (011)

VS t M SVPWM

VS t M SINPWM
 
V6 (110 ) V1 (001)

 
V4 (100) V5 (101)
Fig.7.26. Positions of the space vector in space-vector pulse-width modulation of the output
voltage

This circumference is the inscribed one in the regular hexagon which apexes are the apexes of
the basic vectors or the positions of the space vector in the square waveform of the output
voltage.
2
The maximum value of each phase voltage is of the value of the space vector or from
3
(7.34) it is found:
1
(7.35) VROM  .U d
3
3
Since the maximum value of the space vector in sinusoidal modulation is U d , using the
4
space-vector pulse-width modulation secures 15% better use of the supply voltage.
In practice values of x and y are found corresponding to a sequence of values of  S . The
following equations are derived using the triangle in Fig.7.22:

VS .2  
x . cos  S  
3  6
(7.36) 
V .2
y  S sin  S
3
If a maximum value of the space vector is maintained and taking in consideration from (7.31)
3
that it referees to the value of the supply voltage of , then from (7.36), it is found:
2
 
x  cos  S  
(7.37)  6
y  sin  S
Shifting consecutively from sector into sector it is known which basic vectors corresponds to
x and y . Calculation and forming of the control signals in real time is made using
appropriate software based on digital signal processors. Therefore, it is very convenient that
the component x to be identify as axis r , s, t in series.

In the three-phase inverters with a hysteresis-current control the transistor control is realized
on the base idea explained in Fig.7.27( Mohan, 1995). The purpose in this control is to obtain
sinusoidal currents in the three-phases. The basic part of the control system for the transistors
in phase R is shown. The control channels for the other two phases contain the same blocks.
Three sine waves forming a symmetrical three-phase system with a frequency equal to the
fundamental harmonic are passed to the corresponding channels as reference sinusoidal
waveforms. The sine wave i Rref is the reference one for the channel R. It is continuously
compared to the transitory value of the current i R gained through a current sensor CS R . The
comparison is made with a hysteresis and it is explained in Fig.7.28. If the current has to
increase in accordance with the transitory value of the reference sinusoidal wave, the upper
transistor turns on. At the reach of the upper border of the hysteresis, the lower transistor turns
on because the current should already to be reduced in accordance with the reference sine
wave. The control signal for the upper transistor is shown in Fig.7.28 – signal r . This
operational principle is realized during the whole period also for the other two phases. The
switching is with a high frequency.

id

VT R VT S

VT T

r s t

+ R S T
Ud Cd iT
ZT
-
CS T
r s t
 
VT R VT S VT T
iS ZS
N
CS S O

iR
r r ZR
CS R

Drivers

i
Rref

Fig.7.27. Schema to realize hysteresis-current control

i Rref iR H
iR
i Rref



Fig.7.28. Waveforms illustrating the hysteresis-current control

Other methods to control and regulate the voltage inverters are known, for example, sliding
mode control ( Carpita, 1994) and predictive current control (Abu-Ruh, 2004).
Regardless the implementation and the element base – analogue, digital, based on
microcontrollers, special integrated circuits or digital signal processors, the secured functions
from the control systems connected to the voltage-source inverter operations are the same.
Fig.7.29 displays a general structural schema of a control system describing the required basic
function. The pulses for the gates of the power transistors in the inverter schema are delivered
from a driver blocks securing the required levels of signals to turn on and off the device and
also securing a galvanic isolation. The electrical schemas of these blocks are many and
different. Moreover, in the “intelligent power modules” the drivers are embedded in the same
body with the transistors. The basic signals connected with the operation of the power schema
and the load supplied by the inverter are monitored using feedbacks – current and voltage
transformers, Hall sensors, optoelectronic circuits, current and voltage transducers, etc. Of
course, their number and type are defined by the particular implementation.

LOGICAL
PWM
GENERATION pulses PROCESSING DRIVERS
DISTRIBUTION
sign
half-period POWER
SHEMATIC
regulation  f OUT LOAD
REGULATION
SYSTEM SENSORS
regulation  М А

Fig.7.29. General structural schema of a control system

The signals received from the feedbacks are processed by the regulator system including
appropriate regulators and regulators algorithms. The output signals of this system
characterizing the voltage-source inverters such as regulation of the first harmonic of the
output voltage and its value regulation are conventionally shown. The functions of the
generator block are general. It generates pulse-width pulses, as well as a signal with the
fundamental harmonic of the output voltage but with different value in the two half-periods.
These two signals after logical operations are distributed to the transistor drivers. As it is in
each power electronic converter, here, also special measurements are provided for break-
down mode protections, as well as a suitable indication of the basis states and parameters. The
last mentioned functions are obligatory but they are not separately shown in Fig.7.29. Part of
the protection measurements are sometimes provided in the drivers.
The comparatively easiest implementation of the control system is that of the single-phase
bridge inverter in Fig.7.5.

M f . f OUT
SawVG
synchro.
.
PWM
 pulses
M f . f OUT
C
FD 
PLL
M f sign
f OUT f OUT half-period

regulation  M A

ragulation  f OUT SVG

f OUT

Fig.7.30. Structural schema to implement a sinusoidal pulse-width modulation

Fig.7.30 displays a block schema, which operation is the closest to the implementation way of
the shown in Fig.7.8 – a comparison of a saw voltage with a high frequency to a sinusoidal
waveform, whose frequency is equal to this of the first harmonic of the output voltage. The
symbols in Fig.7.30 are in accordance with the symbols in Fig.7.9.
The sinusoidal voltage generator (SVG) may be implemented using analogue integrated
circuits or combination of analogue and digital methods and it has two output signals. The
first is the sinusoidal voltage, which is passed to the non-inverting input of the comparator C,
and the second – a voltage with a saw waveform with a different sign in its two half-periods.
The second signal can be obtained of the sinusoidal voltage using a comparator with a zero
threshold. A phase locked loop (PLL) circuit is available. The pulses in its output are with
frequency M f times higher than this of the sinusoidal voltage because of the connected
frequency devisor (FD). The saw voltage generator (SawVG) generates a voltage of a saw
waveform and it passes the voltage to the inverting input of the comparator. The operation of
SawVG is synchronized to the output pulses of PLL-circuit. At the output of the comparator, a
sequence of pulses is produced, as it is shown in Fig.7.30. In applications where a regulation
of the output voltage frequency is not required, the schema can be simplified and the PLL
block can be removed. The necessity to regulate the frequency of SVG, as well as the input
signal for this regulation, is also eliminated. When the ratio M f is very high, i.e. the
frequency of the saw voltage is many times higher than this of the sinusoidal voltage, the error
of the lack of a precise synchronization does not significantly reflect on the waveform of the
output voltage and SawVG can be without a synchronization input. All these simplifications
can be made after an assessing of the requirements of the inverter load.
The shown principle is applicable also in three-phase inverters with pulse-width modulation,
as it has been described in Fig.7.22. In this case, SVG has to generate three sinusoidal
waveforms displaced to each other at 2 rad. The three sine waves have to be passed to
3
three comparators at the other inputs of which a signal of a common SawVG should be
delivered.
A possible conception at using microprocessor systems is to bring the function of generation
of the pulse-width modulation signals in a special peripheral chip to use minimum resources
of the control processor. The firm GEC Plessey has offered at the market the integrated circuit
МА838 of a single-phase generator of pulse-width modulation pulses in accordance with a
sinusoidal law (GEC Plessey Semiconductors, 1995). The IC is compatible with
microprocessors and microcontrollers of Intel and Motorоla. The structural schema of the IC
is shown in Fig.7.31. It has two outputs with TTL-levels. They are used to control upper and
lower transistor of an inverter leg via a driver. Regardless of inner register states, both outputs
are in low level when a low level signal is passed to the input TRIP . This input is used to
protect the inverter of current overloading. At the same time at the output SETTRIP a high
level is set that indicates the prohibition of the pulses to the power transistors. This state is
maintained till a circuit reset is performed by a low level at input RST .
МА838 generates pulses with a required waveform for both transistors directly from inner
memory ROM and requires influence of a control processor only to change the parameters of
these signals. The change is made through a standard 8-bit multiplexed bus for address/data
SYSTEM BUS of MOTEL1 type, compatible with the most widely spread microprocessors
and microcontrollers. Using this bus, signal CS and signal for interface MOTEL1 , the IC is
programmed as a peripheral chip for the microprocessor system. The programming is made
using special inner registers. There is a possibility to set the output frequency and the
modulation coefficient, minimum duration of the pulses and “dead” time, as well as to change
the carrying frequency at modulation. The accuracy of setting the output frequency
corresponds to 12-bit. The frequency can be changed to 4 kHz ; the carrying frequency can be
chosen to 24 kHz . The written data in the inner permanent memory corresponds to a bipolar
sinusoidal pulse-width modulation as one shown in Fig.7.8.
The contemporary microprocessors combine most of the functions to generate pulse-width
modulation pulses sequences through very well developed timer systems and with wide
abilities of programming control. This has become possible by the simultaneous increase of
their fast reaction to be good enough to obtain a required accuracy and discreet level. The
series of the width modulated pulses may be preliminarily written in the series of memory
cells, as it is proposed in (Maurice, 1992).
Fig.7.31. Structural schema of a special integrated circuit МА838
Source: ©Gec Plessey Semiconductor 1995, Publication No DS3798 Issue No 3.1,
July 1995

A special feature of the three-phase voltage-source inverters with a space-vector pulse-width

 
modulation is a presence of six active vectors V1  V6 (at which a DC voltage is applied to the
 
load) and two zero vectors V0 ,V7 (at which a DC voltage is not applied to the load). Other
feature both to single-phase and three-phase voltage-source inverters is a prohibition of
simultaneously turning on of both phase-leg devices, because of the input circuit impedance
this would lead to a short-circuit for the source. A simultaneously turning on of both phase-
leg devices is allowed only in resonant DC-link inverters where a resonance process is
developed caused by the elements connected in the input.
In the Z - source inverters one additional zero vector is added to the two zero vectors. The
new zero vector corresponds to a simultaneously turning on of both phase-leg devices and no
voltage is applied to the load. This is made without a danger of breaking the power devices
because of the impedance of the inner circuit. Additionally, in this case as a result a DC
supply voltage to the inverter is gained and also the voltage is higher than the output voltage
of the DC source. I.e. if the DC source voltage is low, the medial boost high-frequency
DC/DC converter or a connection of boost low-frequency transformer in the output of the
inverter is not necessary. The principle is applicable also in the single-phase inverters.
An electrical schematic of a three-phase Z-source inverter is shown in Fig.7.32 (Huang,
2006). It contains passive elements in its input - L1 , L2 , C1 , C2 , which elements form so-called
Z-source. The connection of diode VD is obligatory in using DC voltage, which current
should not change its direction, for example fuel cell. Since the voltage in the input of the Z-
source may become higher than the DC source voltage U DC in particular intervals, the diode
is connected.
 Z  source id
VD
L1
VT R VT S VT T

r s t

+ R S T
C2 C1
UD
C
-

r s t
  
VT R VT S VT T
L2
N

ZR ZS ZT

O
Fig.7.32. Electrical schematic of a three-phase Z-source inverter

If a switching period TS is divided into two parts Ta and Tb , where in Ta corresponds to the
time during which both phase-leg devices are on, and taking in consideration (7.28), the
following equation is found:
TS  Ta  Tb
Ta T
a ,b  b
(7.38) TS TS
x yz b
ab 1
Equivalent schemas illustrating the operation of the inverter shown in Fig.7.32 are presented
in Fig.7.33. The first equivalent schema Fig.7.33.a corresponds to the third zero vector when
both phase-leg devices are on, and the second one – Fig.7.33.b – to the rest eight vectors.

L1 L1
   
    
 
C1  
ui ud id U DC ud id
ui  
C2 C2 C1
 
    
   
L2 L2
a) b)
Fig.7.33 Equivalent schemas illustrating the operation of the inverter in Fig.7.29
The values of the two inductances are equal as well are the values of the two capacitors.
Therefore, they can be made in a common core also because of the inductance voltage
polarities.
Using Fig.7.33.a the following equations can be written:
di
U C1  uL1  L1 d
dt
di
(7.39) U C 2  ul 2  L2 d
dt
U C1  U C 2  U C ; uL1  uL 2  uL
Since the DC capacitor voltages are applied to the inductances, their currents increase in
accordance with a linear law.
Using Fig.7.33.a for Ta is found:
ui  2.U C
(7.40)
ud  0
For the rest intervals included in Tb , it is found from Fig.7.33.b:
uL  U DC  U C
(7.41)
ud  U C  uL  2.U C  U DC
Across the inductances a DC voltage is applied again and the inductance currents decrease in
accordance with a linear law.
Since the voltage across each inductance during a switching period is zero, it is found:
T .U  Tb .U DC  U C 
TS

U L  0   u L .dt  a. C
0 TS
Ta
(7.42) 1
Tb TS
UC  .U DC  .U
Tb  Ta 1 2
Ta DC
TS
Using similar approach, the average value of the input inverter voltage is obtained as:
Ta .0  Tb .2U C  U DC 
TS

(7.43) U d   ud .dt 
0
TS
After substituting U C from (7.42) in (7.43) and transformations, the following equation is
derived:
Tb
(7.44) U d  .U DC  U C
Tb  Ta
Therefore, the voltage of one of the capacitors can be monitored as a feedback for the value of
the input inverter voltage. Using (7.41) and (7.44), the highest value of this voltage during
interval Tb is found as:
TS 1
(7.45) U dM  2.U C  U DC  .U DC  K .U DC  .U
Tb  Ta 1 2
Ta DC
TS
As it appears form (7.45), К  1 and it may be called an increasing coefficient, i.e. during Tb
at the input of the inverter an increased voltage dependent on the time Ta will be applied.
Therefore, a medial high-frequency transformation of the DC source voltage is not required.
During Tb a modulation to regulate the output inverter voltage is made, and, for example, if
the modulation is a sinusoidal one, the maximum phase voltage is:
(7.46) U 1ANM  M A .U dM  M A .K .U DC
It appears from (7.46) that the regulation of the output inverter voltage can be obtained by the
two coefficients К and М А . But one have to take in mind that the two coefficients are
mutually connected by the equation (7.38) a  b  1 .

Methods to Improve Power Efficiency in DC/AC Conversion

Use of zero voltage switching and zero current switching is also possible in inverters to
reduce power losses across the power switches and to increase the efficiency coefficient
(Heumann, 1994). As an example, transistor resonant inverter with active load shown in
Fig.7.34 may be examined.

id

VTA+ VDA+ VT B+ VD+B

uC iL
+
Ud A B
Cd
C L RL
-
-
VTA VDA- VTB-
-
VD B

Fig.7.34. Electrical schematic of a bridge transistor resonant inverter

Of course, other load variants are possible dependent on the inverters purpose – more often a
parallel oscillating circuit. It is also possible the use of output transformer, whose primary
inductance is a part of the inductance L . Other possibility is to connect a high-frequency
rectifier at the transformer side thus DC/DC converters with resonance switching are obtained.
The load may be connected in different ways to the resonance circuit. These converters are not
a subject of examination in this chart, therefore, it is assumed at the description of operational
features of the inverter that elements connected between points A and B are only the ones shown
in the Fig.7.34. Fig.7.35 depicts waveforms of current through the bridge diagonal iL and
capacitor voltage uC in several typical operational modes dependent on the ratio of switching
frequency of the transistors S to resonance frequency of the series circuit 0 . Devices that
conduct during different intervals are marked. It has to be mentioned that the first three modes
are realizable also in thyristor inverters with antiparallel diodes. After a decrease of a current
through diagonally connected transistors, their antiparallel connected diodes are turned on.
Discontinuous-conduction current mode with turning off at zero current both the transistors and
diodes is achieved if the next transistor pair is turned on with a delay in accordance with the
decrease of diode current to 0. If the switching frequency is half of the resonance one
S  0.50 - second diagrams, the switching also happens at zero current, but the load current
is continuous. In the third mode when 0.50  S  0 , zero current switching is only for the
transistors, because they are turned on before the decreasing of the diode current to zero. The
forth mode is resonance mode and it is achieved only in the transistor inverters because in them
a reverse recovery time is not necessary, as it is in the thyristor inverters. The next pair of
transistors is turned on as soon as the current through the pair, which has been conducting till
that moment, decreases to zero. And in ideal case, the antiparallel diodes are not necessary.
Although, since delays and inaccuracies of the transistor switching are always possible to
appear, the diodes are required. Furthermore, the resonance mode is maintained with a specified
accuracy and there is time to achieve the mode in transient processes. The last operational mode
is very interesting – switching above the resonance frequency. Pulses to turn off the conducting
transistor pair and to turn on the next one are passed before the transistor current decreases to
zero. At first, the antiparallel connected diodes to the transistor pair, which has been received
the on signals, begin to conduct. The transistors begin to conduct only when the diode current
decreases to zero. For example, after the turning off of VTA , VTB and the passing of turning on
signals to VTB , VTA , at first, diodes VDB , VDA begin to conduct and after the diode current
decreases to 0 the transistors VTB , VTA begin to conduct. It is clear that a mode of turning off
at zero current is realized for the diodes and also a mode of turning on at zero voltage is realized
for the transistors because the transistor antiparallel connected diode has been conducting at the
start of the transistor conductive interval. In this mode it is possible to use as clamp elements
for the devices only capacitors in parallel to the devices because at the turning on of the
transistors the capacitors will be discharged and it is not necessary to limit their discharged
current. Thus, dissipating of active power in other elements of a clamp group is avoided [44].
It is clarified from the study made and from the waveforms in Fig.7.35 that load power of the
inverter can be regulated using the described operational modes. For this purpose, the control
pulses frequency of the power devices in respect to the resonance frequency has to be changed
using the control system. This is so-called pulse frequency modulation (PFM) or frequency
regulation.
Fig.7.36 describes another way to change the load power - pulse density modulation (PDM).
The voltage of the output of the inverter bridge – between points A and B u AB , as well as load
current iL are shown in the figure - u AB . A special feature of this modulation is the appearance
of an interval during which the voltage across the resonance circuit becomes equal to 0. This
interval is achieved by simultaneously delivering of on signals to both lower or both upper
transistors in the schematic. Thus, conditions for free fading oscillations of the load current
flowing through a transistor and an antiparallel diode of the other transistor are created in one
of the half-periods, conditions for a change of the transistor and diode of the other half-period
are also secured. During the rest of the time a resonance mode is maintained when the
diagonally connected transistors are turning on. To be able to be reached and to be maintained
the resonance mode, the control frequency is required to be changed in case of a load change
and also during transient modes. Therefore, the control system should have the possibility for
frequency-pulse modulation. It is necessary to mention the difference between this mode and
the mode of discontinuous conduction current through the load examined in the first diagrams
shown in Fig.7.35. The voltage between the point A and B is also zero in the previously
examined mode (see Fig.7.35) but current through the load does not flow. At a scrutiny look
upon the operation of the transistor inverter in the PDM mode, it can be seen that since the
antiparallel diode of one of the next to conduct diagonally connected transistors has been
conducting, the transistor turns on at zero voltage after the interval of zero voltage in the bridge
diagonal. This transistor is the one that has been used during the voltage pause. There are two
possibilities to regulate load power: the first is to maintain the interval of a normal operation of
the resonant inverter constant (for example, fixed period number) and to change the duration of
the interval during which the voltage of the bridge diagonal is zero; the second is to change the
interval of a normal operation of the resonant inverter constant (for example, changeable period
number) and to maintain the duration of the interval during which the voltage of the bridge
diagonal is zero constant.

VTA VDA VTB VDB VTA VDA VTB VDB

uC VTB VDB VTA VDA uC VTB VD  VT  VD 
i B A A
iL L

uC uC
iL iL
 
0  2 0  2
T0
T0
TS TS

TS  2.T.0 ;  S  0.50 TS  2.T0 ;  S  0.50

VTA VDA VTB VDB

uC VTB VDB VTA VDA
iL
iL
uC


 2
0

T0
TS
T0  TS  2.T0 ; 0   S  0.50
VT  VTB  
VTA VDB VTB VDA
A
uC VT B
 VTA uC VTB VDA VTA VDB
iL iL
iL uC iL
uC
 
0
 2 0  2

TS  T0 TS
T0
TS  T0 ;  S  0 TS  T0 ;  S  0
Fig.7.35. Waveforms illustrating the operation of the bridge transistor resonant inverter
shown in Fig.7.34
 u AB

iL

Fig.7.36. Waveforms illustrating pulse density modulation

Use of resonance modes in voltage-source inverters is also possible. More detailed description
can be found for example in (Skwarenina, 2002; Bose, 2007).
As it has been clarified by the voltage inverter operational principle and by the output voltage
waveform dependent on the modulation, the waveform is characterized by different harmonic
spectrum. This presumes some special features at measurement of the output active power
corresponding to (7.1) and the efficiency coefficient connected to this power, especially in the
three-phase inverters. The measurement of input and output powers is convenient to be made
using a special digital measurement device (Marrinan, 2007).

1. MOTEL is trademark of Motorola Corp. and Intel Corp.

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