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Understanding Expansion Bus Systems

An expansion bus allows information to move between a computer's CPU, RAM, and peripheral devices like monitors and printers. It consists of wires and protocols that enable expansion of the computer's capabilities. Early computer buses were bundles of wires connecting memory and peripherals. Later buses separated the CPU/memory world from devices, and added features like higher data transfer rates and plug-and-play configuration. Modern third generation buses are more like networks, allowing flexible internal and external connections at very high speeds.

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100% found this document useful (1 vote)
241 views6 pages

Understanding Expansion Bus Systems

An expansion bus allows information to move between a computer's CPU, RAM, and peripheral devices like monitors and printers. It consists of wires and protocols that enable expansion of the computer's capabilities. Early computer buses were bundles of wires connecting memory and peripherals. Later buses separated the CPU/memory world from devices, and added features like higher data transfer rates and plug-and-play configuration. Modern third generation buses are more like networks, allowing flexible internal and external connections at very high speeds.

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Expansion Bus

An expansion bus is made up of electronic pathways which move information from your
CPU and RAM to all of your other peripheral devices such as a microphone, monitor,
telephone line, and printer, which all connect to ports on the back of your computer. It
is a collection of wires and protocols that allows for the expansion of a computer.[1]

To make sense of all of this, let’s look at the example as a whole. Firstly, you use a
parallel connector, where you would plug your printer, telephone line, monitor, or
microphone into your personal system box. Your expansion card will connect to the
expansion bus through the expansion slot. This in turn, may move information along the
line through devices such as your RAM or CPU chip.

First generation

Early computer buses were bundles of wire that attached memory and peripherals. They
were named after electrical buses, or busbars. Almost always, there was one bus for
memory, and another for peripherals, and these were accessed by separate instructions,
with completely different timings and protocols.

One of the first complications was the use of interrupts. Early computers performed I/O
by waiting in a loop for the peripheral to become ready. This was a waste of time for
programs that had other tasks to do. Also, if the program attempted to perform those
other tasks, it might take too long for the program to check again, resulting in lost data.
Engineers thus arranged for the peripherals to interrupt the CPU. The interrupts had to
be prioritized, because the CPU can only execute code for one peripheral at a time, and
some devices are more time-critical than others.

Some time after this, some computers began to share memory between several CPUs.
On these computers, access to the bus had to be prioritized, as well.

The classic, simple way to prioritize interrupts or bus access was with a daisy chain.

DEC noted that having two buses seemed wasteful and expensive for small, mass-
produced computers, and mapped peripherals into the memory bus, so that the devices
appeared to be memory locations. At the time, this was a very daring design. Cynics
predicted failure.

Early microcomputer bus systems were essentially a passive backplane connected to the
pins of the CPU. Memory and other devices would be added to the bus using the same
address and data pins as the CPU itself used, connected in parallel. In some instances,
such as the IBM PC, instructions still generated signals at the CPU that could be used to
implement a true I/O bus.

In many microcontrollers and embedded systems, an I/O bus still does not exist.
Communication is controlled by the CPU, which reads and writes data from the devices
as if they are blocks of memory (in most cases), all timed by a central clock controlling
the speed of the CPU. Devices ask for service by signalling on other CPU pins, typically
using some form of interrupt.

For instance, a disk drive controller would signal the CPU that new data was ready to be
read, at which point the CPU would move the data by reading the memory that
corresponded to the disk drive. Almost all early computers were built in this fashion,
starting with the S-100 bus in the Altair, and continuing through the IBM PC in the
1980s.

These simple bus systems had a serious drawback for general-purpose computers. All
the equipment on the bus has to talk at the same speed, and thus shares a single clock.

Increasing the speed of the CPU is not a simple matter, because the speed of all the
devices must increase as well. This often leads to odd situations where very fast CPUs
have to "slow down" in order to talk to other devices in the computer. While acceptable
in embedded systems, this problem was not tolerated for long in commercial computers.

Another problem is that the CPU is required for all operations, so if it becomes busy
with other tasks, the real throughput of the bus could suffer dramatically.

Such bus systems are difficult to configure when constructed from common off-the-shelf
equipment. Typically each added PC board requires many jumpers in order to set
memory addresses, I/O addresses, interrupt priorities, and interrupt numbers.

Second generation

"Second generation" bus systems like NuBus addressed some of these problems. They
typically separated the computer into two "worlds", the CPU and memory on one side,
and the various devices on the other, with a bus controller in between. This allowed the
CPU to increase in speed without affecting the bus. This also moved much of the burden
for moving the data out of the CPU and into the cards and controller, so devices on the
bus could talk to each other with no CPU intervention. This led to much better "real
world" performance, but also required the cards to be much more complex. These buses
also often addressed speed issues by being "bigger" in terms of the size of the data path,
moving from 8-bit parallel buses in the first generation, to 16 or 32-bit in the second, as
well as adding software setup (now standardised as Plug-n-play) to supplant or replace
the jumpers.

However these newer systems shared one quality with their earlier cousins, in that
everyone on the bus had to talk at the same speed. While the CPU was now isolated and
could increase speed without fear, CPUs and memory continued to increase in speed
much faster than the buses they talked to. The result was that the bus speeds were now
very much slower than what a modern system needed, and the machines were left
starved for data. A particularly common example of this problem was that video cards
quickly outran even the newer bus systems like PCI, and computers began to include
AGP just to drive the video card. By 2004 AGP was outgrown again by high-end video
cards and is being replaced with the new PCI Express bus.

An increasing number of external devices started employing their own bus systems as
well. When disk drives were first introduced, they would be added to the machine with a
card plugged into the bus, which is why computers have so many slots on the bus. But
through the 1980s and 1990s, new systems like SCSI and IDE were introduced to serve
this need, leaving most slots in modern systems empty. Today there are likely to be
about five different buses in the typical machine, supporting various devices.

A useful differentiation then became popular, the concept of the local bus as opposed to
external bus. The former referred to bus systems that were designed to be used with
internal devices, such as graphics cards, and the latter to buses designed to add external
devices such as scanners. Note, though, that "local" also referred to the greater
proximity to the processor of VL-Bus and PCI than ISA. IDE is an external bus in terms
of how it is used, but is almost always found inside the machine.

Third generation

"Third generation" buses are now in the process of coming to market, including
HyperTransport and InfiniBand. They typically include features that allow them to run
at the very high speeds needed to support memory and video cards, while also
supporting lower speeds when talking to slower devices such as disk drives. They also
tend to be very flexible in terms of their physical connections, allowing them to be used
both as internal buses, as well as connecting different machines together. This can lead
to complex problems when trying to service different requests, so much of the work on
these systems concerns software design, as opposed to the hardware itself. In general,
these third generation buses tend to look more like a network than the original concept
of a bus, with a higher protocol overhead needed than early systems, while also allowing
multiple devices to use the bus at once.

On another track, integrated circuits are increasingly being designed from predesigned
logic, "intellectual property." Buses such as Wishbone have been developed to permit
devices on integrated circuits to talk to one another.

Description of a bus

At one time, "bus" meant an electrically parallel system, with electrical conductors
similar or identical to the pins on the CPU. This is no longer the case, and modern
systems are blurring the lines between buses and networks.

Buses can be parallel buses, which carry data words striped across multiple wires, or
serial buses, which carry data in bit-serial form. The addition of extra power and control
connections, differential drivers, and data connections in each direction usually means
that most serial buses have more conductors than the minimum of two used in the I²C
serial bus. As data rates increase, the problems of timing skew and crosstalk across
parallel buses become more and more difficult to circumvent. One partial solution to
this problem has been to double pump the bus. Often, a serial bus can actually be
operated at higher overall data rates than a parallel bus, despite having fewer electrical
connections, because a serial bus inherently has no timing skew or crosstalk. USB,
FireWire, and Serial ATA are examples of this. Multidrop connections do not work well
for fast serial buses, so most modern serial buses use daisy-chain or hub designs.

Most computers have both internal and external buses. An internal bus connects all the
internal components of a computer to the motherboard (and thus, the CPU and internal
memory). These types of buses are also referred to as a local bus, because they are
intended to connect to local devices, not to those in other machines or external to the
computer. An external bus connects external peripherals to the motherboard.

Network connections such as Ethernet are not generally regarded as buses, although the
difference is largely conceptual rather than practical. The arrival of technologies such as
InfiniBand and HyperTransport is further blurring the boundaries between networks
and buses. Even the lines between internal and external are sometimes fuzzy, I²C can be
used as both an internal bus, or an external bus (where it is known as [Link]), and
InfiniBand is intended to replace both internal buses like PCI as well as external ones
like Fibre Channel.

Modern trends in personal computers, especially laptops, have been moving towards
eliminating all external connections except for modem jack, Cat5, USB, headphone jack,
and optional VGA or FireWire.

Bus topology

In a network, the master scheduler controls the data traffic. If data is to be transferred
the requesting computer sends a message to the scheduler, which puts the request into a
queue. The message contains an identification code which is broadcast to all nodes of
the network. The scheduler works out priorities and notifies the receiver as soon as the
bus is available.

The identified node takes the message and performs the data transfer between the two
computers. Having completed the data transfer the bus becomes free for the next
request in the scheduler's queue.

Bus benefit: any computer can be accessed directly and message can be sent in a
relatively simple and fast way. Disadvantage: needs a scheduler to assign frequencies
and priorities to organize the traffic.

Examples of internal computer buses

Parallel

• ASUS Media Bus proprietary, used on some ASUS Socket 7 motherboards


• CAMAC for instrumentation systems
• Extended ISA or EISA
• Industry Standard Architecture or ISA
• Low Pin Count or LPC
• MicroChannel or MCA
• MBus
• Multibus for industrial systems
• NuBus or IEEE 1196
• OPTi local bus used on early Intel 80486 motherboards.
• Peripheral Component Interconnect or PCI
• S-100 bus or IEEE 696, used in the Altair and similar microcomputers
• SBus or IEEE 1496
• VESA Local Bus or VLB or VL-bus
• VMEbus, the VERSAmodule Eurocard bus
• STD Bus for 8- and 16-bit microprocessor systems

Serial

• 1-Wire
• HyperTransport
• I²C
• PCI Express or PCIe
• Serial Peripheral Interface Bus or SPI bus
• USB Universal Serial Bus
• FireWire [Link] or IEEE 1394

Examples of external computer buses

Parallel

• Advanced Technology Attachment or ATA (aka PATA, IDE, EIDE, ATAPI, etc.)
disk/tape peripheral attachment bus
(the original ATA is parallel, but see also the recent serial ATA)
• USB Universal Serial Bus, used for a variety of external devices
• HIPPI HIgh Performance Parallel Interface
• IEEE-488 (aka GPIB, General-Purpose Instrumentation Bus, and HPIB, Hewlett-
Packard Instrumentation Bus)
• PC card, previously known as PCMCIA, much used in laptop computers and other
portables, but fading with the introduction of USB and built-in network and
modem connections
• SCSI Small Computer System Interface, disk/tape peripheral attachment bus

Proprietary

• Floppy drive connector


Examples of internal/external computer buses

• Futurebus
• InfiniBand
• QuickRing
• SCI

Common questions

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Advancements in bus systems have greatly improved the handling of data traffic and device communication over early systems. Earlier buses faced limitations due to their shared clock speed and required all devices to operate at the same speed, which often resulted in bottlenecks . In contrast, modern systems, especially with the advent of third-generation buses, facilitate asynchronous communication, allowing devices to operate at their own speeds while supporting complex scheduling and data traffic management . Modern buses can handle multiple data transfers simultaneously due to their network-like architectures and advanced protocol overheads, which drastically increase real-world throughput and efficiency compared to the single-threaded operation of early bus systems .

Modern advancements in bus systems have blurred the lines between traditional buses and network architectures through several innovations. Technologies like InfiniBand and HyperTransport operate at high speeds necessary for memory and video cards, similar to network data rates, while also supporting devices of varying speeds . They allow multiple devices to communicate simultaneously, resembling network data traffic management rather than the sequential data transfer typical in older bus systems . The inclusion of sophisticated protocol overheads and flexible physical connections further aligns them with network architectures, supporting both internal and external communications and emphasizing the network-like role of managing data traffic .

First-generation computer bus systems faced challenges such as the need for all equipment on the bus to communicate at the same speed, which required sharing a single clock, leading to inefficiencies when increasing the CPU speed . Additionally, these systems suffered from inefficiencies due to the CPU being required for all operations, which meant that the real throughput of the bus could decline significantly if the CPU was busy with other tasks . This necessitated the use of interrupts to prioritize tasks, but the absence of sophisticated scheduling could still result in lost data . These limitations made first-generation buses inefficient for general-purpose computers, as they were unable to cope with the speed increases of CPUs and peripherals .

The evolution from parallel to serial bus systems was largely driven by the rising issues of timing skew and crosstalk observed as data transfer rates increased in parallel buses. Parallel buses, with their multiple wires carrying data words simultaneously, faced significant challenges in managing these electrical disturbances, leading to data integrity issues . Serial buses, in contrast, transmit data sequentially over fewer connections, inherently avoiding timing skew and crosstalk, and can achieve higher data rates despite having fewer conductors . This transition, exemplified by the adoption of technologies like USB and FireWire, also allowed for more flexible, daisy-chain, or hub designs .

Second-generation bus systems, such as NuBus, improved upon earlier limitations by separating the CPU and memory from other devices with a bus controller, allowing the CPU to increase in speed independently . This enabled devices on the bus to communicate without CPU intervention, improving real-world performance. These systems also improved data path sizes from 8-bit to 16 or 32-bit and incorporated software setup to replace hardware jumpers . However, challenges remained, such as the requirement that all devices still communicate at the same speed, which caused slower bus speeds compared to CPU and memory advancements, leading to data throughput bottlenecks .

The integration of bus controllers in second-generation systems fundamentally changed computer architecture by acting as a bridge between the CPU/memory and peripheral devices. This separation allowed the CPU to function independently of the bus speeds, which facilitated significant increases in CPU performance without directly affecting peripheral communication . The controller managed data transfers between devices, reducing the CPU's load and enabling peripheral interactions without CPU involvement, resulting in better overall efficiency . This architectural change laid the groundwork for further advancements in system design, such as increased data throughput and more sophisticated peripheral operations .

Separating CPU and peripheral speeds in second-generation bus systems allowed system designers to focus on improving CPU efficiency without being limited by peripheral communication speeds . While this architectural change enhanced CPU performance and streamlined data management, it necessitated more complex designs for peripheral cards, as they had to incorporate additional logic for communication independent of CPU clock speeds . This provided better overall system performance but also increased the complexity and cost of peripheral device manufacturing, presenting new challenges in balancing performance and system cost .

Third-generation bus systems, like HyperTransport and InfiniBand, significantly enhanced the flexibility and efficiency of modern computing devices by supporting very high speeds necessary for memory and video cards, while maintaining compatibility with slower peripherals like disk drives. These systems resemble networks more than traditional buses, with the capability to handle multiple requests simultaneously, reducing bottlenecks . Their flexible physical connections allow them to serve as both internal and external buses, further enhancing versatility. However, increased protocol complexity can complicate software design, indicating a shift from hardware to software challenges . This complexity allows better management of data traffic and prioritization, ultimately improving the efficiency of computing devices .

Interrupts played a crucial role in the evolution of early computer bus systems by improving CPU efficiency. Initially, CPUs had to wait for peripheral devices to become ready, wasting processing time and risking data loss if other tasks were prioritized . The introduction of interrupts allowed peripheral devices to signal the CPU when they were ready to communicate, enabling the CPU to perform other operations in the meantime. This prioritized signal system ensured that time-critical tasks could preempt less urgent ones, greatly enhancing operational efficiency and setting the foundation for complex multitasking in modern computers .

The introduction of Plug-n-Play systems significantly enhanced second-generation bus technologies by simplifying the configuration process. Before Plug-n-Play, setting up peripherals required manual configuration through jumpers for setting memory addresses, I/O addresses, and interrupt priorities, which was both time-consuming and error-prone . Plug-n-Play automated these setups, allowing systems to automatically recognize and configure peripherals without user intervention, reducing setup complexity and facilitating easier hardware upgrades and expansion. This advancement further improved the accessibility and usability of computing systems, encouraging broader adoption and innovation in personal computing .

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