International Journal of Recent Advances in Multidisciplinary Topics 31
Volume 3, Issue 2, February 2022
[Link] | ISSN (Online): 2582-7839
Review on Design and Analysis of ALU Using
Reversible Logic Gates
N. Lathangi1*, K. B. Ramesh2
1
Student, Department of Electronics and Instrumentation Engineering, RV college of Engineering, Bangalore,
India
2
Associate Professor, Department of Electronics and Instrumentation Engineering, RV college of Engineering,
Bangalore, India
Abstract: [1] Reversible logic has been of great scientific interest information processing, DNA computing, quantum
in recent years because of its ability to reduce power dissipation computation and nanotechnology. The important reversible
which is the main requirement in low power design. Optimization
gates used for reversible logic synthesis are Feynman Gate,
of power is the primary necessity in portable devices like battery
operated devices. It finds its wide range of applications in the Fredkin gate, Toffoli gate, and Peres gate.
fields of Optical computing, Quantum computing,
Complementary Metal oxide semiconductor and Nanotechnology. 2. Theory
The reversible computing can be performed by using reversible ‘Reversibility’ in computing implies that no information
logic gates which perform arithmetic and logical operations. The
ALU (Arithmetic Logic Unit) is a digital electronic circuit that about the computational states can be lost, so any earlier stage
conducts operations on binary numbers in arithmetic and bitwise can recovered by computing backwards or un-computing the
logical ways. It is used to perform all logical and arithmetic results. Reversible circuits conserve information by
function in processors. It is also an important subsystem in digital uncomputing bits instead of throwing them away. This is
system design. An ALU has a variety of input and output nets termed as logical reversibility. Logical reversibility and its
which are used to convey digital signals between the ALU and
benefits can only be obtained by employing physical
external circuitry. [4] ALUs which are designed using non
reversible logic gates consume more power. So, there is a need for reversibility. Reversible computing offers the only possible
low power consuming ALU designs. This paper is a review of physical way to improve performance. It also leads to
previous works on the design and implementation of ALU using improvement in energy efficiency. Reversible computing is
reversible logic gates. The key objective of this work is to analyze strongly affected by digital logic designs. Reversible logic
the design of the function blocks individually, in order to attain elements are needed to recover the state of inputs from the
better understanding about reversible computing. outputs. Reversible logic supports the process of running the
Keywords: Reversible gate, Power optimization, Arithmetic system both forward and backward. This means that reversible
Logic Unit, Feynman gate, Peres gate, Toffoli gate, Fredkin gate, computations can generate inputs from outputs and can stop and
Digital circuits. go back to any point in the computation history.
Computing systems give off heat when voltage levels change
1. Introduction from positive to negative: bits from zero to one. Most of the
The Arithmetic Logic Unit is a very important subsystem in energy needed to make that change is given off in the form of
the digital system design. It constitutes an integral part of a heat. Rather than changing voltages to new levels, reversible
computer processor that performs arithmetic and logic circuit elements will gradually move charge from one node to
operations in the computer. An ALU is a combinational logic the next. This way, one can only expect to lose a minimal
circuit that can have more inputs and only one output. amount of energy on each transition. Theoretically physical
Nowadays ALU is getting smaller and more complex to enable reversibility is a process that dissipates no energy or heat.
the development of a smaller but more powerful processors. Definition 1: A reversible gate is a n x n circuit (n inputs and n
The need for high speed, less power consumption and outputs) which uniquely maps each of its input to its
compatible processors has been increasing as a result of corresponding output. Reversible gates must satisfy the
computer, digital signal processing and networking following conditions:
applications. [3] Reversible logic has received great attention in 1. It should have equal number of inputs and outputs
the recent years due to its ability to reduce the power dissipation 2. It should have one to one mapping between the inputs
which is the main requirement in low power VLSI design. [1] and outputs.
It has wide applications in low power CMOS and Optical 3. There should be neither feedback nor fanout in case of
*Corresponding author: lathu182@[Link]
N. Lathangi et al. International Journal of Recent Advances in Multidisciplinary Topics, VOL. 3, NO. 2, FEBRUARY 2022 32
a reversible gate. quantum cost. Half adder can be designed by using Single Peres
Definition 2: Ancilla inputs of a reversible gate are the inputs gate.
which should be maintained constant at either ‘0’ or ‘1’ so that
the gate realizes the required Boolean function.
Definition 3: Garbage outputs of a reversible gate are the extra
outputs which are of no logical use and are present only to
maintain reversibility.
Definition 4: Quantum cost refers to the cost of the circuit (or
gate) in terms of number of 1x1 and 2x2 primitive gates used to
design that circuit (or gate).
3. Applications
Reversible computing has applications in transaction
processing and computer security, but the main long-term
benefit is felt very well in those areas which require high energy 3) Toffoli gate
efficiency, speed and performance. It finds applications in areas The following figure shows a 3*3 Toffoli gate. If the input
like vector is I (A, B, C) and the output vector is O (P, Q, R), then
1. Low power CMOS. outputs are defined by P=A, Q=B, R=AB C
2. Quantum computer.
3. Nanotechnology
4. Optical computing
5. Design of low power arithmetic and data path for
digital signal processing (DSP).
6. Field Programmable Gate Arrays (FPGAs) in CMOS
technology for extremely low power, high testability
and self-repair.
4. Reversible gates
1) Feynman Gate
Feynman gate is also known as 2X2 reversible gate. The
input and output vectors for Feynman gate is in (A, B) and Out
(P, Q) respectively. The outputs of FEYMAN gate are denoted
as P=A, Q=A XOR B. The application of this gate is used in
many circuits because of low cost of the FEYMAN gates.
Feynman Gate (FG) can be used as a copying gate. Since a fan-
out is not allowed in reversible logic, this gate is useful for
duplication of required output.
4) Sayem Gate
It is a 4x4 reversible gate. The input and output vector of this
gate are, Iv = (A, B, C, D) and Ov = (A, A’B AC, A’B
AC D, AB A’C D).
5) Reversible Positive Edge Triggered T-Flip Flop
2) Peres Gate
It is a 3X3 reversible gate. Let the input and output for
PERES gate be In (A, B, C) and Out(P, Q, R) respectively. The
output is defined as P = A, Q = A XOR B and R=AB XOR C.
Peres gate is used in many designs because of its lowest
N. Lathangi et al. International Journal of Recent Advances in Multidisciplinary Topics, VOL. 3, NO. 2, FEBRUARY 2022 33
A Master-Slave T Flip-Flop has been designed using depicted:
reversible gates. The truth table and design are shown below.
The added Feynman gate as shown in figure is to get the desired
functionality of Q-1.
6) COG Gate
A COG gate is a 3x3 gate with inputs A, B and C and outputs
P, Q and R such that P=A, Q=AC XOR A’B and R=BC XOR
B’C’. It has a quantum cost of four
7) CNOT Gate
A CNOT (Controlled NOT) is a 2x2 gate which maps its two For a n-bit ALU ‘n’ of such units are combined to derive one
inputs I1 and I2 to its two outputs Y1 and Y2 such that Y1=I1, output. Ex: for a 32-bit ALU, A0 to A31 can be the individual
Y2=I1 ْ I2. CNOT gate representation is as shown. 1-bit ALUs. A low power 16-bit ALU is designed using Verilog
HDL. Verilog HDL is an industry standard language for the
5. ALU with irreversible logic gates description, modelling and synthesis or simulate of digital
The 16-bit ALU is designed which allows the computer to circuits and systems. The proposed design 1 has a quantum cost
add, subtract, multiplication and division and to perform basic of 17. It has 5 garbage outputs and 2 ancilla inputs.
logical operations such as AND, OR, XOR, XNOR, NAND and
inverter etc. A low power 16-bit ALU is designed using Verilog
HDL. Verilog HDL is an industry standard language for the
description, modelling and synthesis or simulate of digital
circuits and systems. In ALU architecture, a high-performance
arithmetic hardware with minimum possible clock cycles
capable of computing square, square root and inverse in
addition to basic arithmetic operations. [2]
The ALU comprises of three units namely arithmetic, logical
and control unit. The following subsections focus on the
designing of these three units and in the end, all of them are
integrated together to form the complete ALU.
1) Arithmetic Unit
The proposed design 2 has a quantum cost of 13. The number
of garbage outputs and ancilla inputs are same as those of
Design 1.
2) Logical Unit
The logical unit has six inputs- A, B, X, Y, N and P. The
result of the logical operation performed on the input A and B
is reflected on the output bit Lout. The logical operation to be
performed is selected by the selection bits X, Y, N and P. The
logical unit will have two realizations. The first design (Design
a) uses Toffoli and CNOT gates while the second design
(Design b) uses Peres and CNOT gates. In each design, GLi
represents ith garbage output of the proposed logical unit.
The proposed arithmetic unit has five inputs A, B, Cin, X and ‘Design a’ has a quantum cost of 45 while it has 15 garbage
Y and two outputs S and Cout. Depending upon the selection outputs and 10 ancilla inputs. Design b has a quantum cost of
bits X and Y and the value of Cin (input carry from previous 38. Besides, it has 16 garbage outputs and 11 ancilla inputs.
stage), an operation is being carried out on the inputs A and B.
S is the final sum/difference bit produced and Cout is the final
carry/borrow bit produced. The functions performed by the
arithmetic unit are summarized in Table and the design is
N. Lathangi et al. International Journal of Recent Advances in Multidisciplinary Topics, VOL. 3, NO. 2, FEBRUARY 2022 34
The three units of ALU are combines using the connections
shown below:
6. Conclusion
The above-mentioned conclusions are made by extensive
literature research and review and it can be concluded that one
of the low power technique, Reversible logic gates can be used
to reduce the power dissipation as compared to irreversible
logic gates. When an ALU is designed using non reversible
logic gates, it is said to consume more power of about 0.312
mw and the implementation of ALU based on reversible logic
can reduce the power consumption during operations to about
3) Design b of logical unit 5.1%. The scope for application of this technology is vast and
yet to be explored. This paper has drawn these conclusions
through thorough case studies and if implemented, the scope for
reversible computing is vast.
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