Faculty Orientation Program 2020-21 (SEM-I)

On
Second Year of Computer Engineering
(2019 Course)
210245:Digital Electronics and Logic Design

Presented by:
[Link] Nilesh P.
Savitribai Phule Pune University
Ganeshkhind Rd, Ganeshkhind, Pune, Maharashtra
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 210245:Digital Electronics and Logic Design
Teaching/Examination Scheme

Teaching Scheme: Examination Scheme

TH: 03 Hours/Week Mid_Semester(TH): 30 Marks

End_Semester(TH): 70 Marks

Credits : 03

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 Unit V : Logic Families (06 Hours)

• Classification of logic families:

• Unipolar and Bipolar Logic Families, Characteristics of Digital ICs: Fan-in, Fan-
out, Current and voltage parameters, Noise immunity, Propagation Delay, Power
Dissipation, Figure of Merits, Operating Temperature Range, power supply
requirements.
• Transistor-Transistor Logic:
• Operation of TTL NAND Gate (Two input), TTL with active pull up, TTL with open
collector output, Wired AND Connection, Tristate TTL Devices, TTL
characteristics.
• CMOS:
• CMOS Inverter, CMOS characteristics, CMOS configurations- Wired Logic, Open
drain outputs.
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 Classification of logic families:
Logic
Families

Bipolar Unipolar

Saturated Unsaturated PMOS NMOS CMOS

RTL Schottky
ECL
TTL
DTL
DCTL
I2L
TTL

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 Types of Logic System:
• Positive Logic System : -
• HIGH = 1(+5V) Vcc
LOGIC 1
• LOW = 0 (0V)
Undefined
Logic

• Negative Logic System :- LOGIC 0

GND
• HIGH = 0(+5V)
• LOW = 1 (0V)
Voltage range for Positive Logic System

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 Characteristics of Digital ICs :
• Fan-in, Fan-out
• Current and voltage parameters
• Noise immunity
• Propagation Delay
• Power Dissipation
• Figure of Merits
• Operating Temperature Range
• Power supply requirements.

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 Fan-In & Fan-Out:

• Fan-In :
• Fan-In of digital logic gate refers to number of inputs.
• Two input gate will have a fan in equal to 2.
• Fan-Out :
• The maximum number of inputs ofsevelar gates that can be
driven by a output of logic gate.
• Fan-out is a measure of the number of loads that a gate
can drive.
• High fan out is advantageous because it reduces the need
of additional drivers to drive more gates.

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 Voltage and Currents Parameters:
• Ideally the input voltage levels of 0V & 5V
( for TTL) are called as logic 0 & 1 levels
respectively but practically we won’t always
obtain volt.
• Low level input voltage :-VIL(max)
• High level input voltage :- VIH(min)
• Low level output voltage :-VOL(max)
• High level output voltage :-VOH(min)

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 Voltage and Currents Parameters:
• High level input current( IIH ):
• Low-level input current ( IIL ):
• High-level output current ( IOH ):
• Low-level output current ( IOL ):

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 Propagation Delay
• Propagation Delay of gate is basically time
interval between application of input pulse and
the occurrence of output pulse.

• tPHL : - Propagation delay measured when o/p

switches from High(1) to low(0).
• tPLH : - Propagation delay measured when o/p
switches from Low(0) to High(1).

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 Noise immunity (Noise Margin ):
Noise immunity is defined as the
ability of a logic circuit to tolerate
the noise without causing any
unwanted changes in the output.
A quantitative measure of noise
immunity is called as noise margin.
High level noise margin,
VNH = VOH(min) – VIH(min)
Low level noise margin,
VNL = VIL(max) – VOL(max)
OUTPUT INPUT

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 Power Dissipation:
• This is the amount of power dissipated in an IC.
• It is determined by the current ,Icc, that it draws from Vcc supply,
and is given by Vcc*Icc .
• Icc is the average value of Icc (0) and Icc (1) .

Pd=Vcc * Iccavg

• This power is specified in milliwatts.

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 Figure of merit:

• Overall performance IC is calculated by the term Figure of Merit.

• The figure of merit of a digital IC is defined as the product of speed

and power.

Figure of merit = Propagation delay *Power Dessipation

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 Operating Temperature Range:
• The temperature range in which an IC functions
For 74 Series –(0°C to 70°C) which is used for consumer and
industrial applications.
For 54 Series – ( -55°C to 125°C ) which is used for military purposes.

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 Transistor-Transistor Logic:
• Transistor-Transistor Logic is
named for its dependence on
Transistors alone to perform
Logic operation.

Two Types of Transistors:

1)N-P-N Transistor
2) P-N-P Transistor

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Operation of TTL NAND Gate (Two input):

D2,D3EB Junctions
D4CB Junction

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 Operation of TTL NAND Gate (Two input):

• A and B are input terminals.

Operation:-
• Case 1 :- Input A and B both are LOW or
Either A or B LOW
• Case 2 :- A and B both HIGH

TRUTH TABLE OF 2-INPUT NAND GATE

A B C
0 0 1
0 1 1
1 0 1
1 1 0

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 Operation of TTL NAND Gate (Two input):

INPUT TRANSISTOR OUTPUT

A B Q1 Q2 Q3 Q4 Y

0 0 ON OFF ON OFF 1

0 1 ON OFF ON OFF 1

1 0 ON OFF ON OFF 1

1 1 OFF ON OFF ON 0

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 TTL with Active Pull-Up /Totem-Pole Output:

The highlighted Output Configuration

Transistor Q3,Diode D4 and Transistor
Q4 form a Active Pull-Up/Totem-Pole
Output.
THIS CIRCUIT IS USED BECAUSE:
• LOW IMPEDENCE
• LOW PROPOGATION DELAY
• HIGH SPEED

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TTL with Active Pull-Up /Totem-Pole Output:

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TTL with Active Pull-Up /Totem-Pole Output:

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TTL with Active Pull-Up /Totem-Pole Output:

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TTL with open collector output :

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TTL with open collector output :

• It is same as 2 Input TTL NAND Gate but with

R3 ,pull up transistor Q3 and D4 removed.
• The Output is taken through collector of Q4.
• External resistance RL is connected for
proper operation. It is known as pull up
resistance.

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 Wired AND Connection:
• Totem-pole Output can not be Wired ANDed.
• Wired ANDing is possible when we use Open collector output.

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 Tri-state TTL Devices:
• A tri-state gate has three output states
• LOW state
• HIGH state
• High-impedance state.
• An external enable input decides whether
the logic gate works according to its truth
table or is in the high-impedance state.
• When OE(Enable)=1 logic gate works
according to truth table.
• When OE(Enable)=0 it is called as High
Impedence(Hi-z) State.

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Tri-state TTL Devices:

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 CMOS Inverter:
• In CMOS inverter,
• Q1 is the n-channel MOS
• Q2 is the p-channel MOS

Vi Q1 Q2 output

0V( logic 0) OFF ON VDD( logic 1)

VDD( logic 1) ON OFF 0V ( logic 0)

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CMOS Inverter:

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CMOS configurations- Wired Logic:

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 CMOS configurations- Open drain outputs:

•The P-Channel Pull-Up MOSFET

(PMOS) is replaced by a diode.

•An External Pull-up resistance

is connected between open drain
and supply voltage +VDD.

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 Comparison CMOS & TTL:
Sr. No. Parameter CMOS TTL
1 Device Used N-Channel MOSFET & P-Channel Bipolar junction transistor
MOSFET
2 (min) 3.5 V (= 5V) 2V
3 (max) 1.5 V 0.8 V
4 (min) 4.95 V 2.7 V
5 (max) 0.05 V 0.4 V
6 Noise margin VN= 1.45 V VN=0.4 V
7 Noisy immunity Better than TTL Less than CMOS
8 Propagation delay 105ns (Metal gate CMOS) 10 ns. (Standard TTL)
9 Switching speed Less than TTL Faster than CMOS
10 Power dissipation per gate =0.1 mW. 10mW

11 Speed power product 10.5 pJ 100pJ

12 Fan out Typically 50 10
13 Power Supply voltage Flexible from 3V to 15 V. Fixed equal to 5V.

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Unit VI: Introduction to Computer Architecture (06 Hours)

• Introduction to Ideal Microprocessor – Data Bus, Address Bus, Control

Bus.
• Microprocessor based Systems – Basic Operation, Microprocessor
operation, Block Diagram of Microprocessor.
• Functional Units of Microprocessor – ALU using IC 74181, Basic
Arithmetic operations using ALU IC 74181, 4-bit Multiplier circuit using
ALU and shift registers. Memory Organization and Operations, digital
circuit using decoder and registers for memory operations.

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 Introduction to Ideal Microprocessor:

• A computer can be represented functionally (in a simplified form) by the

block diagram as shown, it comprises of three basic parts or sub-
systems:

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 Introduction to Ideal Microprocessor:

• The microprocessor or CPU reads each instruction from the memory,

decodes it and executes it.
• It processes the data as required in the instructions. The processing is in
the form of arithmetic and logical operations.
• The data is retrieved from memory or taken from an input device and
the result of processing is stored in the memory or delivered to an
appropriate output device, all as per the instructions.

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Data Bus, Address Bus, Control Bus

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 Data Bus:

•Data lines that provide a path for moving data among system
modules
•May consist of 32, 64, 128, or more separate lines
•The number of lines determines how many bits of data can be
transferred at a time.

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 Address Bus:

If the processor wishes to read a

word of data from memory it puts the
address of the desired word on the address
lines

•Used to address I/O ports

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 Control Bus:

•Used to control the access and the use of the data and address lines.

•Data and Address lines are shared by all components there must be a means of
controlling their use.

•Control signals transmit both command and timing information among system
modules
• Timing signals indicate the validity of data and address information
• Command signals specify operations to be performed

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Microprocessor based Systems – Basic Operation :

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Hardware and Software Approaches

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 Major components:

• CPU
• Instruction interpreter
• Module of general-purpose arithmetic and logic functions
• I/O Components
• Input module
• Contains basic components for accepting data and instructions and converting
them into an internal form of signals usable by the system
• Output module
• Means of reporting results
• Memory

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Memory & I/O:

Memory address Memory buffer

register (MAR) register (MBR)
• Specifies the address • Contains the data to
in memory for the be written into
next read or write memory or receives
the data read from
memory

I/O address I/O buffer register

register (I/OAR) (I/OBR)
• Specifies a particular • Used for the
I/O device exchange of data
between an I/O
module and the CPU

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 Microprocessor operation:
•FETCH: At the beginning of each instruction cycle the processor fetches
an instruction from memory.
•EXECUTE:Execute the Instruction.

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Read & Write Cycle:

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 Processor Components

• ALU- Arithmetic Logic Unit

• Registers
• Control Unit

ALU
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 Registers:

Register as data storage 4 bit Register

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 Registers:

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 Control Unit:

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Digital Electronics Logic Design

Thank you ….!!!

D r. S a b l e N i l e s h P

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