[Link]. Thamer M.

Jamel Electronic I First Class

Chapter Two "Bipolar Transistor Circuits"

[Link] CONSTRUCTION:-
 The transistor is a three-layer semiconductor device consisting of either two n- and
one p-type layers of material or two p- and one n-type layers of material. The former is called an
npn transistor, while the latter is called a pnp transistor. Both are shown in Fig. 3.2 with the
proper dc biasing.

 For the biasing shown in Fig. 3.2 the terminals have been indicated by the capital
letters E for emitter, C for collector, and B for base.

 The abbreviation BJT, from bipolar junction transistor, is often applied to this three
terminal device. The term bipolar reflects the fact that holes and electrons participate in
the injection process into the oppositely polarized material. If only one carrier is

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employed (electron or hole), it is considered a unipolar device. The Schottky diode is

such a device.

2. TRANSISTOR OPERATION:-
 The basic operation of the transistor will now be described using the pnp transistor
of Fig. 3.2a. The operation of the npn transistor is exactly the same if the roles played
by the electron and hole are interchanged.

 In Fig. 3.3 the pnp transistor has been redrawn without the base-to-collector bias. The
depletion region has been reduced in width due to the applied bias, resulting in a heavy
flow of majority carriers from the p- to the n-type material.

 Let us now remove the base-to-emitter bias of the pnp transistor of Fig. 3.2a as shown in
Fig. 3.4. Consider the similarities between this situation and that of the reverse-biased
diode of diod. Recall that the flow of majority carriers is zero, resulting in only a
minority-carrier flow, as indicated in Fig. 3.4.

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 In summary, therefore: One p-n junction of a transistor is reverse biased, while the
other is forward biased.
 In Fig. 3.5 both biasing potentials have been applied to a pnp transistor, with the resulting
majority- and minority-carrier flow indicated. Note in Fig. 3.5 the widths of the depletion
regions, indicating clearly which junction is forward-biased and which is reverse-biased.

 As indicated in Fig. 3.5, a large number of majority carriers will diffuse across the
forward-biased p-n junction into the n-type material. The question then is whether these
carriers will contribute directly to the base current IB or pass directly into the p-type
material. Since the sandwiched n-type material is very thin and has a low conductivity, a
very small number of these carriers will take this path of high resistance to the base
terminal.
 The magnitude of the base current is typically on the order of microamperes as compared
to milliamperes for the emitter and collector currents. The larger number of these
majority carriers will diffuse across the reverse-biased junction into the p-type material
connected to the collector terminal as indicated in Fig. [Link] this with the fact
that all the minority carriers in the depletion region will cross the reverse-biased junction
of a diode accounts for the flow indicated in Fig. 3.5.

 Applying Kirchhoff’s current law to the transistor of Fig. 3.5 as if it were a single node,
we obtain

 and find that the emitter current is the sum of the collector and base currents. The
collector current, however, is comprised of two components—the majority and minority
carriers as indicated in Fig. 3.5. The minority-current component is called the leakage
current and is given the symbol ICO (IC current with emitter terminal Open). The collector
current, therefore, is determined in total by Eq. (3.2).

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 For general-purpose transistors, IC is measured in milliamperes, while ICO is measured

in microamperes or nanoamperes.

3. COMMON-BASE CONFIGURATION:-
 Fig. 3.6 for the common-base configuration with pnp and npn transistors. The common-
base terminology is derived from the fact that the base is common to both the input and
output sides of the configuration. In addition, the base is usually the terminal closest to,
or at, ground potential.
 For the transistor: The arrow in the graphic symbol defines the direction of emitter
current (conventional flow) through the device. All the current directions appearing in
Fig. 3.6 are the actual directions as defined by the choice of conventional flow.

 Note in each case that IE =IC + IB.

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 To fully describe the behavior of a three-terminal device such as the common base
amplifiers of Fig. 3.6 requires two sets of characteristics—one for the driving point or
input parameters and the other for the output side. The input set for the common-base
amplifier as shown in Fig. 3.7 will relate an input current (IE) to an input voltage (VBE) for
various levels of output voltage (VCB).

 The output set will relate an output current (IC) to an output voltage (VCB) for
various levels of input current (IE) as shown in Fig. 3.8. The output or collector
set of characteristics has three basic regions of interest, as indicated in Fig. 3.8:
the active, cutoff, and saturation regions.

 The active region is the region normally employed for linear (undistorted)
amplifiers. In particular: In the active region the collector-base junction is
reverse-biased, while the base-emitter junction is forward-biased.

 The active region is defined by the biasing arrangements of Fig. 3.6. At the lower
end of the active region the emitter current (IE) is zero, the collector current is
simply that due to the reverse saturation current ICO, as indicated in Fig. 3.8. The
current ICO is so small (microamperes) in magnitude compared to the vertical
scale of IC (milliamperes) that it appears on virtually the same horizontal line as IC
=0.

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 Note in Fig. 3.8 that as the emitter current increases above zero, the collector
current increases to a magnitude essentially equal to that of the emitter current as
determined by the basic transistor-current relations.

 As inferred by its name, the cutoff region is defined as that region where the
collector current is 0 A, as revealed on Fig. 3.8. In addition: In the cutoff region
the collector-base and base-emitter junctions of a transistor are both reverse-
biased.

 The saturation region is defined as that region of the characteristics to the left of
VCB =0 V. The horizontal scale in this region was expanded to clearly show the
dramatic change in characteristics in this region. Note the exponential increase in
collector current as the voltage VCB increases toward 0 V. In the saturation
region the collector-base and base-emitter junctions are forward-biased.

 For the analysis to follow in this chapter, the equivalent model of Fig. 3.10c will
be employed for all dc analysis of transistor networks. That is, once a transistor is in
the “on” state, the base-to-emitter voltage will be assumed to be the following:

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EXAMPLE :
(a) Using the characteristics of Fig. 3.8, determine the resulting collector current if
IE =3 mA and VCB = 10 V.
(b) Using the characteristics of Fig. 3.8, determine the resulting collector current if IE
remains at 3 mA but VCB is reduced to 2 V.
(c) Using the characteristics of Figs. 3.7 and 3.8, determine VBE if IC = 4 mA and VCB = 20
V.
(d) Repeat part (c) using the characteristics of Figs. 3.8 and 3.10c.

Solution
(a) The characteristics clearly indicate that IC = IE =3 mA.
(b) The effect of changing VCB is negligible and IC continues to be 3 mA.
(c) From Fig. 3.8, IE =IC = 4 mA. On Fig. 3.7 the resulting level of VBE is about 0.74 V.
(d) Again from Fig. 3.8, IE= IC =4 mA. However, on Fig. 3.10c, VBE is 0.7 V for any level
of emitter current.

 Alpha (α): In the dc mode the levels of IC and IE due to the majority carriers are related by
a quantity called alpha and defined by the following equation:

 for practical devices the level of alpha typically extends from 0.90 to 0.998, with most
approaching the high end of the range. Since alpha is defined solely for the majority carriers,
Eq. (3.2) becomes

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 For ac situations where the point of operation moves on the characteristic curve, an ac
alpha is defined by

 The ac alpha is formally called the common-base, short-circuit, amplification factor,

 Biasing : The proper biasing of the common-base configuration in the active region can
be determined quickly using the approximation IC = IE and assuming for the moment that IB
= 0 µA. The result is the configuration of Fig. 3.11 for the pnp transistor. The arrow of the
symbol defines the direction of conventional flow for IE = IC. The dc supplies are then
inserted with a polarity that will support the resulting current direction. For the npn
transistor the polarities will be reversed.

[Link] AMPLIFYING ACTION:-

 The basic amplifying action of the transistor can be introduced on a surface level using
the network of Fig. 3.12. For the common-base configuration the ac input resistance
determined by the characteristics of Fig. 3.7 is quite small and typically varies from 10 to
100 . The output resistance as determined by the curves of Fig. 3.8 is quite high.
 Using a common value of 20  for the input resistance, we find that

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 Typical values of voltage amplification for the common-base configuration vary

from 50 to 300. The current amplification (IC/IE) is always less than 1 for the common-
base configuration. This latter characteristic should be obvious since IC = α IE and σ is
always less than 1.

[Link]-EMITTER CONFIGURATION:-
 The most frequently encountered transistor configuration appears in Fig. 3.13 for the pnp
and npn transistors. It is called the common-emitter configuration since the emitter is
common or reference to both the input and output terminals (in this case common to both
the base and collector terminals).
 Two sets of characteristics are again necessary to describe fully the behavior of the
common-emitter configuration: one for the input or base-emitter circuit and one for the
output or collector-emitter circuit. Both are shown in Fig. 3.14.

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[Link]. Thamer [Link] Electronic I First Class

 Even though the transistor configuration has changed, the current relations developed
earlier for the common-base configuration are still applicable. That is, IE = IC + IB and IC
= α IE.
 For the common-emitter configuration the output characteristics are a plot of the output
current (IC) versus output voltage (VCE) for a range of values of input current (IB). The
input characteristics are a plot of the input current (IB) versus the input voltage (VBE) for a
range of values of output voltage (VCE).

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 The active region for the common-emitter configuration is that portion of the upper-right
quadrant that has the greatest linearity, that is, that region in which the curves for IB are
nearly straight and equally spaced. In Fig. 3.14a this region exists to the right of the
vertical dashed line at VCEsat and above the curve for IB equal to zero. The region to the
left of VCEsat is called the saturation region. In the active region of a common-emitter
amplifier the collector-base junction is reverse-biased, while the base-emitter junction
is forward-biased.
 For future reference, the collector current defined by the condition IB = 0 µA will be
assigned the notation indicated by Eq. (3.9).

 In Fig. 3.15 the conditions surrounding this newly defined current are demonstrated
with its assigned reference direction. For linear (least distortion) amplification
purposes, cutoff for the commonemitter configuration will be defined by IC = ICEO. In
other words, the region below IB = 0 µA is to be avoided if an undistorted output signal is
required.

 When employed as a switch in the logic circuitry of a computer, a transistor will have
two points of operation of interest: one in the cutoff and one in the saturation region. The
cutoff condition should ideally be IC = 0 mA for the chosen VCE voltage.
 Since ICEO is typically low in magnitude for silicon materials, cutoff will exist for
switching purposes when IB = 0 µA or IC = ICEO for silicon transistors only. For
germanium transistors, however, cutoff for switching purposes will be defined as those
conditions that exist when IC = ICBO.

EXAMPLE : (a) Using the characteristics of Fig. 3.14, determine IC at IB =30 µA and VCE =
10 V.
(b) Using the characteristics of Fig. 3.14, determine IC at VBE = 0.7 V and VCE = 15 V.

Solution

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(a) At the intersection of IB =30 µA and VCE = 10 V, IC = 3.4 mA.

(b) Using Fig. 3.14b, IB = 20 µA at VBE = 0.7 V. From Fig. 3.14a we find that IC = 2.5 mA at the
intersection of IB =20 µA and VCE = 15 V.

 Beta (β) : In the dc mode the levels of IC and IB are related by a quantity called beta and
defined by the following equation:

 For practical devices the level of typically ranges from about 50 to over 400, with most
in the midrange. As for α, β certainly reveals the relative magnitude of one current to the
other. For a device with a of 200, the collector current is 200 times the magnitude of the
base current.

 For ac situations an ac beta has been defined as follows:

 The use of Eq. (3.11) is best described by a numerical example using an actual set of
characteristics such as appearing in Fig. 3.14a and repeated in Fig. 3.17. Let us determine
ac for a region of the characteristics defined by an operating point of IB = 25 µA and VCE
= 7.5 V as indicated on Fig. 3.17.
 The restriction of VCE = constant requires that a vertical line be drawn through the
operating point at VCE = 7.5 V. At any location on this vertical line the voltage VCE is 7.5
V, a constant. The change in IB ( Δ IB) as appearing in Eq. (3.11) is then defined by
choosing two points on either side of the Q-point along the vertical axis of about equal
distances to either side of the Q-point. For this situation the IB = 20 µA and 30 µA curves
meet the requirement without extending too far from the Q-point.

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The resulting βac for the region can then be determined by

If we determine the dc beta at the Q-point:

Calculating the βac at the Q-point indicated will result in:-

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 A relationship can be developed between β and α using the basic relationships introduced
thus far. Using β = IC/IB we have IB = IC/β , and from α = IC/IE we have IE = IC/α.
Substituting into

 Beta is a particularly important parameter because it provides a direct link between

current levels of the input and output circuits for a common-emitter configuration. That
is,

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 Biasing: Let us assume that we are presented with an npn transistor such as shown in Fig.
3.19a and asked to apply the proper biasing to place the device in the active region.

 The first step is to indicate the direction of IE as established by the arrow in the transistor
symbol as shown in Fig. 3.19b. Next, the other currents are introduced as shown, keeping
in mind the Kirchhoff’s current law relationship: IC + IB = IE. Finally, the supplies are
introduced with polarities that will support the resulting directions of IB and IC as shown
in Fig. 3.19c to complete the picture. The same approach can be applied to pnp
transistors. If the transistor of Fig. 3.19 was a pnp transistor, all the currents and polarities
of Fig. 3.19c would be reversed.

[Link]-COLLECTOR CONFIGURATION:
 The third and final transistor configuration is the common-collector configuration, shown
in Fig. 3.20 with the proper current directions and voltage notation. The common-
collector configuration is used primarily for impedance-matching purposes since it has a
high input impedance and low output impedance, opposite to that of the common-base
and common-emitter configurations.

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[Link]. Thamer [Link] Electronic I First Class

 A common-collector circuit configuration is provided in Fig. 3.21 with the load resistor
connected from emitter to ground. Note that the collector is tied to ground even though
the transistor is connected in a manner similar to the common-emitter configuration.

 For all practical purposes, the output characteristics of the common-collector

configuration are the same as for the common-emitter configuration. For the common-
collector configuration the output characteristics are a plot of IE versus VEC for a range of
values of IB.
 The input current, therefore, is the same for both the common-emitter and common
collector characteristics. The horizontal voltage axis for the common-collector
configuration is obtained by simply changing the sign of the collector-to-emitter voltage
of the common-emitter characteristics.

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 Finally, there is an almost unnoticeable change in the vertical scale of IC of the common-
emitter characteristics if IC is replaced by IE for the common-collector characteristics
(since α ≈1). For the input circuit of the common-collector configuration the common-
emitter base characteristics are sufficient for obtaining the required information.

7. OPERATING POINT:-
 For transistor amplifiers the resulting dc current and voltage establish an
operating point on the characteristics that define the region that will be employed
for amplification of the applied signal. Since the operating point is a fixed point
on the characteristics, it is also called the quiescent point (abbreviated Q-point).
 Figure 4.1 shows a general output device characteristic with four operating points
indicated. The biasing circuit can be designed to set the device operation at any of
these points or others within the active region.

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[Link]. Thamer [Link] Electronic I First Class

 The maximum ratings are indicated on the characteristics of Fig. 4.1 by a

horizontal line for the maximum collector current ICmax and a vertical line at the
maximum collector-to-emitter voltage VCEmax.
 The maximum power constraint is defined by the curve PCmax in the same figure.
At the lower end of the scales are the cutoff region, defined by IB ≤ 0 µA, and the
saturation region, defined by VCE ≤ VCEsat.

 The BJT device could be biased to operate outside these maximum limits, but the
result of such operation would be either a considerable shortening of the lifetime
of the device or destruction of the device. Confining ourselves to the active
region, one can select many different operating areas or points.
 If no bias were used, the device would initially be completely off, resulting in a
Q-point at A—namely, zero current through the device (and zero voltage across
it). Since it is necessary to bias a device so that it can respond to the entire range
of an input signal, point A would not be suitable.
 For point B, if a signal is applied to the circuit, the device will vary in current and
voltage from operating point, allowing the device to react to (and possibly
amplify) both the positive and negative excursions of the input signal. If the input

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signal is properly chosen, the voltage and current of the device will vary but not
enough to drive the device into cutoff or saturation.
 Point C would allow some positive and negative variation of the output signal, but
the peak to- peak value would be limited by the proximity of VCE = 0 V/IC = 0
mA. Operating at point C also raises some concern about the nonlinearities
introduced by the fact that the spacing between IB curves is rapidly changing in
this region.
 Point D sets the device operating point near the maximum voltage and power
level. The output voltage swing in the positive direction is thus limited if the
maximum voltage is not to be exceeded. Point B therefore seems the best
operating point in terms of linear gain and largest possible voltage and current
swing. This is usually the desired condition for small-signal amplifiers , but not
the case necessarily for power amplifiers. In this discussion, we will be
concentrating primarily on biasing the transistor for small-signal amplification
operation.
 For the BJT to be biased in its linear or active operating region the following must
be true:
1. The base–emitter junction must be forward-biased (p-region voltage more
positive), with a resulting forward-bias voltage of about 0.6 to 0.7 V.
2. The base–collector junction must be reverse-biased (n-region more positive),
with the reverse-bias voltage being any value within the maximum limits of the
device.
 Operation in the cutoff, saturation, and linear regions of the BJT
characteristic are provided as follows:
1. Linear-region operation: Base–emitter junction forward biased Base–
collector junction reverse biased.
2. Cutoff-region operation: Base–emitter junction reverse biased
3. Saturation-region operation: Base–emitter junction forward biased
Base–collector junction forward biased

8. FIXED-BIAS CIRCUIT:-
 The fixed-bias circuit of Fig. 4.2 provides a relatively straightforward and simple
introduction to transistor dc bias analysis. Even though the network employs an npn
transistor, the equations and calculations apply equally well to a pnp transistor
configuration merely by changing all current directions and voltage polarities.

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 The current directions of Fig. 4.2 are the actual current directions, and the voltages are
defined by the standard double-subscript notation. For the dc analysis the network can be
isolated from the indicated ac levels by replacing the capacitors with an open circuit
equivalent.

 In addition, the dc supply VCC can be separated into two supplies (for analysis purposes
only) as shown in Fig. 4.3 to permit a separation of input and output circuits. It also

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reduces the linkage between the two to the base current IB. The separation is certainly
valid, as we note in Fig. 4.3 that VCC is connected directly to RB and RC just as in Fig. 4.2.

Forward Bias of Base–Emitter:-

 Consider first the base–emitter circuit loop of Fig. 4.4. Writing Kirchhoff’s voltage
equation in the clockwise direction for the loop, we obtain

 Note the polarity of the voltage drop across RB as established by the indicated direction of
IB. Solving the equation for the current IB will result in the following:

 Since the supply voltage VCC and the base–emitter voltage VBE are constants, the selection
of a base resistor, RB, sets the level of base current for the operating point.

Collector–Emitter Loop:-

 The collector–emitter section of the network appears in Fig. 4.5 with the indicated
direction of current IC and the resulting polarity across RC. The magnitude of the collector
current is related directly to IB through

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 Applying Kirchhoff’s voltage law in the clockwise direction around the indicated closed
loop of Fig. 4.5 will result in the following:

 As a brief review of single- and double-subscript notation recall that

 Where VCE is the voltage from collector to emitter and VC and VE are the voltages from
collector and emitter to ground respectively. But in this case, since VE = 0 V, we have

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EXAMPLE:
Determine the following for the fixed-bias configuration of Fig. 4.7.?

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Load-Line Analysis:-
 We will now investigate how the network parameters define the possible range of Q-
points and how the actual Q-point is determined. The network of Fig. 4.11a establishes an
output equation that relates the variables IC and VCE in the following manner:

 The device characteristics of IC versus VCE are provided in Fig. 4.11b. We must now
superimpose the straight line defined by Eq. (4.12) on the characteristics. The most direct
method of plotting Eq. (4.12) on the output characteristics is to use the fact that a straight
line is defined by two points. If we choose IC to be 0 mA, we are specifying the
horizontal axis as the line on which one point is located. By substituting IC = 0 mA into
Eq. (4.12), we find that

 Defining one point for the straight line as shown in Fig. 4.12.

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 If we now choose VCE to be 0 V, which establishes the vertical axis as the line on which
the second point will be defined, we find that IC is determined by the following equation:

 By joining the two points defined by Eqs. (4.13) and (4.14), the straight line established
by Eq. (4.12) can be drawn. The resulting line on the graph of Fig. 4.12 is called the load
line since it is defined by the load resistor RC. By solving for the resulting level of IB, the
actual Q-point can be established as shown in Fig. 4.12.
 If the level of IB is changed by varying the value of RB the Q-point moves up or down the
load line as shown in Fig. 4.13. If VCC is held fixed and RC changed, the load line will
shift as shown in Fig. 4.14. If IB is held fixed, the Q-point will move as shown in the
same figure. If RC is fixed and VCC varied, the load line shifts as shown in Fig. 4.15.

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[Link]. Thamer [Link] Electronic I First Class

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 [Link]. Thamer [Link] Electronic I First Class

EXAMPLE:
Given the load line of Fig. 4.16 and the defined Q-point, determine the required values
of VCC, RC, and RB for a fixed-bias configuration?

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9. EMITTER-STABILIZED BIAS CIRCUIT:-

 The dc bias network of Fig. 4.17 contains an emitter resistor to improve the stability level
over that of the fixed-bias configuration

 Base–Emitter Loop: - The base–emitter loop of the network of Fig. 4.17 can be redrawn
as shown in Fig. 4.18. Writing Kirchhoff’s voltage law around the indicated loop in the
clockwise direction will result in the following equation:

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There is an interesting result that can be derived from Eq. (4.17) if the equation is used to sketch
a series network that would result in the same equation. Such is the case for the network of Fig.
4.19. Solving for the current IB will result in the same equation obtained above. Note that aside
from the base-to-emitter voltage VBE, the resistor RE is reflected back to the input base circuit by
a factor (β +1). In other words, the emitter resistor, which is part of the collector–emitter loop,
“appears as” (β +1)RE in the base–emitter loop. Since β is typically 50 or more, the emitter
resistor appears to be a great deal larger in the base circuit. In general, therefore, for the
configuration of Fig. 4.20,

 Collector–Emitter Loop:- The collector–emitter loop is redrawn in Fig. 4.21. Writing

Kirchhoff’s voltage law for the indicated loop in the clockwise direction will result in

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 [Link]. Thamer [Link] Electronic I First Class

EXAMPLE:-

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 [Link]. Thamer [Link] Electronic I First Class

Load-Line Analysis:- The level of IB as determined by Eq. (4.17) defines the level of IB on the
characteristics of Fig. 4.24 (denoted IBQ).

The collector–emitter loop equation that defines the load line is the following:

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[Link] SWITCHING NETWORKS

 The application of transistors is not limited solely to the amplification of signals. Through
proper design it can be used as a switch for computer and control applications.

 The network of Fig. 4.52a can be employed as an inverter in computer logic circuitry.
Note that the output voltage VC is opposite to that applied to the base or input terminal.

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 Proper design for the inversion process requires that the operating point switch from
cutoff to saturation along the load line depicted in Fig. 4.52b. For our purposes we will
assume that IC = ICEO = 0 mA when IB = 0 µA (an excellent approximation in light of
improving construction techniques), as shown in Fig. 4.52b. In addition,we will assume
that VCE = VCEsat = 0 V rather than the typical 0.1- to 0.3-V level.

 When Vi = 5 V, the transistor will be “on” and the design must ensure that the network is
heavily saturated by a level of IB greater than that associated with the IB curve appearing
near the saturation level. In Fig. 4.52b, this requires that IB = 50 µA. The saturation level
for the collector current for the circuit of Fig. 4.52a is defined by

 The level of IB in the active region just before saturation results can be approximated by
the following equation:

 For the saturation level we must therefore ensure that the following condition is satisfied:

 For the network of Fig. 4.52b, when Vi = 5 V, the resulting level of IB is the following:

 For Vi = 0 V, IB = 0 µA, and since we are assuming that IC = ICEO = 0 mA, the voltage
drop across RC as determined by VRC = ICRC = 0 V, resulting in VC= +5 V for the
response indicated in Fig. 4.52a.

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 In addition to its contribution to computer logic, the transistor can also be employed as a
switch using the same extremities of the load line. At saturation, the current IC is quite
high and the voltage VCE very low. The result is a resistance level between the two
terminals determined by

which is a relatively low value and ≈ 0 when placed in series with resistors in the kilohm range.

 For Vi = 0 V, as shown in Fig. 4.54, the cutoff condition will result in a resistance level
of the following magnitude:

 resulting in the open-circuit equivalence. For a typical value of ICEO = 10 µA, the
magnitude of the cutoff resistance is

which certainly approaches an open-circuit equivalence for many situations.

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EXAMPLE:- Determine RB and RC for the transistor inverter of Fig. 4.55 if ICsat =10 mA?

36