DFT Flow:

DFT Flow:
MBIST Insertion

EDT/OCC insertion
using DFT Spec

Synthesis

Hierarchical Scan insertion

(Wrapper insertion, Gray box insertion)

ATPG

Simulation
What is DFT and why DFT is required
Adding testable features to the design converting all the flops in to scannable cells by adding
mux and stitching these cells to form a scan chain in shift register fashion.
 In order to identify Manufacturing defects
 Increased productivity
 Improved quality
 Increase the durability of a chip
 Reduce the test – time and test – cost also test – data
Note: DFT is not to find the functional bugs DFT is to find the manufacturing defects.

What is testability?
The ability to put a design in to known initial state and then control and observe the internal
signal values
Controllability: Difficulty in setting the signal to the required logic value (either 0 or 1)
from the input side of the design
Observability: Difficulty in propagating the required logic value either 0 or 1) to the output
side of the design

Need of Scan:
In a smaller and purely combinational circuit it is easy to control the internal nodes from PI's
and observe the response at PO's.
 Today's designs are usually complex and invariably contain sequential cells.
 The internal nodes will be fed by the flip-flops which are logically far from the Primary
Inputs and outputs. This makes the internal nodes difficult to test.
 Scan helps us in directly applying the stimulus to internal nodes by leading the flip-
flops feeding them and propagating the captured value in scan cells through shift
register mode.

SCAN Principle:
 First convert the normal flop into scan flop by using multiplexer.
  The test patterns are applied directly to the internal design by shifting in the input values
through the serial scan shift registers.
 Apply the capture clock and capture the internal logic's response into the scan cells.
 Captured values are shifted out, through the scan out.

Scan path design in structured DFT

 All flip-flops are replaced by scan flops.
 Connect the scan flops as configurable shift registers.
 Add one Test Control (TC) primary input.
 Add a SCAN IN input and SCAN OUT output for the shift register.

Scan design procedure

 Initially, select scan mode. (SE = HIGH)

 Shift in scan data.
 Select normal mode. (SE = LOW)
 Force primary input values.
 Measure primary outputs.
 Capture circuit response from combinational logic into scan cells.
 Shift out scan data. Then, shift in next set of scan cell data values. (SE = HIGH)

Scan design operations

Scan involves 3 different types of operations
 Normal operation (TM=0, SE=0)
 Shift operation (TM=1, SE=1)
 Capture operation (TM=1, SE=0)

1. Normal operation
 During this mode of operation, all test signals are turned OFF.
 In this mode, TM (Test Mode) pin is set to 0 and SE is set also 0 always.
 The scan design operates in the original functional configuration.
 The normal mode is activated when Scan Enable is 0.
 The mux selects the normal mode Data input (DI) to the D pin of actual flip-flop. And
the value from D pin is propagate to Q output.
2. Shift operation
 In this operation, we shift the test pattern into the scan chain.
 Here, we shift the test patterns into the scan chains.
 It covers the shift paths when SE is equals to 1.
 In this mode, TM pin is set to 1 and SE pin is also set to 1 always.
 Here we use scan chains that are used to shift-in and shift-out the test data.
 A number of flops connected back-to-back in chain with output of one flop connected
to input of next flop.
 It acts as shift register.
 The scan data fed from SI(Scan-In) pin.
 The output of last flop is connected to SO(Scan-Out). Which is take shifted data out.

3. Capture operation

 In this mode, SE (Scan Enable) pin is de-asserted (Logic Low). So that, the flip-flops
work in a normal functional mode.
 The response from the combinational circuit is captured, corresponding applied a test
pattern, the response gets loaded into a scan chain.
 It runs at functional frequency. During this mode, TM pin is set to 1, but SE pin is set
to 0 always
Scan – Insertion Flow
1. Setup (or) Build Phase:
 Design (Netlist contains of clocks, pins, reset, constraint information)
 Library (Information about Gates, Flops, Model reference name)
 Scan configuration (Number of chains required to build based on number of pins and
pads, gives requirements of scan clock, scan enable, TM, Scan-in and Scan -out
declarations)
 set_context dft -scan
 read_cell_library<[Link]>
 read_verilog<netlist>
 add_clocks 0<clock name>
 set_scan_enable<scan_enable>
 set_scan_pins input/output si/so
 add_pin_constarints testmode c1
 set_current_design<top_module name>

2. Analysis:
 In analysis mode, it will analyze whether the design is proper for scan insertion or not
 In analysis mode, it will check for the DRC’s by taking design and library cell as inputs
 DRC rule checks will be done here
 check_design_rules
 write_results
 report_scan_chains
 report_scan_cells

3. Insertion:
 Replace DFF with SDFF and build the scan chains
 Create necessary ports (TM, SE, etc)
 insert_test_logic <number>
 read_config_data
 write_config_data
 process_specification
 extract_sdc
 extract_icl
 write_atpg_setup
 write_scan_order
 report_wrapper_cells
 report_static_dft_signal_settings

Inputs & Outputs for Scan:

Inputs for Scan
 Library file (Contains info about gates, flops, model reference name in form of code)
 Gate level netlist (Non scan netlist) (Contains clocks, pins, reset, constraint
information)
 Compression ratio (scan in, scan out)
  Core test Language models (information regarding scan chains of a block, all input and
output signals are defined with direction at first)
 Run File (Contain just source of inputs)
Outputs for Scan
 Scan Inserted netlist (Contains scan inserted logic)
 ATPG Do – File (Contains scan chain info. and scan group information)
 ATPG Test – Proc file
 Scan cell report
 Scan chain report
 Scan definition file (Contains overall scan related information)
 SDC (Synopsis Design Constraints)

Scan advantages:

 Easy to get controllability and observability on each and every node

 Make a complete design in to shift register
 Improve test efficiency
 Easy to generate patterns for scan design
 Increase the coverage

Scan disadvantages:

 Area over ahead

 Power consumption increase
 Timing issues coming
 Routing congestions increase
Scan design rules:

Scan design rules also called as SCAN DRC’S in order to implement scan into a design, the
design must comply with a set of scan design rules. As they limit the fault coverage.
Scan design rules that are labeled “avoid” must be fixed throughout the shift and capture
operations

Major Scan Drc’s:

 All internal clocks must be controllable from top level

 Set and reset signals must be controllable from top level
 Avoid the combinational feedbacks in the design
 If any latch in the design need to convert into transparent latch
 Need not be convert the existing shift registers into scan flops
 If there are any memory elements in design bypass the memory logic.
 Avoid the multicycles paths as much as possible
 There is no minimum coupling between the clock and data
 Scan enable signals must be buffered
 Edge mixing
 If design positive edge flop follows negative edge flop data mismatches are occurs,
these data mismatches avoid by two methods
 Design must be negative edge flop follows the positive edge
 Use lockup latch between positive edge flop follows negative edge flop
Scan Compression:
Embedded Deterministic Testing (EDT) is the technology used by Testkompress. Compression
is a technique to reduce the test time, test cost and also test data.
By using compression technique, we will decrease length of the scan chains without
increasing the scan ports.

Suppose we have 100 flops then we require 100 cycles for shiftin 100 cycles for shiftout and 1
cycle for capture total we require 201 cycles for one pattern.

For 100 patterns we require 201x100 = 20100 cycles. Assume the frequency is 10 MHz clock
then time period for each cycle is 100ns so for 100 patterns we require 20100x100ns =
201000ns=2.01 msec

If 50 flops in each chain then we require 10100 cyclesx100ns=1.01 msec

Advantages of compression:
 Reduce test cost
 Reduce test time: (LxW)/Frequency
 Reduce test data volume (LxWxH)
where
L=Length of longest scan chain
W=Number of patterns
H= Number of scan channels

Compression ratio = Internal scan chains

Scan channels

Initialization cycles= ceil Decompressor size

Number of channels

Each compressed test pattern has a small number of additional shift cycles, so the
total number of shifts per pattern would be slightly more than the number of scan
cells in each chain.
The term “additional shift cycles” refers to the sum of the initialization cycles,
masking bits (when using Xpress), low power bits (when using a low-power
decompressor), and user defined pipeline bits.
You can use the following equation to predict the number of initializations cycles
the tool adds to each pattern load.
In this equation, “ceil” indicates the ceiling function that rounds a fraction to the next
highest integer.
Scan compression main blocks:

 Decompressor
 Compressor
 Masking logic

Decompressor:

The decompressor can be composed of a broadcast or spreader network with a multiplexer

logic of scan input pins

It is located between the external scan channel inputs and the internal scan chain inputs

It consists of LFSR, Phase shifter that has XOR gates.

LFSR:
LFSR (linear feedback shift register) consists of ‘N’ flops and XOR gates.
LFSR represented by characteristic polynomial.
The inputs of LFSR are coming from external scan channels. The output of LFSR
will connect to scan chain inputs through phase shifter.
The initial value to the LFSR is called “seed value”.
After that based on characteristic polynomial LFSR will generate the patterns.
Example: seed value = 0 0 1

clk Q0 Q1 Q2
-- 0 0 1
1 1 0 0
2 1 1 0
3 1 1 1
4 0 1 1
5 1 0 1
6 0 1 0
7 0 0 1
8 1 0 0

In the above circuit the patterns are repeating after 7th clock pulse so this is one of the
disadvantages of the LFSR.
so to overcome that disadvantage we will use phase shifter.
Phase Shifter:
One of the major disadvantage of LFSR is there is no enough randomness. In the
absence of phase shifter there exists a diagonal relationship between adjacent bit
streams.
So, to introduce more randomness between the bit streams we will use a phase shifter
which is implemented by XOR network.

Basically, each bit stream is phase shifted by some cycles.

More randomness helps in increasing fault coverage.

LFSR with phase shifter can support more scan chains (“N” degree LFSR can
support maximum of “N” scan chains without phase shifter).
Lockup latch:

Lockup latch is a transparent latch used to fixing timing problems between

decompressor/compactor and internal scan chains because both are running different
clocks.
 It provides the clock synchronization between scan clock and EDT clock.
 In decompressor side it considers both edt-clock and first scan cell.
  In compactor side it considers clock of last scan cell and presence of
pipeline stages in compactor.
 If any two scan cells in the chains having timing issues, then also, we will
use lockup latches.

Compactor:

It is located between the internal scan chain outputs and external scan channel
output
Used to compress the number of scan chain data which is fed to scan channels by
using the XOR logic

Masking Logic:

 If Design contains x-source logic which can drives the x-values to scan chain
output.
 For these x-source logic effects the test coverage. Need to mask x-source
logic by using masking logic.
 The mask logic is masking some errors
 X-masking
 If any internal scan chain logic drives x-value to the xor logic, the xor logic
always drives x-value at output of scan channel.
 By using x-masking we can mask that particular scan chain logic by using
AND gate logic
 Aliasing effect
 The output of scan chain gives same value with fault and without fault then
this effect is called aliasing effect.
 This effect can eliminate by using masking AND logic
Scan Compression Flow:

[Link] up mode:
 set_context_dft_edt
 read_cell_library
 read_verilog
 ATPG dofile (clocks added in scan, how many scan flops, scan chains, pin
constraints added in scan)
 set_current_design
 set_edt_options -channel<number>

2. Analysis Mode:
 write_edt_files
 report_dft_control_points
 report_config_data
ATPG (Automatic test pattern generation):

The procedure involves the generation of input patterns that can ascertain presence or absence
of faults at some location in a circuit

For detection of faults in design we generate patterns called test pattern generation, if it is
automated through a DFT tool we call as automatic test pattern generation.

ATPG Flow:

[Link] Phase:

 Invoke tool tessent -shell (2022.4 latest version)

 set_context patterns -scan
 read libraries
 read netlist
 read verilog
 set current design top module name to read all libraries and modules of current design
(during this phase it will find the undefined modules before using set_system_mode or
create_flat_model we must either define the missing modules using read_verilog or
read_cell_library or use add_black_box -auto to read them as black boxes)
 add_black_boxes -auto used to black box all undefined modules in the current design
netlist. Tool will not target on these black boxes, if we will not define, we will face
tracing issues

 DRC handling set_drc_handling D1 -warning

 Clock definitionadd_clocks 0 clock name
 Pin constraints add_pin_con
 cut pointsadd_primary_input
 add_input_con
 read test_proc file
 Jdr programming
 add edt blocks top
 run chain dofile (setting edt top, decompressor, compactor, internal scan chains)

2. DRC Mode:

 set_system_mode analysis
 design flatteningwhich converts the blocks in to design primitives (and, or, xor etc.)
 learning analysis it will trace the shift path from SO to SI
 scan chain identification how many memory elements
 edt finder analysisedt blocks, scan chain scan cells
 edt setup and rule checking --> enters edt pattern generation phase
 transparent latch check
 scan clock rule check non scan elements will be identified and those are categorized
in to TLA (those gates propagate values without holding state, tie0, tie1, pin or state
elements constrained to a specific value (0,1, x, z) the rule checker may also determine
that state elements exhibited behavior and replace them with the appropriate tie gates)
3. ATPG Phase:

 report scan_cells and scan_chains

 save flat model
 set_fault_model -trans (by default tool will have stuck at)
 set pattern type -sequential 2
 set atpg compression on
 add faults all
 set abort limit
 write chain patterns for ATE in still format
 write chain patterns for simulation in Verilog testbench format
 set atpg pattern limit pattern count
 create patterns (if using NCP generate with each NCP individually)
 pattern generation with NCP
 edt with 1 hot scan masking
 finding the detected by implication faults tool will stop pattern generation once
found ineffective patterns (means detecting less than 12% of faults from remaining
faults) redundant faults identified by generating deterministic pattern generation
 write patterns for ATPG to run again for debugging purpose

ATPG Inputs:
 Libraries: contains information of gates, flops, model reference name in the form of a
code
 Scan +compressed netlist: contains scan & compression inserted logic
 ATPG setup files: contains the setup information for ATPG
 ATPG Dofile: has scan info, chain length from SI to SO
 ATPG testproc files: contains timescale, setup procedure, load/unload, shift, capture,
sequential procedure info, edt clock, edt update, edt bypass information etc.
 SDC files: Synopsis Delay Constraints, contains timing information like false path,
multicycle path info, etc
 Log files: contains all the report information
 Run files: contains the path of the netlist, library to execute the operation

ATPG Outputs:
 Testbenches: chain test (Shift) and shift & capture testbenches for serial & parallel
simulations. These are the inputs for simulations
 Cycle counts & Pattern counts: contains how many flops are present per chain info &
how many patterns generated after ATPG
 Coverage reports: contains fault coverage & test coverage info
 AU fault list files: contains the info of ATPG untestable faults and why the coverage is
less
 Scan chain & Scan group files: contains number of scan chains and scan chain group
information
ATPG Faults Model
A fault model is something that could go wrong in the construction or defect of design.

A good fault model should satisfy two criteria's

 It should reflect the behavior of defect
 It should be computationally efficient in terms of fault simulation and test pattern
generation.

There are different types of fault models

 Stuck at Fault
 Transition Fault
 Path delay Fault
 IDDQ fault

Stuck at Fault:

 The stuck fault model is the state of logic signals on a line in logic circuit
including primary inputs and primary outputs.
 It appears to be stuck at a constant logic value
 SAF done at slow clock frequency.
 stuck at fault models perform get the controllability and observability of the design.
 stuck at – 0 fault: It drives the constant logic 0 value.
 stuck at – 1fault: It drives the constant logic 1 value.
Transition Fault:

 A transition at any node means that the effect of any transition from 0>1(slow to rise)
or 1>0 (slow to fall) will not reach at primary output or scan flop output with in the
stipulated time
 Slow to rise: when the system is at max freq, it is unable to produce transition from 0
to 1. OR gate is used for 0 to 1 transition.
 Slow to fall: when the system is at max freq, it fails to transit from 1 to 0. AND gate is
used for 1 to 0 transition.

Transition delay fault testing approach:

There are 2 approaches to test transition delay:
 Launch On Shift (LOS)
 Launch On Capture (LOC)

Launch on shift (LOS):

 Here the data is launched from shift path ie, when SE=1 and capture is done from combo
path ie, when SE=0
 But SE changes immediately, that need to be taken care or else it reaches metastable.
So to add delay for SE to change from 1 to 0 insert pipeline registers which adds delay
ie, Launch on extra shift pulse.
 Coverage is more
 Less patterns
 STA is difficult to meet
Launch on capture (LOC):
 Here data is launched and captured from capture path itself ie, D path
 Both launch & capture happens when SE=0. So no need od pipeline insertion required
 But SE remains zero for both launch & capture, hence coverage is lost
 Patterns is more because the patterns comes from combo path
 STA is easy to meet

Path delay Fault:

 Path delay fault model defects in the circuit path

 Testing the combined delay through all the gates of the specific path (critical path)
 Propagation delay of all paths in the circuits must be less than one clock cycle

IDDQ fault:

 IDDQ testing is a method for testing CMOS integrated circuits for the presence of
manufacturing faults.
 This has the advantage of checking the chip for many possible faults with one
measurement.
 Another advantage is that it may catch faults that are not found by conventional stuck-
at fault test vectors.
ATPG Faults Classes

Fault classes means it is a set of class where we can define the fault models
There are two type of Faults classes
 Testable It could able to detect fault while performing the fault model is called as
testable faults

 Untestable Untestable (UT) faults are faults for which no pattern can exist to either
detect or possible-detect them. The tools acquire some knowledge of faults prior to
ATPG, they classify certain unused, tied, or blocked faults before ATPG runs

Untestable
 Redundant fault
 Tide Fault
 Blocked
 Unused

DI (Detectable Implication)
Testable
DS (Detectable simulation)
• Backboxes
• Pin constraints
Possible Detectable • Insufficient Seq depth
• Analog boxes
• Tide to unknown logic
• Non scan elements

Pos Detectable Testable

Detectable
Pos Detectable Untestable

Uncontrollable
ATPG Untestable
Unobservable

Undetectable
Untestable:
 Redundant fault:
The redundant fault class includes faults the test generator considers undetectable. After the
test pattern generator exhausts all patterns, it performs a special analysis to verify that the fault
is undetectable under any conditions

 Tide Fault:

The tied fault class includes faults on gates where the point of the fault is tied to a value identical
to the fault stuck value because tied values propagate, the tied circuitry at A causes tied faults
at A, B, C, and D.

 Blocked:

The blocked fault class includes faults on circuitry for which tied logic blocks all paths to an
observable point. Tied faults and blocked faults can be equivalent faults.
  Unused:

The unused fault class includes all faults on circuitry unconnected to any circuit observation
point and faults on floating primary outputs

Testable:

 Detectable:
The detected fault class includes all faults that the ATPG process identifies as detected. The
detected fault class contains two sub classes
Det simulation (DS) - faults detected when the tool performs fault simulation.
Det implication (DI) - faults detected when the tool performs learning analysis.

 Possible Detectable:
The posdet, or possible-detected, fault class includes all faults that fault simulation identifies
as possible-detected but not hard detected. A possible-detected fault results from a 0-X or 1-
Xdifference at an observation point. The posdet class contains two subclasses.
 ATPG Untestable:
Untestable (UT) faults are faults for which no pattern can exist to either detect or possible-
detect them.
Untestable faults cannot cause functional failures, so the tools exclude them when calculating
test coverage
• Undetectable:
The undetected fault class includes undetected faults that cannot be proven untestable or ATPG
untestable. The undetected class contains two subclasses:

uncontrolled (UC) - undetected faults, which during pattern simulation, never achieve the value
at the point of the fault required for fault detection-that is, they are uncontrollable.

unobserved (UO) - faults whose effects do not propagate to an observable point.