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Cache Performance Analysis in RISC-V

This program accesses an array in different ways to demonstrate how cache parameters affect performance. It contains an array and loops through it multiple times with a given step size. Each iteration can either write a 0 to each element or read and increment each element. This is done to model cache behavior under write-only or read-write access patterns. The program outputs are meant to be analyzed alongside a cache simulator and visualizer to help students understand how cache size, block size, and other factors impact cache hits and misses.

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Daniel José
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15 views2 pages

Cache Performance Analysis in RISC-V

This program accesses an array in different ways to demonstrate how cache parameters affect performance. It contains an array and loops through it multiple times with a given step size. Each iteration can either write a 0 to each element or read and increment each element. This is done to model cache behavior under write-only or read-write access patterns. The program outputs are meant to be analyzed alongside a cache simulator and visualizer to help students understand how cache size, block size, and other factors impact cache hits and misses.

Uploaded by

Daniel José
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as TXT, PDF, TXT or read online on Scribd

# Rewriten by Stephan Kaminsky in RISC-V on 7/30/2018

# This program accesses an array in ways that provide data about the cache
parameters.
# Coupled with the Data Cache Simulator and Memory Reference Visualization to help
students
# understand how the cache parameters affect cache performance.
#
# PSEUDOCODE:
# int array[]; //Assume sizeof(int) == 4
# for (k = 0; k < repcount; k++) { // repeat repcount times
# /* Step through the selected array segment with the given step size. */
# for (index = 0; index < arraysize; index += stepsize) {
# if(option==0)
# array[index] = 0; // Option 0: One cache access - write
# else
# array[index] = array[index] + 1; // Option 1: Two cache accesses -
read AND write
# }
# }

.data
array: .word 2048 # max array size specified in BYTES (DO NOT CHANGE)

.text
###################################################################################
###############
# You MAY change the code below this section
main: li a0, 256 # array size in BYTES (power of 2 < array size)
li a1, 2 # step size (power of 2 > 0)
li a2, 1 # rep count (int > 0)
li a3, 1 # 0 - option 0, 1 - option 1
# You MAY change the code above this section
###################################################################################
###############

jal accessWords # lw/sw


#jal accessBytes # lb/sb

li a0,10 # exit
ecall

# SUMMARY OF REGISTER USE:


# a0 = array size in bytes
# a1 = step size
# a2 = number of times to repeat
# a3 = 0 (W) / 1 (RW)
# s0 = moving array ptr
# s1 = array limit (ptr)

accessWords:
la s0, array # ptr to array
add s1, s0, a0 # hardcode array limit (ptr)
slli t1, a1, 2 # multiply stepsize by 4 because WORDS
wordLoop:
beq a3, zero, wordZero

lw t0, 0(s0) # array[index/4]++


addi t0, t0, 1
sw t0, 0(s0)
j wordCheck

wordZero:
sw zero, 0(s0) # array[index/4] = 0

wordCheck:
add s0, s0, t1 # increment ptr
blt s0, s1, wordLoop # inner loop done?

addi a2, a2, -1


bgtz a2, accessWords # outer loop done?
jr ra

accessBytes:
la s0, array # ptr to array
add s1, s0, a0 # hardcode array limit (ptr)
byteLoop:
beq a3, zero, byteZero

lbu t0, 0(s0) # array[index]++


addi t0, t0, 1
sb t0, 0(s0)
j byteCheck

byteZero:
sb zero, 0(s0) # array[index] = 0

byteCheck:
add s0, s0, a1 # increment ptr
blt s0, s1, byteLoop # inner loop done?

addi a2, a2, -1


bgtz a2, accessBytes # outer loop done?
jr ra

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