Conclusion: na = 4 om Hovusental Dis = 8.9 Vagdteal, Diulaiens me biw = 2 {2} What is the highest Gequency that can be measured by C.R.O. available in your laboratory? Fe anor fas pot pos Mat, BI futis highest voltage haiaebe Be by C.R.O. available in your laboratory? ey [4] What you will do 1o measure voltage which is greater than voltage limit of the C.R.O.? : : Aunoultiby _heaeres a Andi (6] What do you mean by dual channel C.R.O Page 7 Edited by : Vaibhav Neema, July,2011A cro, witkh 2 wilical wer that ant pul’ bused with c oe hag trum __togethin mu Thun Prieur othr Sup dine L203 Sob cabal ainda geet Mhirt 2 uapuls arr. pubstra nh Fe pred of de ot mecbenitin sonb'te cit.0,-Cecdonuet etetron beam? sit _orallortope ina ivaleuanust _uahich con = 8 i 4 arn. ay abe pound by “fk 2109. 1 ‘it to test hl CRO. prove is in working condition or not? De ert oe _-auny cena chur —-1£ che hye Ff “a phi oneal doa doa er eee on allesVette al Hager zontal 4 litude : fii =4 I Oey} 1 8 2. Frequency: 10-8 kKH2 ) | ac NedticaL pis 2 zontalce aveforms of sine, square, ramp and ceisngutar in the tiven ace. tt WORKSHEET ¢: Observation table: Fonetion | Vertical | Voli? atv | Ampiitwde [ itorteont Timed | Time Division b) (pp) al Div. WW (a) Veath «) (a) \ | 7 | ‘in Ls 2 18 22 |S |i0 49.09 | 4 2 4 bY | 50 |4o |e | g | 2 3% IB | £0 | 90 om iad 3 2 Q | £0 |% Hh} ay 2 4 50 | 0. 4 +28 3 2. To | 90 4 Triangu | s a? So | 92 | log lar wave | aa | 2 v0 3s sal g 2 fo |Jo | thy | Ramp Wave Draw observed waveforms: y: 14:28 keHey Sine wave: (Amplitude: 4 Frequency eyJAPERIMENT NO, 2 (A) penne neter aes OF PN junction diag ame? ec 10" eel yetor dee is formed by doping Ptype in at oneigponi another side of the semicond MPMCINY IN ome gu eee in the following lure 100 CYA loving queen Jnnction hs 2 Maan Depletion rene 1 initially free: ehapge carriers from both side rec n arom in Poside yy charged ions iv P side of junetion(a tivély charged ion) and pos Jectron 8" iden acom im 0 ion of 8 i es positively charged ion ri called as depletion region. F prevented because firs kept at distance BY yn dotted in the above HENS ‘de accepts hole ic region. This region dep when voltage is "Ot applied shown in the above figure. WI terminals of the on polarity of DC supply: [1) Forward-Bias Condition Ve verininal connected to P-tYPE material & the circuit diagram, (NE diode 15 foward bias vourage Wil force material to recombine junction. This reduces increase in. majorly carriers iu depletion Te between the (Wo rther recombi nf the depletion voltage 8 depletion (acts sitively charged donates electron and ere of any type of free nation of free erated as a sort of gion forms 4 ending of the battery al as shows i fication ofCirewit diagram (reverse bi verowsr rere 2 :: WORKSHEET :: Observation table: (Forward bias) CSZLcon) | ‘Sr. No. | Supply voltage | Diode voltage | Diode current { (Volt) (va) (ia) 0 ' 0.0 aces oO [old x no" 205 xi" | 40X10 | [Link] x0 | ig.o8 x10™” | ” page 11/60, 2022 og by : Vaibhav Neema, July:Observation table: (Reverse bias) | [Link]. | Supply voltage [Diode voltage | Diode current ‘a (Id) : & } ( Ci (be) T. 0 0 0 2. 2 2 act leo 4 o 0 6 0 O_| & a 0 lo o LO I+ 0 | 0 4} 90 | 0i eel da Doda Td C ium)Conclusion: Aden. i an bined s Gumwal baruany slowly Ua Vales, {1} List important specifications of the diode Th_simps a ication ane - _Cunnuat. folas SdlunationCunnuut 1 brtakdewnvaltags Mat. pour disaipatid Lwil, cabacitowce Huh ue. [2] What is breakdown voltage? What is the breakdown vol 1N4001 and nt ee seek eta. mandoninea alta. id « ta nua “ban plage ANON in Sov ¢ r00 © of diode aaa — that. pina (3] What is the highest forward current ics de 1N4007 and 1NS0027 PLN ee = key »- aida aM Ri ce di’ ig a a 1 Chimear._ died) sae te i dir yates, ie ciety fen } chy corabecuee! di ody Vr sei i elt Parse 13 168 Aes+) Photodiode ant upid JLED an uncd._in Ret the —-—--— ee [8] What is the forward voltage drop; alaam._ Ayatian , Optical. Communication” ite . [6] How to check diode with help of multimeter? Addon suits in diode check rmeds| as Photodetidar I> ditict opti Remati contol ‘bunglon “Pei h- th da died. Thy te tnt To chide mum blacking Tee_calyads 6EXPERIMENT NO. 2 (B) AIM: To obtain characteristics of light emitting diode (LED) Introduction: LED is semiconductor junetion diote which emits fish ‘ fh it in forward bias condition. P type Oates eevcists of large number of holes while N type of semicond igen rope momber of electrons. Al zero bias (no voltage toe depletion region exists and it separate out two regions. When LED Libro deroemtarrier potential reduces and depletion region bec ee Piestron crosses the depletion region and recombines with poles, Simla per frosses depletion region and recombine with soa tach hols ination of hole and electron produces photon (light) The io on the number of mino Stee light emitted depends rity carriers available for pecombination. Wavelength (oF frequency) of emitted Tight depends on cand. egy. The light emitting diode works by the process of spontaneous gep en emission. band gap. In a direet band gap ly across band source material rivst have direct d hole recombine direct! efor material electron an need of third particle to,conserve are made from,gsqownd of ement The wavelengthiygencrated DY spends on dof d bandgap energy 4 5 tion between frequency ¢ Light semicondu gap without momentum. group-lk (ALGa,tn) the LED g level of ¢ material ([Link],Sb) © ay an ndecstand rele Light soures and group-V nds on bandgap ener! 'F emission depe above elements, Let us U and energy: sie emitted frequency by te LED { photon energy is related (0! a photon eneray E=W = veto at because ‘wavelength a5x10-34 I+ yuere n= rank’ constant = 6625200 41-8 eight = «108 m/s ¢ = Velocity of th Wavelength of emittedExperiment Procedure: Connect the power supply, voltmeter, current meter with the LED as shown in the circuit diagram. Increase voltage from the power supply from OV to 20V,in step as shown in the observation table Measure voltage across LED and current through the LED. Note down ings in the observation table and also observes light coming from readi LED. Reverse DC power supply polarity for reverse bias Repeat the above procedure for the different values of supply voltage for reverse bias Draw VI characteristics for forward bias and reverse bias in one graph Cirevit diagram (forward bias} Circuit diag? (reverse bias):(pA) adenoa apoid. “¢seyq asx2aay) :arqes ToHIeAI2 SIO adeypoa Atddng | “ON “7S It! el oc 8 r 0 “FR 1 $1 L t o 66:0 1 9 ° GEO #0 s © 09°09 a + ese] 1h-0 ig v0 eee 0 oT Y zo z 9 0 0 1 wp (ew (ea) iwesses spora| odenes opera | eenes Siddus | “ON AS 6) MOL EAIO (eid paemsed) & Joa SsadOM ©Salar” . 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I-A uyergo OL ATV (vy) €'ON LNGWIAAA XaCircuit diagram (forward bins): Gy $ minis F (v) pe rows | Sore xz His | [ :: WORKSHEET :: Observation table: (Reverse bias) Diode voltage (Vz) Diode current | (lz) Supply voltage (Volt)abe: (Porward bins) Observation Diode voltage | Diode current (va) (ld) oe ia a a of _[ te. 0 7 oa) 7 2 : sok En a -_ 4 4-0 o : . 5.0 0. é 60 0 Zz Page 21/60, Edited by : Vaibhav Neema, July, 2011photo iy ur (ovqdoy A men mopyea1q s9u AIG D9UDHONIp oy) cgrepaorcg ye wer rporp vias of (WIR 5 OF ~) pnp Fam _ MOY ea1q St eum [p] grrr yn —orevepw 3 Reape bende ny Pari ay TW0Oy By nr op WIT van up UNBAN 498.U9] 40) uorsox UMOPHEIIq UII d}es9d0 v9 8 aporp sau: ‘240 Apersads ay) st 1eym [¢] E "cy ___Phovyono 24 Wor rporp COT T b rf hore pop Oth —comep por op OT IG rm Ng hae Bethan POMP U2 Swern Ng Teenage on "1 Wo unopyeoig hae gtion © guonesap 19800 Nd ewiou sywisdo om uey (al Low oxen — oe cee Corre uns OXI fry Apo rsp 7c a Prt von vy pr BHOR-progarHUE — Vey W spomp wn5] Draw Zener regulator circ MI (6 obtain regwiated De i ; ed DC voltage Considering input DC voltnge tn the range trom tov. 10¥. 0 load resistance of 10KQ, Consider e aunt Vis Wo-an)y Ia, Ve = way ui = tL PL= toma = vy fr (71 Draw output waveform in th Uit of question 5, 10V at the inpur ifwe apply AC wave of Page 23/60 Edited by : Vaibhav Neema, July, 2011Sa EXPERIMEN, nv Zener diodes tine and tod ep, NOs) *RUation AIM: Introduction: b ede Alef imsy zemwt th Vawatton. head cgi ‘ uma valtag, @ ae rly, Sinner Joad suristure uh ~dfarum dale di SL aad Oba ae dl |! head Regul atten lola | : Page 24/60, Edited by : Vaibhav Neema, July, 20113 3 to Draw characteristics veyObservation table: (Line Regulation & Lond Regulation ) Vina = Coast Sr. No. Rr (kn) Vi Va o 0100 9.25. t Bar 9.25 2 5.08 gar 3 5.72 gos 4 SRE gis s 5.5) gus 6 5.93 Gos | S098 gr a guar 4 ae See to Geis TT i Al Page 25 / 60, b Edited by : Vaibhav Neema, July, 2011yroz AINE vouaan aeuaTen “p9/ 92 o8ed + Aq peated guopeyatoy poor jo sopisarzered? Sed. oy 1K i) vouvptey poe sone WA “oN AS wi WONwAsaDMOEXPERIMENT No, 4 Amer eien pt i snr wise wed clipping and clamping o, pitt 9 ehane DC level (average Jeyely nb SHU, Cha Pre 1828 Me atue With tHE SIENA. In clampige he RAL whe nes ue (DC level Ping, sh whieh samt ic 3 D will change meee? of waver th same Om pe signal WHE MCEDLve clamp, sitive clamping aug ting pc el acitor is Widely used in the 8 AddS negative pos Posing signs COPE ne sinusoidal signat ig aameing Circuit Tei in th wee ; shown below ical clan waegsie cmon "ow for positive lemoat ping x) “ty 0 : te Jnl an Sz or Sinewave with average valued oo. Mee Sine wave clamped to postive level Vin mtn 19 negative level Yn Clamping eireuit is used in video amplifier of television receiver 10 restore DC evel of video signal to preserve overall brightness of the scene, Clamp !ng circuit is also used in offset control of fanetion generator, Zero offset menns no DC value is added in the AC signal Circuit operation: ping and negative clamping is Typical cireuit operation of the positive cle aiven below. Page 25/60 paited by : Vaibhav Neema, JULY,Positive clamping: —_ wh LG Consider that 4V peak to peak signal with zero offeet is applied at the input of the clamping eivevit. On the first negative half cycle of the input tignal, Giode D turns ON because anode voltage is greatcr than cathode voltage Capacitor charges to the negative peak voltage let us say -2V in our example, The value of R should be high so that it will not discharge the capacitance. Afier completion of negative cycle, positive cycle starts and diode turns OFF. Capacitance voltage is in series with the input voltage. As per the Kirchof’s law oviput voltage will be addition of input voltage and capacitance voltage. lap, signal is positive swing of 42V and capacitor voltage is 42V. Thus during the positive peak of the input voltage total output voltage will be +4V. We'cain-consider that during the positive cycle capacitor acts like a battery and’iidg2V in the input, Waveforms are drawn here considering idcal diode, ‘névigskage in the capacitance under ideal situations which will be different in [Link]. Negative clamping: 4 nto In a negative clamping cireuit polarity of diode is reverse than in positive clamping. In our signal input swings from -2V to +2V (peak to peak 4V). Diode turns ON during the positive cycle and charge is stored in the capacitor. Capacitor will charge up to +2 V in our example. During the \ negative cycle this voltage will be in series with the input voltage and gives. total output -4V during negative peak of the input signal Page 27/60. ane ramme t won rte Lhe worsn{Iu0Dits if input of AV peak- the following circu ied. & $s ae Be 22 [1] Draw 1 to-pea.* usous dino puv so1sts219esPu> saysuray, 2P0!P duo 21982 2ars0d 1 umoys 248 SUNIIIO 4 aura aaddyy> 21942 2 soy wsoyaea ? andy 2) U! sy andy (epost qungs pue 821195 arsed sym: Ss -qioy paurejdxa a4e SoZ saddyjo 9w0s “S39: rug aBvyjoa se umoUy OstE ose syns Surddy 194 40 2009 WOJ2AEA “TPAAL ‘pouosajo1 wos yo advys aasssoad 10u s00P HNN aurddua nosy Suyduely “S492 UHL a8 ey]0a vyaem ayy go uols0d OS «SAI, fa] YoryA WILOJOA A nosto 8urddia apaindure 30 491 5 sou2s9go4 St) AO 19 ‘wo}[Link] yo odeys sonsosoad 1 dy) “wa9y ‘uo Mojaq 40 9408 ajas 0) pasn st HE =paddyo s1 (242 sosn iynouto 3 anya wsojaaem 24 sv 0} passajas osye asv ynosy> Buy ata Surddsi “fandt 99939591 Aseaygae ue jo wed yey) woEss}UUsUBsD 40} I yuo} 9NPOLUT syymovo soddy9 yo vndgo aq ve surzojaaess 240800 OL STV § ‘ON LNSWIAAd XS01 895! aw u aynyo voruod ial sed 2196 1 umous ésnuj 092 Se ava 1ndUt nau: uontpuoo NO’ no Jo wo!s0) ou sf WON pi st a 2p qejene st wsayanen V yoo grey 2amisod jo wonsod omer ig ajoko aa oy yuem you op 9m go [ryase 81 StL ‘POS yon 29u9s9}93 9 umoys yao 20) UL seouasayoa aayysod aya Suyadyya aarazsed 2PO!P sapos wou Jd sands 21989 24! ips} wuaojoavas 10dUt aoe) WF 8) c1 2pOECT “OSC URMAL ¢ i ynduy 2udy PU PERT uy sec] 2pordl *O>(0) WAL porp yunys 10d assaaai st aporp Jo Anaviod }ndyno ayy 1 outta wos dd ¥ 2m sou pur wor ‘yadino oy) aia waw JOU sp WO} 9AU iy oyy sauddq Yo}yas WOHPUOD NO[ oS ‘09 / £¢ abeg : sdi9 4A~ moy2q 219K9 2A vou Jo wopsod amos pur 21249 aansod ainua sn, YA 01 eMba uEIsuo suremas aBeW0a nding “indino 9yto1 papusixa 5 aA a8eyor aanvou pue rndino 243 re a1q) JOU s WLO}AAve. Indu ‘uorpUOD NO UL St_G apoiq “A= <(i)'A Udy + Indino ayi ae aqepear st wsoj2aem wado) wortpuos AAO Ut SIC] >POIq HA->(I)!A UDyA & Wwa0Janem ay) UL UMOYS se 219K eaneBOU Jo UoNIOd 2wos pur oho oarnisod aayiua dijo {um stu “Uno419 Zurmo|jo} 41 UL UAOYS St 8 oBeyjon souasajo4 oanresou yur Burddry9 carutsod aporp iunys raBeroa aoudiaggas yeSau qyim Surddyya aarsod aporp yunys, get WA- 01 [enba 81 yoiym iueisuos suiewer aeijad,rtdjno pue yndino ayy I aqzy eae JOU Ss! Wioyanem indur ‘uoNpUoD a0 2 CeO sindino ayy SE. 9pord MA-<()'* HOU ws as -ajoko aateBau jo uottiod amos dy qi sty, “22n8y Burmoljoy 241 UL UMOYs st dFUIOA DduUDI—J01 oALeZU yu soddyo ANeTON “sporp yr Jo Aysejod SuTuryo Kq porsyoe aq uvo Surddyo oanedon raauarayar yyy Buyddy]a oayyesou aporp Say9g *sdi]9 ¥A~ moJ9q 9949 ony¥BIU JO Uo} 20d ows puY aJoX9 aAagysod a4NUI SNYL “% 0 jenbo yuvisuos suyeiuas jndino pue indino oy) I aquieae JOU Sf wsoJ9AvMm Indul ‘uOPFPUOD Ado WE st q aporq “WA <()IA USHA + syndino ay) J a1qviEAL 51 wisojeawm rnduy ‘uoHIPuOD NO UY SEC aporg HA->Q)!A UOUAL &Circuit 2: Circuit 3: Circuit 4:cae shunt diode negative tlipping with negative rete renee net cning mith epi eae gi " je can 1¢ diode. Some portion of negative ue I reversing polarity of dition (open circuit) and input 4. When witb-Vis Diode D is in OFF available at the output put waveform is not ON condition, im tinge Ve is extended 10 the to Ve. Thus entire positive =Vie clips. waveform is 4 When v(t) < ~Ves Diode D is in available at the oucpot and negative vo Gutpur. Oucput voltage remains constant qv cycle and Some Ps negative cycle below put vol ortion o| Experiment Procedure? 10, set sine wave with 6Y peak 10 generator Wife CR et voltageis 0. enerator a the iapdbor the clippi Connect function wn the CRO for different clipping circuits peak. Ensure that offs _ Connect the function & wy iput waveforms 0 waveforms. WORKSHEET 2 itable in th circuit ¢ laboratory oF ons (as per eiseuil 2” w circuit diag Hr feted om breadboard) Dra’ uit con!Waveforms: LJinput Wayeform: + oq ven al Lay i | {| + { CIE put waveform for circuit 1 i i Out EeConclusion: ip madwa slo oie lay — 0 Pe ang diy fu sm u) wauepore : questions:qroz/Atap ‘ween aeuaten : Aq paatpa —s~ "09 6 962d 4 eu “osoz $1 a8ey}on indino 29494 apoip ay yBnosyp sossed 1u911n ON “se1q 9819404 UI SI 9porp pur 2poyied o1 paisodsos yim aatiefau st apoue ‘afeyjoa Indu so 91249 sey aatredau Fung ry 20unrsisou peo} ayy ss0s9e $doj242p 21249 aalusod pur aporp aq) 4a nosur sossed juszmo pur s¥sq psemsos ul si aporq “apoures ay yu poredwoo sod st aporp aya Jo apoue a8eyon rnduy ayy Jo aKa yey eantsod Busing “a1n8y Sumoqios ey1 vi UNOYS sf JoNDEdeD THOYNM sO1)N922 ALM jrey jo wesderp ynoal ous “21K9 aaiuisod Sursmp siompuos yorym pasn st ‘aporp 2u0 Sug “pasn roM st (212K9 sAnreBau) aBerjoa Dy Jo 21249 H1ey sMIOUY pasn st a8vyoa ay poifdde jo 21289 yey fluo soyri99s aAvm Je UL “aypoar aaea grou Jo apd}ouud Bup [094 sayyioas anve seq yonaisuod fim nok “usiulgado sry) ap ~s9y11993 a8vH ILA pue soynioas anem slep :s21s0%0r¥9 om) o1UF paplarp ATpeorg s9yTI99y I94NID9E so) 214eWAs aouay Kusdosd jeuonsauprun sey Speug “e1ap jeuorrsosprun Hyuossq “Jus1N9 10 aBeyOA [Link] rut spoau sysn904 iuaisns 40 a8eyOa ae JsaAUod O} pasn as1A9p suosOA|9 UE se pouyep aq Kew saypiooy “saytioos st Ajddns somod Dq Jo y901q 1844 Oy, ‘AxessaoaU st Aiddns samod Jo uB{sap sodosd waysks oquos199I9 oy Jo eoUEuIIO}Z0d PUY Am!qeHOt DW, “Ajddns samod Qq ynoyN “919 JIOUKT|NUE ‘OY 2! s1uowiANSTE Gursnsvaw sv fjom se a[lqout ‘ouoydsja1 ‘orpes *soymdwoo ‘worstad}oy JO YUH ues 2m ‘ajdwexo soy “ysnur sj fjddns somod “Q'q ‘srusuidrnba 2}u031031 WY ‘uo os pur ssoyydwe ‘ss0r¥; onoaja ye 92829U9 61 somod sopinosd 1} osmva9g Sf SttLL “VusMdInbs o}uond9[9 Kuv Jo 19LHa|> iwenoduy ayy st kddas 490d DG “OG Ov QV weruos oy 42yH9eH ESE Aiddus somod aq uy 81 9po1p Jo suon voy ddy wvrsod wy L490 24 JO 240 oyanpoayuy ovdva sayy Voy PUB UA dds “yyossna gq ‘edNJos Qa sinswou oy soHsEdeD 911 ROU 0 ayy Tw wiTOj9Aa 2429840 OL ENIY wy pue s9ypioo4 on va Le 9 ON LNIWINAAXHale wave rectifier without filler eapacitor convert AC voltage int pulsating DC voltage. Fiter capacitor is used to obtain smooth BE volts - Construct following circuit to perform this practical : Practical Cirenit diagram: 194007 c avec Ie 10004 T \ List of components: 1) Transformer Input: 230V AC, output: 12V AC, 500 mA (2] Diode 1N4007 [3] Resistor 10K [4] Capacitor 1000pF [5] Toggle Switch ose PCB. Keep toggle switch OFF to Construct circuit on the genekal purp stifiefsyithout filter capacitor and ON to perform practical of half wave rect connect filter capacitor Waveforms: [1] Without filter capacitor Input Waveform at secondary of transformer: Tm i T | T + Lf “Output waveform: Vo 4 / 0 ff Page 40/60 Edited by : Vaibhav Neema, guly, 2011[2] With filter ca} rf Input Waveform at secondary of transformer A Loe Observations: [1] Without filter capacitor “Ee. ‘AC Input voltage (rms) Vims= 63) =_2V— DC output voltage Voc = foe = = AC output voltage (Ripple voltage) ve:_4 ple factor: (Vil 7 ee DC current: Rip (2) With filter capacitor (rms) Vrms= 2a AC Input voltage DC output voltage Joc = AC output voltage Ripple poles) ve Ripple factor: (Vi Voc) = et vaibhav Neemay Edited by +| | pom Hit 4 mm fr ps ei © ar enor ws —genportTy | UOTE at Ts otits 2 aNOUUE Cage wpe fi prvre’ 1% “pou 99 90 wo 2p Pe wet nay = ero fone ms veges foramen TH rbuxpen “AtTg jsonsede> sony 30 4h wy afvyjon apddts uo 29u0)S15% Peo! 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To measure DC volinge, without filter capacitor Introduction: which converts an ac voltage to de voltage ‘The Bridge rectifier is a circuit, Bridge rectifier circuit 1s using both half eycles of the input ac voltage. The shown in the following figure. Prom races bee ron “ene 9 putaneg ara tage of tap Da 2a ee sso con oT emmene bel nected to form a bridge. The ac input s af the bridge. The load ‘ds of the bridge. For the D1 and D2 conduct e conducting diodes ¢ load current flows diodes D3 and ting diodes D3 urrent circuit has four diodes con the diagonally opposite ent 1d between the other two en put ac voltage, diodes the OFF state. Th ce Ri. and hence th put ac voltages ‘The conduct and hence the © aif cycle. Thus & The voltage is applied 10 resistance is connecte positive half cycle of the in Pinereas diodes D3 and D4 remain in Will be in series with the Toad fesistan through Ri, For the negative half cycle of the in Dé conduct whereas, DI and D2 remain OFF. and D4 will be in series with (De load resistance Rt flows through Ri in the same direction as in the previous by ireetional wave is converted into & unidirectivaal wave: page 47 / 69, gdited by : vaibhav Neema July, 2013fq partes payise? 24 gow yorum id oumon ou 2Aey 202008. gyddns pue 22uersis?! prol * “paanbas st (AS 224) ‘s3)) 23 v1104 OL UUM fuejnoned cowarayys 290924 1a SL -gapoip ont $S0298 JO4P paeyjoa psemsod * {as00 mor sf 980908 aay soporp nod S2210b9H * saaggy291 98PHA J? sodeyuvapestd -sajako oy qnog Suan fant aay pain s! s0uz0)SU00 Yeo u94id 40) post nbor ye anaoysweosr 221s 2211eS gauyii924 asnn99g 41198 yao uf ven J0udiU 8! 0728) HORS a s91us0}3 PAL we ea sre st aparP 2400 Ald >A yadwo> pue ry dey 30103 yon ‘01 paydde K9941P st aged 91 ‘uvay ueys p2s!nD2 ne a} disap 22ws0}SUeN 591029 0N * sayniv2: 28p13q Jo" ‘AL ot posn SANS # aurddas pueda yasinbos st de you umop MOP ae epuoo3s saTybrgues OM eet ag, oun aspuq yo s2de7U24PY ie or vu OOS my pavyoud YI 25m UL? nok Hitand 10182092 20 “WO taoy Sudues somroedeo 1092382 Srotreiiggpjonseu amy OF aAETENS apse fr (oRp1zq Jo. twsop ut saporP 270} JO von dWigusos) Beyond 729224 o8pug ° AS a poto 99 veo 991 padder-soyuaa se 119m SE AUTEN U st sounysiso2 pe aBans ojpuys “o1ndy ayy us wmoys SE SEEDS f sat au) Jo Kupedua Be ed adans uuu of, ‘9posp ou oR vurep eo af 2poF ans ‘smu, Wn: = pores spoooxa juasino a82ns Jf ‘98421 Aa94 St | Hn Bin ys ¥ oyf] sioe sonoed 5 *319h9 984y owdo dyyuppuy 9818994 $01 1) 94) Bujsnp so¥seys sonoedva vaya “22ndy 4 eee eae 3} OY) UY vmous sy a youdeo sony yajo 2oynos ai}pysq ayn jo west 1991 2AM INqtoz ‘Ate ween aeuaten + Aq peated ———$—_—— ‘09 / 6b 362d % ussogoaea 104119 T_] | | EE CRBS | wr ousoysuean so Ksvpuogas 2e waoyoneay Indu] sonoedva sony Ino 4A [1] mS ? son2edes 45 rnoquun 1sBses, nem (10) 30 dandapioued aq do ynas> 1MsstoD 5 } MOT s0NStS°y [eI 01 NO pue sonsedes 9 01 440 yottms 318801 davy “add 250! yous 918804 [5] atonor b2ede9 a vyaed soynoos aBp}1q V | 10 ‘hy ---- LOOPN] 2pord [Z] var gos ‘Ov A ZI 29mojsuedy [ :siuiouodwos Jo 1s¢] ae1t0z ‘Arne euean aeyqrea + Aq peatpa FT AA (OB e0a addy) oFer0A rndino Oy PES 2A (eyon apddryp aero 1nd190 ov 09 / 0¢ abe a =r SG = (294 144) 20298 apddry PUTT tuansn 9a FETE = 2a, aeijoa indino 9a RBTOT =susq (sw) Benoa indut oy soysedeo 19) is [2] ERO = 04a 0) 130198) addy WRrottuzsan9 0a = 90, aBeroa yndino 9q Yay sonsedea samy rnoyitay [1] rsuorwarasag ; NZ | Kavpuooas ve wsajeavyy 1AdUy suvar go Sapunyoudea JNU MA CHConclusion: Gp buidge Peclt fin un t only port ur ha Sti Ail et Questions: 11) ha isthe mathematica expression for ripple factor. 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