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Cmos

cmos vlsi

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34 views6 pages

Cmos

cmos vlsi

Uploaded by

Praveen kumar
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
barks Department of ECE, NITK Reg. No: Sem [Link] MOS VLSI Mid-Term Exam Duration: 90 mins. Sep. 23, 2019, 8:30 10:00AM Marks: 20 Note: * Answer all questions. Draw the circuit diagram, label all components and the size of each transistor. Tabulate the computed results at the end of each solution. Also mention the region of operation of each transistor. + Assume Vpp = SV, Kn’ = S0HA/V?, Vrw = 0.5V, length of all transistors = 1p. Voltage levels of logic 'l’ and logic ‘0’ are SV and OV respectively unless specified otherwise. Use Re as taught in the class for computing /estimating the equivalent resistance of the MOSFETs. 1. Design a enhancement NMOS load inverter forthe following specifications: Vox = O.1V, Ci = Ipf. If an ideal step input is applied, then the rse-time ofthe inverter should be 2.2ns. Compute the sizeof the transistors, and the power dissipated by the inverter when input is high {10 marks. 2, Design an NMOS inverter with resistive load for the following specifications: W/L of MOSFET 7) Compute the value of Re such that Voy = 0.1V when Vi= Vao. Identify the region of operation of the MOSFET when Vi = Veo +b) Compute the output voltage if Vi = 3Vand Vi= Voo- ©) Compute the current drawn from the supply when Vi= 3V and V1 = Vio. 4) Compute the power dissipated in the MOSFET when Vs = 3V and Vs (10 marks. NGINEERING DEPARTMENT OF ELECTRONICS & COMMUNICATION ©) NGRATHKAL NATIONAL INSTITUTE OF TECHNOLOGY KARNATA! a ‘Mid-Semester Exarnination - ODD 2018 EC-701 CMOS VLSI Max. marks 25 Duration: 99 minutes ee

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