3.

8 Classification of Output Stages:

3.9 Class-A output stage
(1) Transfer Characteristics

Circuit connections:
• The circuit consists of two transistors connected as shown in the figure.
• For the transistor Q2, the resistor R and the diode D provides biasing. The resulting
collector current I is constant.
• This current I of transistor Q2 provides constant current biasing for the transistor Q1.
• The input voltage is applied to base of Q1.
Operation:
• The output voltage vo = vi – VBE
• When the input voltage is equal to VBE, he ou pu vol age s ‘ ’. f he npu vol age s
increases above VBE, the output voltage increases as shown in the following graph. After a
certain value, the output voltage saturates when Q1 enters into saturation. In saturation, the
volage VCE(SAT) is constant (around 0.2V). The corresponding output voltage is
VCC – VCE(SAT)
• For all input voltages less than VBE, the output voltage becomes negative and the load
current flows through Q2.
• As vi increases in the negative direction, the output voltage also increases in the negative
direction as shown in the figure. The extreme voltage in the negative direction is
-VCC + VCE(SAT)

Thus, the variation of output voltage is from (-VCC + VCE(SAT) to (VCC – VCE(SAT)

The maximum load current is IL(max) = [VCC – VCE(SAT)] / RL

The bias current in Q2 = [VCC – VCE(SAT)] / RL

The emitter current of Q1 varies between 0 and 2[VCC – VCE(SAT)] / RL.

(2) Power Dissipation:

(3) Conversion Efficiency:

The output waveform of the circuit is as shown below. The peak value of the output voltage is:
VCC – VCE(SAT).

vo
Prob: 13 A class-A output stage has supply voltage of VCC =20V. The DC bias current is held
constant at I = 100mA. The load resistance is adjusted to get maximum output power,
find the maximum output AC power and the corresponding load resistance .

3.9 Class-A output stage

(1) Transfer Characteristics
Consider the following circuit diagram:
Circuit connections:
• One n-p-n transistor and another p-n-p transistor is connected together as shown in the
figure. The emitters of the transistors are connected together and DC supply is connected
to the collector terminal. Positive supply is used for n-p-n transistor and for the p-n-p
transistor is connected negative DC supply is connected.
• The base terminals of the two transistors are connected together to the input signal vi.
• The load resistor RL is connected to the emitter terminal.
• The transistors are not provided with biasing arrangement. Therefore, there is no bias
current is zero.
Circuit operation:
• Since the input is connected to the base terminal and output is connected to the emitter
term nal, each rans s or opera es l ke “em er follower”. For an em er follower, he
voltage gain is unity. Therefore, the output voltage is equal to the input voltage.
• During positive half cycle of the input voltage, the transistor QN will conduct when the
input voltage exceeds 0.5V which is the minimum voltage required to forward bias the base
to emitter junction.
❖ When QN is conducting, the positive input voltage appears at the output voltage.
❖ As the input voltage increases, the output voltage is limited to VCC – VCE(SAT) when
transistor enters into saturation.
❖ Thus, we get positive output voltage when QN conducts.
• During negative half cycle of the input voltage, the transistor Q P will conduct when the
input voltage exceeds - 0.5V which is the minimum voltage required to forward bias the
base to emitter junction.
❖ When QP is conducting, the negative input voltage appears at the output voltage.
❖ As the input voltage increases, the output voltage is limited to -VCC + VCE(SAT) when
transistor enters into saturation.
❖ Thus, we get negative output voltage when QP conducts.
Transfer characteristics:

(2) Conversion efficiency:

Based on the transfer characteristics, the output voltage waveform can be drawn as shown below.
Each transistor conducts only when the input voltage exceeds 0.5V. When the input voltage is in
between -0.5V and +0.5V, both the transistors will not conduct. Therefore, the output voltage is
zero. Th s resul s n d s or ed ou pu waveform. Th s s called “crossover d s or on”.
v

vo
 vo

(3) Power dissipation:

The power dissipation is the difference between input DC power and the output AC power.
3.10 Class- AB output stage
Circuit diagram:

• One n-p-n transistor and another p-n-p transistor is connected together as shown in the
figure. The emitters of the transistors are connected together and DC supply is connected
to the collector terminal. Positive supply is used for n-p-n transistor and for the p-n-p
transistor is connected negative DC supply is connected.
• The base terminals of the two transistors are connected together to the input signal vi.
• The load resistor RL is connected to the emitter terminal.
• Both the transistors are provided with biasing arrangement by connecting a DC supply
VBB/2 in the base of the transistors. The value of VBB is adjusted to ensure the forward
biasing of the base to emitter junction.
Circuit operation:
• Since the input is connected to the base terminal and output is connected to the emitter
erm nal, each rans s or opera es l ke “em er follower”. For an em er follower, he
voltage gain is unity. Therefore, the output voltage is equal to the input voltage.
• During positive half cycle of the input voltage, the transistor QN will conduct when the
input voltage exceeds 0V.
❖ When QN is conducting, the positive input voltage appears at the output voltage.
❖ As the input voltage increases, the output voltage is limited to VCC – VCE(SAT) when
transistor enters into saturation.
❖ Thus, we get positive output voltage when QN conducts.
• During negative half cycle of the input voltage, the transistor Q P will conduct when the
input voltage exceeds 0 V.
❖ When QP is conducting, the negative input voltage appears at the output voltage.
❖ As the input voltage increases, the output voltage is limited to -VCC + VCE(SAT) when
transistor enters into saturation.
❖ Thus, we get negative output voltage when QP conducts.
Transfer characteristics:
 v

vo

As seen in the above waveform, he ou pu waveform s free from “cross over d s or on”.
3.11 Class-C Tuned Amplifier

This circuit is used to get conversion efficiency greater than that of class B amplifier (78.5%). For
this purpose, the transistor is operated either in cut-off or saturation.
In cut-off, the current through the transistor is zero. That is IC = 0. Therefore, the power dissipated
in the transistor is zero. The power dissipated can be found as product of voltage across the
transistor and current through transistor. (Power dissipation = VCE × IC)
In saturation, the voltage across the transistor is zero. That is VCE = 0. Therefore, there is no power
dissipation in the transistor.
Since the power dissipation is zero, the conversion efficiency will be very high.
Circuit connections:
The collector of the transistor is connected DC supply through an inductor called radio frequency
coil (RFC). The collector is also connected to a filter circuit which removes harmonics to provide
sinusoidal output of required frequency.
Operation:
During the positive half cycle of the input signal, the transistor is driven into saturation. Then the
voltage across the transistor is zero. But current flows through RFC and the transistor.
During the negative half cycle of the input signal, the transistor is driven into cut-off and current
through the transistor becomes zero. The inductor RFC develops the induced emf and this appears
at the collector terminal. Due to the presence of inductor (RFC) and the capacitor at the collector,
the collector voltage is sinusoidal.
The collector voltage is as follows:

vn

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