Roll No. [[_| Total No. of Pages : 2 “Total No. of Questions : 09 [Link]. (ECE/ETE) (Sem.—3) ‘DIGITAL CIRCUIT AND LOGIC DESIGN Subject Code : BTEC-302 (2011 Batch) 4 : Paper ID : [A1134] +c Time : 3 Hrs. wey $60 INSTRUCTION TO CANDIDATES : or 1. SECTION-A is COMPULSORY consisting of TEN “Gdestions carrying TWO marks each. 2. SECTION-B contains FIVE questions an rive marks each and students has to attempt any FOUR questi 3. SECTION-C contains THREE question’[Link] TEN marks each and * students has to attempt any TWO questions. z SECTION-A Write briefly i) What is the difference between combinational-and sequential circuits? ( (i) What is Face’ around condition and how it is removed? (ii) Explain the propagation delay time in DTL. (iv)_Subtract using 9's, 10's, 2's and 1 's complement (18-24). () GC5)16 — UF7)i6 Jig and (235)g + (146)g (vi), Explain the D flip-flop and importance of preset and clear function. (vii) Explain resolution and accuracy of A/D converter. "(vi What isthe difference between multiplexer and encoder? (ix) , What is the difference between static and dynamic memory? ” (%) What is binary ladder network and its importance? JIN-12] (2) St115ta/514SECTION-B Explain the working of JK flip-flop using truth table and also derive Excitation table of JK FF from characteristic table. 3. Explain 3 bit Asynchronous DOWN-counter with the help of waveform. Design MOD-14 Asynchronous up counter using JK flip-flop. we) * 4, Design Full adder and Full substractor circuit using 4 to 1 5. Explain the working of simultaneous and Dual slope se 6. Solve using K map and implement result with the Bh f NAND gates only F,, cp) = ACD+ABD+ACD+AB+ABC, CS SECTION-C c\N 7. (a) Design BCD to grey code oe circuit. (b) Explain 2-input CMOS NOR 8 8. Design MOD-6 up-down céuster by avoiding lock out conditions using JK Flip-flop. \Y <9. Explain 2-Input NAND. ana NOR gate of TTL logic family. SO [N-12] (2) stustsist4Roll No. Total No. of Q ‘Total No. of Pages : 02 i estions : 09 B-Vech. |ECE/EE/EEE/EIE] (Sem.-4) DIGITAL ELECTRONICS | Subject Code : EC-204 | Paper ID : [40307] - oft, Time : 3 Hrs. Max, Marks 6 INSTRUCTION TO CANDIDATES : ‘ 1. SECTION-A is COMPULSORY. cute 2, Attempt any FOUR questions from SECTION. 3. Attempt any TWO questions from SECTION.C! SECTION-A (10 x 2 = 20 Marks) short notes on (@) Convert (241.35),9 to its detail and hexadecimal eqitivalent (b) Explain term Pan-i -in, Fan-out and Noise margin (c) What is difference: | fe signed and unsigned numbers. Ad) What is race. around condition in JK flip flop and how it is improved 7 : (c) Give tlie characteristics table of RS and JK Flip-flop. (D) Explaii difference between PLA and PAL ? (g) What is DCTL and explain its disadvantages. counter and Johnson counter, (h} What is difference between R race betwee! static and dynamic memory G) Explain term Resolution and Accuracy of A/D converter SE MON-B (xs 20 Marks) 2. A four -varinble function is given as /"(A.B,CD) = aM (Q34.,67.11,13, Use K-Map method te minimize Uw fanetion and re: gates only. 'h-12], (8-9) 259/260/2613. Design full adder and full subs tractor using PLA. 4. Explain the working of successive approximation A/D converter in detail. 5. Draw a circuit for TTL NOR gate and explain its working, 6. Design 2 bit magnitude comparator. ; — . 5 SECTION-C (2 * 10 = 20 Marks) a circuit for reduced state ON, ¢ = 100. d= tol, 7. Reduce the following state diagram and des diagram using D Flipflop when a = 010, J 8. Solve using K-map-and Q-M methods and implement usi gates only. Pon oy = m(i),|,2,3,9,10,12,16,18,19,29.31) ~ d ¢ 3.14.24). 9. (a) Explain 3 bit Asynchronous counter using wave form and de. MOD-13 Asynchronous Counter. (6) Write a short note on charged coupled device memory. [A-12}AMRITSAR COLLEGE OF ENGINEERING AND TECHNOLOGY, AMRITSAR Roll No. .. (AUTONOMOUS COLLEGE) Total No. of Questions: 09 Total No. of Pages: 02 [Link]. (ECE)-3rd Digital Circuits and Logic Design BTEC-302 Time! 03 Hours Maximum Marks: 60 Instruction to Candidates: » -2) 3) Qu ii) iii) @ Section-A contains ten questions. All questions are compulsory. Section-B contains five questions. Attempt any four questions. Section-C contains three questions. Attempt any two questions. Section - A eS % (10 x2=20) Differentiate betweeit latch and flip flop. ‘Compare performance of DTL and TTL. Why Johnson counter is called as twisted ring counter. Simplify A(B+BC). Convert (675) to its equivalent radix 16 number. Convert 1011011040 gray code ‘What i the Principle of Duality? Convert A'+B'to standard minterms. Find complement of AB(BC+AC) What is don't care condition?” Section -B (4x5=20) Simplify the expression using K-map and implement it by using NAND gate only’ F(AB,CD)= Lm(1,3,5,8,9,11,15)+d2,13)(\ 2g] AMRITSAR COLLEGE OF ENGINEERING AND TECHNOLOGY, AMRITSAR (AUTONOMOUS COLLEGE) = Roll No. Total No. of Questions: 09 [Link]. (ECE)~Sem-3rd DCLD ACEC-16302 Time:.03 Hours Maximum Marks: 60 Instruction to Candidates: 1) Section - A is Compulsory. 2) Attempt any Four questions from Section - B, 3) Attempt any Two questions from Section -C. Section-A (10*2) ay (), IFA=1101 and B= 164, Find A+B (ii) Whet do you mean by 1s compliment. Explain with example. (ii) Compare CMOS with TTL. (iv) Whats glitch? (sy Convert 112.35 decimal to octal (vi) Draw full adder using logi gates. 'vii) What do you mean by Registers?63) a) Q6) ge What do you meari by iniversal gate? Why only NAND and NOR are universal gates? Explain NAND as a universal gate in detail. What is Magnitude Comparator? Explain two bit magnitude comparator in detail, t oy Implement a full subtractor with two half subtractor and an OR gate. What are shift Registers? Explain its types in details. Section -C . x 10=20 What is a Counter? Differentiate between synchronous and asynchronous counter. Design a synchronous MOD-8 counter using JK flip flop. What are Flip Flops? Explain the working of Master Slave JK Flip Flop. 9,12,13,15)using the binary designation Obtain the set of prime implicants for 5! m (1,2,3,5,6, of minterms using Q- M Mettiod. "(viii) I lateh is different from flip flop. : tix) Convert 1001 binary to gray code, hd 9) Draw 4:1 multiplexer using 2:1 multiplexer. Section -B (4*5) 2) what is decoder? Design full subtractor using 3:8 decoder, 23) Design mod-6 up counter using T flip Nop. J#/baplain the working of binary weighted D/A converter with suitable example. | QS) List features of JK flip flop over SR flip Nop and also explain its working, (go! 2) which BCD code is called natural binary code? Why? by show that: AB'C+B+BD'+ABD'+A'C =B+C Section-C (2*10) .7) Find the minimum sum of products expression for the function: Fussy -a)= m(2,4,5,7,8,14) +d(1.10) using k map method. € 98) Solve the following function using type-1 of MUX designing: F(A,B,C,D)= m(0,1,3,4,6,8,12,14,15) Q9) Design a 4-bit twisted ring counter (or) 4 -bit Johnson counter with the help of timing waveformasls(is- AMRITSAR COLLEGE OF ENGINEERING AND TECHNOLOGY, AMRITSAR (AUTONOMOUS COLLEGE) Roll No. : ‘ Total No. of Questions: 09 Total No. of Pages: 02 [Link]. (ECE)-3™ Sem SUBJECT NAME: Digital Circuit and Logic Design BTEC-302 Time: 03 Hours Maximum Marks: 60 Instruction to Candidates: 1) 2) So) vii) viii) ix) x) @) Q3) a Seetion-A contains ten questions. All questions are compulsory. Section-B contains five questions, Attempt any four questions. Section-C contains three questions. Attempt any two questions. Section - A (10 x2=20) What are Decoders? ‘ What are Bit, Byte and Nibble. Explain the importance of Gray code. What is Standard SOP and standard POS form, Realize AND gate using NAND gate only, fy Ob Gb = +5 What is the difference between positive and negative logic State De-Morgans theorems? Define 1’s and 2’s complements. What are weighted and non weighted codes. Wry some gates are said to be universal gates. Section -B (4*5=20) Explain 4-bit priority encoder with truth table and also implement it using basie gates. Convert SR flip flop to JK flip flop Design a combinational circuit that generates an odd parity bit for 4-bit input andE> me implement it using logic gates. Q5) Explain Binary to BCD code Convertor, * Q6) State and prove De-Morgan's theorems Section—C (2x10=2 27) What are couriters? Explain its types with their working with the help of timing diagram Q8) Explain in detail (@) RS Flip flop (6) JK Flip lop Q) Solve the following using Q-M’Method Y=Em(0,1,3,8,9,13,14,15,16,17, 19,25,27,31).-_ os AMRITSAR COLLEGE OF ENGINEERING AND TECHNOLOGY, AMRITSAR (AUTONOMOUS COLLEGE) Roll No. Total No. of Questions: 09 Total No, of Pages: 02 [Link]. (ECE) - 4 Sem Digital Electronic EC-204 ‘Time: 03 Hours Maximum Marks: 60 Instruction to Candidates: 1) Section-A contains ten questions, All questions are compulsory. 2) Section-B contains five questions. Attempt any four questions, 3) Section-C contains three questions. Attempt any two questions. Section- A. (10 x2=20) What is a half-adder? What is full-subtractor? ‘What is a combinational circuit? What is Standard SOP and standard POS form. What are bit, byte and nibble? Explain briefly the term ‘digital’. ‘Add 11101101 + 01111110 ‘What do you mean by term logic in DCLD? Define 1’s and 2’s complements. What is minterm. Section -B (4x5=20) Q2) Explain 4 bit priority encoder with truth table and also implement it using basic gates. Q3) Explain Binary to BCD code Convertor Q4) State and prove De-Morgan's theorems8s Q8) Q9) Explain JK Flip flop in detail Write a short note on Memory organization Section -C @2x10=4 Solve the following using Q-M Method Y=m(0,1,3,8,8,9,13,14,15,16,17,19,25,27,31), Realize NOR as a universal gate. What are counters? Explain decade counter in detail.AMRITSAR COLLEGE OF ENGINEERING AND TECHNOLOGY, AMRITSAR (AUTONOMOUS COLLEGE) Roll No. tit \ | | \ lI ll i | | | Total No. of Questions: 09 Total No. of Pages: 02 [Link], (ECE) - 3rd 1 Circuits and Logie Design BTEC-302 Time: 03 Hours Maximum Marks: 60 Instruction to Candidates: 1) Section-A contains ten questions. All questions are compulsory. 2) Section-B contains five questions. Attempt any four questions. 3) Section-C contains three questions. Attempt any two questions. Section - A (10 x 2 = 20) Qn i) Convert (305.6875)io to its equivalent octal number, ii) Find 2's complement of 1010001 iii) Convert (10110110). to gray code. iv) -Whatis FAN IN? ¥) List two applications of Multiplexer. vi) With the help of diagram explain and showw how many gates are required to build a half adder. vii) Differentiate between synchronous and asynchronous sequential circuits. viii) What do you mean by triggering of Flip Flop. ix) What is Glitch? x) What is magnitude comparator?Q2) Q3) Q4) Q5) Q6) 8) Qs) | i secon Section-B (4+ 5~29) Simplify the expression using K-map and implement it by using NAND gate only: } F(A,B,C,D)= Sm(1,5,7,8,9,10,11,14,15) . | State and prove De-Morgan's theorems. 4 What is Encoder? Design Binary to Decimal Decoder for 4 bits. i Design a circuit that generates an even parity bit for 4 bit input and implemented it using only NAND gate. } What are shift registers? Explain its types in details. Section - C (2* 10= 20 ‘What is a Counter? Differentiate between synchronous and asynchronous counter. Design a synchronous MOD-8 counter using JK flip flop. ‘What are Flip Flops? Explain its types. Draw the logic circuits and excitaion tables for SR and flip flop. Obtain the set of prime implicants for Sm (0,1,3,8,9,13,14,15,16,17,19,25,27,3 using the binar designation of minterms using Q- M MethodAMRITSAR COLLI EGE OF ENGINEERING AND TECHNOLOGY, AMRITSAR (AUTONOMOUS, COLLEGE) Roll No. yotal No. of Questions: 09 No, of Pages: 02 ‘Total No. of Pages: [Link]. (ECE)-Sem 3" DIGITAL CIRCUIT AND LOGIC DESIGN BTEC-302 1: 03 Hou ‘Time: 03 Hours Maximum Marks: 60 Instruction to Candidates: 1) Section - A is Compulsory. 4 Ss 2) Attempt any Four questions from Section - B. 3) Attempt any Two questions from Section -C. Section - A (10 x2=20) gy i) Convert (225.225). into hexadecimal number. iy Subtract the following using 2's complement (1101 1):—(11001)2= Ch iii) What are the advantages of gray codes. ective codes &explain with the help of one example. iv) What are refl gray code. ¥) Write the procedure for the conversion of binary code to Minimize the expression AB+AC+ABC(ABtC). vi) and a demultiplexer with suitable block vil) What is a Decoder? Compare @ decoder diagrams. vii) Differentiate betwe ix) Explain resolution of Analog to digital converter. x) What is DCTL and explain its disadvantages. Section -B en sequential and combination circuits. (4x5=20) 2) Prove that if AtB=A+C and AB= AC then B=C.88e Qn) Q8) Q@) Reduce the following expression by using K-map Y=aM (1, 3, 7, 11, 15) (5, 9, 13) Design a full subtractor using NAND gate. ‘What are the three basic types of TTL? Explain any two in detail. Explain the working of Binary weighted resistance type D/A converter. Seetion - C (10 x2= 29 Obtain the set of prime implicants for m(0,1,3,4,6,7,8,9,14,15) using the binary designation of minters using Q-M method. ~ ‘What is the difference between level and edge triggering? Explain the working of master slave J-K flip flop. Design a Mod-S ripple UP counter using a 3-bit ripple counter.sep ysay Eu Ww, AMRITSAR COLL EGE OF ENGINEERING AND TECHNOLOGY, AMRITSAR (AUTONOMOUS COLLEGE) Total No, of Pages: 02 [Link]. (EEE) -4" Sem DIGITAL ELECTRONICS SUBJECT CODE: BC-204 Time: 03 Hours Maximum Marks: 60 Instruction to Candidates: D) 2) 3) vii) viii) ix) +x) @) Section - A is Compulsory. Attempt any Four questions from Section - B. Attempt any Two questions from Section -C. Seetion- A * (10 x2 = 20) Represent the decimal number 786 in Octal and as a binary number. What is the difference between combinational and sequential circuit? What is buffer register? Which is the fastest ADC and why? What do you mean by RTL? On what factors does the percentage resolution of D/A converter depend? * List four applications of shift register. Prove that full adder is equal to the sum of two half adders. Convert to POS form F( A, B, C,D) = B’C + A’D’ + AC’ How many flip flops are required to design MOD 48 counter. Section - B (4x 5=20) What is the importance and applications of Gray code? Convert the binary number 1001011001111011 to Gray code,Q3) What is a demultiplexer? Explain the difference between DEMUX and MUX. | 24 Draw the circuit of § R flip Nop and explain its truth and excitation table, i Q5) Simplify the function using K-map and implement using minimum number of gates, } F(A, B,C, D)=Em (0, 1, 2, 6,7, 11, 14) + d(3, 10, 15) j 6) Draw the circuit of ECL and explain its operation. Also compare it with TTL Navi gates, > Section -C 10 x Qn ( 24) i) Deseribe the working ofa successive approximation A/D converter with the help of a suitabi diagram and also compare ts performance in terms of speed and accuracy with any other AJD converter. ii) An A/D converter has the following specifications : resolution = 12 bits; relative accuracy = 0.05 percent of full scale; and full scale output = +5 y (@) What is the quantization error in volts? (0) What is the possible error in volts? 28) 1) State and explain the differences arnong ROM, PROM, RAM, SRAM and DRAM, it) Drawa master-slave J-K fip-lop system, Explain its operation and show that race-around | condition is eliminated, ®) i) Design thea synchronous counter to design the Sequence 0, 1, 3, 6,4, 2,0... Also eliminate : the lock out condition. ii) What is the difference between PLA and PAL? Explain PLA in detail,ewupres \e) AMRITSAR COLLEGE OF ENGINEERING AND TECHNOLOGY, AMRITSAR (AUTONOMOUS COLLEGE) Roll No. .. Total No. of Questions: 09 Total No. of Pages: 02 [Link]. (ECE) ~Sem 3" Digital Circuits and Logie Design ~ BTEC-302 Time: 03 Hours Maximum Marks: 60 Instruction to Candidates: 1), Section - A is Compulsory. 2) Attempt any Four questions from Section - B. 3) Attempt any Two questions frum Section -C. Section - A (10 8) Convertthe expression Y= AB +2AC + BC into canonical SOP form. 'b) _- What do you mean by positive and negative logic? 'c) Why Gray code is used in labeling the rows and columns in K-Maps? 4) Convert (2436) into binary and Hexa-decimal. @) State De-Morgan’s theorems, i) What do you mean by RACE condition in flip flops. 18)» Convert Gray code (1100) into Excess-3 code. th) Which counter is fast in operation, parallel or ripple and why? ’) Write down the features of semiconductor memory. ‘i) Name the different classification of ROM’s,@ 3) ow Q6) Qn Q8) Q) Section -B S (4*5=20) Minimize the following expression using K-map Y =m (0, 1,2, 5, 13, 15) Explain the EPROM memory cell with suitable diagram. Explain the 2-bit priority encoder with truth table and also implement it using basic gates. Using 8:1 Mux implement the following function F(A,B,C,D) = Em (2, 4, 5,7, 10, 14) Explain the different Boolean laws and theorems. Section -C : (10 x 2=20) (2) Design BCD to Excess-3 code convertor. (b) Explain how Parallel In Serial Out (PISO) shift register works. (a) Design a Mod-6 up counter. (©) Convert SR flip flop to JK flip flop. Realize the following logic function in SOP form using Quine-Me Cluskey method (A,B,C, D)=2M (2,7,8,9, 10, 12)AMRITSAR COLLEGE OF ENGINEERING AND TECHNOLOGY, AMRITSAR (AUTONOMOUS COLLEGE) Total No. of Questions: 09 ‘otal No. of Pages: 02 [Link]. (ECE) - Sem. - 4" DIGITAL ELECTRONICS SUBJECT CODE : EC - 204 Time: 03 Hours Maximum Marks: 60 Instruction to Candidates: 1) Section - A is Compulsory 2) Attempt any Four questions from Section - B. 3) Attempt any Two questions fom Section - C. Section A, (10 *2=20) Qn i) Find the péssible base for 153/3 = 4. ii) Convert (2ACS.D)jo to decimal, octal and binary. iii) Write Gray code for (18)j0 and (67). iv) Subtract (9)40 from (4)io using Is compliment method, ¥) What is Sequential access memory? vi) State the Demorgan’s theorem. Vii) What is the significance of using universal gates? Realize AND gate using NOR gate. viii) What do you mean by register? Write down the types of shift registers. ix) Differentiate between combinational circuits and sequential circuits? x) Write the truth table for Full subtractor. Section - B (4x5=20) Q2) Explain the different ypes of ROMS? Discuss their advantages and! disadvantages.Q3) Q4) Q5) Q6) Q7) Q8) Q9) Minimize the expression Y = Sm (2. 3,4, 5, 13, 15)-* Ed (8 9% 10. 11) using K - map implement the circuit using NAND gates only. Design a circuit that will generate an odd parity for 4 - bit input and implement it using XNOR gates, Perform the following conversions: a)DtoJ-K Flip Flop b)J-KtoS-R Flip Flop Draw the circuit diagram of open collector of TTL NOT gate and explain its working, WI the disadvantage of using open collector gates configuration, Section -C (10 x2: Design a3 bit Synchronous up / down counter using T Flip Flops. The counter sl count up when up / down control input E = 0 and count down when control input Also draw the state diagram. Explain the operation of a successive approximation type ADC with the help of a block diagram? Also state its advantages, disadvantages and applications. Design a 4 - bit Gray code to Binary code converter(E) grten ECE), rt fo} 8" sent Amritsar College of Enginecring & Technology, Amritsar 2014 (An Autonomous College under UGC Act 1956(2/)) pec 2 es toll No. Sotal No. of Questions: 09 ‘Total No. of Pages: 02 [Link]. (ECE) - 3 Sem SUBJECT NAME: Digital Electronics SUBJECT CODE: EC-204 Time: 3 Hours Maximum Marks: 60 instructions to Candidates: 1) Section- A is Compulsory. | 2) Attempt any Four questions trom Section- B. 3) Attempt any Two questions from Section- C. Section-A ” (10 x 2= 29) Qu) i) What are Sequential Memories? ii) Define 1s and 2°s complement iii) What are ASCII codes? | iv) Realize OR gate using NAND gate only. i ¥) Convert gray code 11011010 to binary code. \ vi) What do you mean by Positive and Negative logic’? - | vii) What are Logic gates? Why are they called so? viii) Define Accuracy and Resolution? ix) Whatis D Flip-flop? : ® ‘ x) Whatare State diagrams? iSection-B (4X S=29) Q2) Draw the circuit of TTL NAND gate & explain its operation, Compare the TT, & ECL logic families. , ‘ Q3) What are A/D converters? Explain Single and Dual slope A/D converter Q4) State and prove De’Morgans Laws. Q5) Implement Half Subtractor using NAND and NOR gate only. Q6) Convert JK flip flop to SR flip flop. Section-C {2X 10=20) Q7) What are counters? Explain its types. Also explain Ring and Johnson counter, Q8) Solve the following function using Q-M method. Also verify it by using K may Y=Em(0,1,6,7,8,9,13,14,15) _ 7 Q9) What are flip flops? Explain Master-slave JK flip- flop.@ Amritsar College of Engineering& Technology, Amritsar (An Autonomous College under UGC Act 1956(2) Roll no... _o Total No of Questions: 09 Total No of Pages: 02 [Link] (ECE)-Sem (3") DIGITAL CIRCUIT AND LOGIC DESIGN BTEC-302 Time: 03 hours Maximum marks: 60 Instructions to candidates ) 2) 3) Section - A is Compulsory Attempt any Four questions from Section - B Attempt any Two questions from Section - C Section - A (10*2=20) With reference to A/D converter, differentiate between resolution and accuracy. ‘What two principle functions are performed by encoder? Explain in brief the ¢Sncept of cache memory? Why do we need io have secondary storage devices when the computer already has a primary storage? What do you mean by quantization error? Determine the resolution of a 12-bit A/D converter having a full-scale analogue input voltage of 5 V. How do you implement three-input and four-input EX-OR logic functions with the help of two-input EX-OR gates? Find the hex equivalent of (762.013)s. Why NAND and NOR gates are universal gates? Find the octal equivalent of (2F.74)is, Section - BQ2) Q3) Q4) Q5) 6) Q7) _ 28) Qs) (sy Compare the performance features of an SRAM and a DRAM. What is py refreshing? Which type of RAM would you expect in battery-operated equipment? How will you implement a Full subtractor from a Full adder? Explain the working of DTL logic family. Design all the gates (NOT, AND, OR, NAND, NOR, XOR, XNOR) using Multiplexer? Minimize the Boolean function F(A,B,C,D) =11(0,4,5,6,7,10,14) using the mapping method using karaugh mapping method. Section - C 10 (a) The data sheet of a certain eight-bit A/D converter lists the following specificatior resolution eight bits; full-scale error 0.02% of full scale; full-scale analogue input V. Determine (a) the quantization error (in volts) and (b) the total possible error (it volts). : (b) Explain in detail the working of single and dual,slope A/D converter. (@) What is a flip-flop? Show the logic implementation of an R-S flip-flop having acti high R and $ inputs. Draw its truth table and mark the invalid entry. ©) Draw the function table for (a) a negative edge-triggered D'flip-flop and (b) a De with an active LOW ENABLE input. : Design MOD ~ 12 synchronoiis counter using D flip flop.Amritsar College of Engineering& Technology, Amritsar (An Autonomous College under UGC Act 1986(20) ‘Total No of Questions: 09 Total No of Pages: 02 [Link] (LCE )-Nem (3%) Ponte care om acts) DIGITAL CIRCUIT AND LOGIC DENG BTEC a ‘Time: 0) howrs Maximum marks: 68 Instructions to candidates 1) Section Ais Compulsory 2) Anempe any Fewr questions from Sextion «ft 3) Anemgt any Tre questions from Sexton ~ C Sexton = 4, on 1 Give tao mays of converting 4 fae input NAND gate to an inverter’? i) Show that UAT = 01 afoern (18S)i9 ~ (Whey ening the exeene:) conde Define pomtive anal negative logic” How can you implement a NOT cite rogut EX-OR gate’? ing 2 ts Discuss the sahent features of ECL logic family” Wi). Draw the truth table of full suberactor 7 viii). Explain the difference between D Latch and D flip flop? ix). Find out whether 16-bit 2°s complement arithmetic can be used to add 14276 and 18490. XD. Convert (2513)ato binary and hexadecimal Section - B@) Q3) Qa) Qs) 26) Q7) Q8) Q9) (4*5=20) Perform the following addition operations: 8) 275.75)9+ 37.875)i0 ) (AFI.B3)ict (FFF.E)ic Implement the product-of-sums Boolean function expressed by I1(1, 2, 5) by a suitable multiplexer. Explain setup time and hold time, what will happen if there is setup time and hold time violation, how to overcome this?. Explain the working of TTL logic family. Eight-line to three-line priority encoder circuit with DO, D1, D2, D3, D4, DS, D6 and D7 as the data input lines, The output bits are A (MSB), B and C (LSB). Higher-order data bits have been assigned a higher priority, with D7 having the highest priority. If the data inputs and outputs are active when LOW, determine the logic status of output bits for the following logic status of data inputs (2) All inputs are in logic ‘0° state. (6) DI to D 4 are in logic ‘1" state and DS to D7 are in logic ‘0° state (€)D7 isin logic ‘0” state. The logic status of the other inputs is not known, Section -C (2*10=20) Design MOD-4 down counter using J-K flip flops. Briefly describe the process of analogue -to- digital conversion in a counter type A/D Converter. How does it differ from the successive approximation A/D converter used for the same purpose? (@) An eight-bitD/A converter has a step size of 20 mV. Determine the full-scale output and percentage resolution. (0) A certain eight-bit D/A converter has a full-scale output of § mA and a full-scale error of £0.25% of full scale. Determine the range of expected analo, gue output for a digital input of 10000010.AMRITSAR COLLEGE OF ENGINEERING AND TECHNOLOGY, AMRITSAR (AUTONOMOUS COLLEGE) Roll No, Total No. of Questions: 09 Total No. of Pages: 02 [Link]. (ECE)- Sem 3" (Balth 26/5 ones) DIGITAL CIRCUIT AND LOGIC DESIGN BTEC-302 Time: 3.00 Hours ‘Maxiraum Marks: 60 Instruction to Candidates: 1) Section - A is Compulsory, 2) Attempt any Four questions from Section -B, 3) Attempt any Two questions from Section -C, Section- A (10 x2=29) a i) Subtract (12),9 from (8)1o using 2s” complement. ii) Compare ECL and TTL | logic families. ili) _ Obtain Excess-3 Code Of (48)10. iv) Whatare the. ‘applications of Gray codes. 9) What is the difference between edge triggering and level triggering vi) Explain difference between synchronous and Asynchronous ‘Sequential Circuit. vii) Convert (101101 10); to Gray code viii) Explain Lock out: ‘condition in detail, xi) Convert Y= m (1,3, 5) into standard SOP and POS form, = *) Explain the term Resolution and Accuracy of A/D. converter,f i ~! @ @) on Q5) Qy an g8 Section-B Explain Shift register and also explain PISO in deat, (x5 =29) Explain Decimal to BCD encoder in detail. Explain R-2R Ladder type in detail. Convert (0101) into analog signal by R-2R, Ladder tyne. Explain DTL in detail. Implement 8:1 MUX by using 2:1 and 4:1 MUX. Section -C (2) Explain Johnson or twisted ring counter. Oneal (©) Minimize the following using K-MAP if i f=xM (0,1,,2,3,6,8,9,10,11,12,13) Design 3- bit synchronous Ring UP/Down counter and explain in Detail. Explain Master Stave flip flop in detail.‘Total No. of Questions : 09] [Total No. of Pages : 02 B. Tech (ECE/Electronics & Computer Engincering/ETE) (Sem. - 3°) DIGITAL CIRCUIT AND LOGIC DESIGN SUBJECT CODE : BTEC - 302 (2011 & 2012 Bateh) Paper ID : [A1131] Time : 03 Hours Maximum Marks : 60 Instruction to Candidates: 1) Section - A is Compulsory consisting of ten questions carrying two marks each. 2) Section - B contains five questions carrying five marks each and students has to attempt any four questions. 3) Section- C contains three questions carrying ten marks each and students has to attempt any two questions. Section - A QI) a) Convert Gray Code 11000 to Excess-3 Code. b) Convert (100.55), into Binary and Hexadecimal numbers. ©) How Overflow contition is detected in2's complement arithmetic? 4) _ustify with example, the Sel Complementing property of Excess-3 Code. ©) Convert (A+B)(B +C) into canonical SOP form. £) Realize three input NOR gate using three input NAND gates only. 2) What do you mean by positive and negative logic? h) Why Look Ahead Carry Adder are faster than Ripple Carry Adders? i) Give the advantages of Totem Pole Output in TTL ICs, |) Why Gray code is used in labeling the rows and columns in K-Map? t R-1911 PIO.a» Section - B Q2) Compare asynchronous and Synchronous Sequential circuits. 93) Design the Logic Circuit of two bit magnitude comparator using NAND gates only. Q4) Draw and explain the ECL circuit for 2 input OR gate. Q5) Design a combinational circuit that converts three bit Gra number. Q6) Realize Full-Subtractor using 1:8 Demultiplexer. Section - C 97) 2) Compare DTL, TTL and ECL IC logic families in terms of Propagation delay, Power dissipation, Noise Margin and Fan-out. b) Describe the Operation of Dual-Sloy suitable diagram. 28) Design mod-8 UP and Down asynchronous Coun using timing waveforms. Describe the limitation: * : Q9) Write short notes on followings : a) Programmable Logic Devices, b) _Non-Weighted Binary Codes, y Code to Binary pe analog to Digital converter using ter and illustrate its operation s of this counter.Roll No. Total No. of Pages : 02 Total No. of Questions : 09 Time : 3 Hrs. [Link]. (ECE/Electronics & Computer Engg./ETE) (Sem.—-3) DIGITAL CIRCUIT AND LOGIC DESIGN Subject Code : BTEC-302 (2011 Batch) Paper ID : [A1121] : Max. Marks : 60 INSTRUCTION TO CANDIDATES : 4 2. 3. SECTION-A is COMPULSORY consisting of TEN questions carrying TWO marks each. SECTION-B contains FIVE questions carrying FIVE marks each and students has to attempt any FOUR questions. SECTION-C sontains THREE questions carrying TEN marks each and students has 9 attempt any TWO questions. SECTION-A. . Answer briefly : a) Convert (10110110), to Gray code and Excess 3 code. b) Prove that if A+B = A+C and AB=AC then B=C. ¢) Give the implementation circuit of 3 to 8 line decoder. = 6 ou 4) Compare sequential circuits and combinational circuits.“ Convert the following logic function into product of maxterms : F(A,B,C,D) = C‘D+ABC’+A’B°D+ABD" e ) How many bits are required for a DAC so that its full scale output is 12.6 V and resolution is 20 mV? Implement the following function using PAL: Y= Sm(2,4), 2 h) List different applications of counters. i) Explain resolution of A/D converters, J) Give the vlassification of Bipolar and Unipolar logic families. [N.2-1774 1ac Sanat SECTION-B 2. Simplify using K maps : 1) Y= E m(,3,5,6) + ¥ d(4) TT) Y= TIM (1,3,7,11,15 ). d(5,9,13) w + Design a 3 bit odd parity generator, s Convert JK Flip flop to SR flip flop. What are three basic types of TTL? Explain any two in detail. a SECTION-C 7. Write short notes on : 1) PLD’s I) ROM. 8. a) Design a 3 bit synchronous up/down Counter using JK flip flops. b) Explain two applications of registers as counters, 9. Ent st different applications of Multiplexer, Im [Link])= ¥ m(0,1,3,5,7) using D) Single 8:1 MUX I) Single 4:1 MUX IID) Single 2:1 MUX plement the logic function: Explain briefly working of binary weighted resistance D/A converter with the help of an example, What are its drawbacks?Total No. of Questions : 09] [Total No. of Pages : 02 [Link]. (ECE/EE/EEE/EIE) (Sem. - 4") DIGITAL ELECTRONICS SUBJECT CODE : EC - 204 Paper ID : [40307] Time : 03 Hours Instruction to Candidates: Maximum Marks : 60 1) Section - A is compulsory consisting of Ten questions carrying Two marks each. 2) _ Section-B contains Five questions carrying Five marks each and students has to attempt any Four questions. 3) Section - C contains Three questions carrying Ten marks each and students has to attempt any Two questions, Section - A Qi) a) Subtract using 9's and 10’s complement 34 - 14. b (213),- (172), = --), and (2AC),, + (IBD), = (— °) Explain Demorgans Laws. qd Subtract using 2’s and I’s complement (32-24). °) 1) Whatis the difference between combinational and sequential circuits, g) What are the advantages of CMOS over TTL. fh) Whatare the applications of Johnson counter. i) Explain terms fan-in, fan-out and Resolution DA Converter. i) What are the application of Multiplexer. R-2070 PTO.2) 93) 24) Q5) 26) Q7) 28) 29) Section - B Solve using K-map and implement using NAND gates only. F(v,w,x,y)= Em (0,1,2, 7,9,12,14,1 5)+d(4,5) Design full subtractor using 4:1 Multiplexer and 8:1 MUX. Design four bit BCD to grey code converter. Explain working of DCTL and DTL in detail. Explain the working of voitage to frequency conversion circuit. Section - C a) Explain the working successive approximation A/D converter. b) Design MOD-S counter using RS flip-flops. Design MOD-6 up-down counter using JK flip-flops. Write short note on: a) Decoder b) NAND gate usiny CMOSRoll No. ] Total No. of Pages : 02 Total No. of Questions : 09 [Link]. (ECE/EE/EEE/EIE) (Sem.—4th) DIGITAL ELECTRONICS Subject Code : EC-204 Paper ID : [A0307] Time : 3 Hrs. Max. Marks : 60 INSTRUCTION TO CANDIDATES : 4, SECTION-A Is COMPULSORY consisting of TEN questions carrying TWO marks each. 2, SECTION-B contains FIVE questions carrying FIVE marks each and students has to attempt any FOUR questions. 3. SECTiON-C contains THREE questions carrying TEN marks each and students has to attempt any TWO questions. SECTION-A 1. Write briefly + al Convert grey code to BNS (110001101). ---)g and (2FC)1¢ + (IED) 16 = ¢ b. Solve (253)g- (145)s = c. Explain Demorgans laws. d. Subtract using 2’s and I’s complement (33-24). -)ig and (ASF)ig e. Solve (245), = £ What is the difference between combinational and sequential circuits? Explain the characteristic table of D Flip-flop. h. What are the applications of Johnson counter? i, Explain the terms Resolution and Accuracy of A/D converter. What is difference between decoder and multiplexer? [N2-1615 J]Cone SECTION-B - Solve using K-map and implement using NAND gates only.\ F(v,wx,y) = Em (0,1,2,3, ,9,11,14,15) + d (4,5,7) ~ Design full adder and full subs tractor using 4:1 Multiplexer. - Design BCD to grey code system. + Explain working of DCTL in detail. Also the term current hogging, - Explain the working of voltage of frequency conversion circuit, SECTION-C ~ Solve using QM method and verify the result with K-map. Also implement using NOR gates only. F(v,W.x,y,z) = Im (0,1,2,4,5,14,15,19,23,25,27,29,31) + (5,7,9,11) * (@) Explain the working of simultaneous A/D converter. (©) Convert RS to JK and RS to D flip-flop. ~ Design MOD-6 up-down Counter using D flip-flop.