Lecture 5:

DC &
Transient
Response
 Outline
‰ Pass Transistors
‰ DC Response
‰ Logic Levels and Noise Margins
‰ Transient Response
‰ RC Delay Models
‰ Delay Estimation

5: DC and Transient Response CMOS VLSI Design 4th Ed. 2

 Pass Transistors
‰ We have assumed source is grounded
‰ What if source > 0?
VDD
– e.g. pass transistor passing VDD
VDD
‰ Vg = VDD
– If Vs > VDD-Vt, Vgs < Vt
– Hence transistor would turn itself off
‰ nMOS pass transistors pull no higher than VDD-Vtn
– Called a degraded “1”
– Approach degraded value slowly (low Ids)
‰ pMOS pass transistors pull no lower than Vtp
‰ Transmission gates are needed to pass both 0 and 1

5: DC and Transient Response CMOS VLSI Design 4th Ed. 3

 Pass Transistor Ckts

5: DC and Transient Response CMOS VLSI Design 4th Ed. 4

 DC Response
‰ DC Response: Vout vs. Vin for a gate
‰ Ex: Inverter
– When Vin = 0 -> Vout = VDD
– When Vin = VDD -> Vout = 0
VDD
– In between, Vout depends on
transistor size and current Idsp
Vin Vout
– By KCL, must settle such that Idsn
Idsn = |Idsp|
– We could solve equations
– But graphical solution gives more insight

5: DC and Transient Response CMOS VLSI Design 4th Ed. 5

 Transistor Operation
‰ Current depends on region of transistor behavior
‰ For what Vin and Vout are nMOS and pMOS in
– Cutoff?
– Linear?
– Saturation?

5: DC and Transient Response CMOS VLSI Design 4th Ed. 6

 nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn
Vin < Vtn Vin > Vtn Vin > Vtn
Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn
Vout < Vin - Vtn Vout > Vin - Vtn

VDD
Vgsn = Vin Idsp
Vin Vout
Vdsn = Vout Idsn

5: DC and Transient Response CMOS VLSI Design 4th Ed. 7

 pMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp
Vin > VDD + Vtp Vin < VDD + Vtp Vin < VDD + Vtp
Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp
Vout > Vin - Vtp Vout < Vin - Vtp

VDD
Vgsp = Vin - VDD Vtp < 0 Idsp
Vin Vout
Vdsp = Vout - VDD Idsn

5: DC and Transient Response CMOS VLSI Design 4th Ed. 8

 I-V Characteristics
‰ Make pMOS is wider than nMOS such that βn = βp

5: DC and Transient Response CMOS VLSI Design 4th Ed. 9

 Current vs. Vout, Vin

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout

5: DC and Transient Response CMOS VLSI Design 4th Ed. 10

 Load Line Analysis
‰ For a given Vin:
– Plot Idsn, Idsp vs. Vout
– Vout must be where |currents| are equal in
Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|
VDD
Vin2 Vin3
Idsp
Vin3 Vin2 Vin Vout
Vin4 Vin1 Idsn

VDD
Vout

5: DC and Transient Response CMOS VLSI Design 4th Ed. 11

 Load Line Analysis
‰ Vin = 0V
0.4V
0.6V
0.8V
.2V
DD DD
DD

Vin0 Vin5
in5

Vin1 Vin4
Idsn
dsn, |Idsp
dsp
|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
in0
VDD
DD
Vout
out

5: DC and Transient Response CMOS VLSI Design 4th Ed. 12

 DC Transfer Curve
‰ Transcribe points onto Vin vs. Vout plot

Vin0 Vin1
VDD Vin2
Vin0 Vin5
A B

Vout
Vin1 Vin4
C

Vin2 Vin3
Vin3
Vin3 Vin2 D Vin4 Vin5
Vin4 Vin1 E
0 Vtn VDD/2 VDD+Vtp
VDD VDD
Vout Vin

5: DC and Transient Response CMOS VLSI Design 4th Ed. 13

 Operating Regions
‰ Revisit transistor operating regions

Region nMOS pMOS

A Cutoff Linear
VDD
B Saturation Linear A B

C Saturation Saturation Vout

C
D Linear Saturation
E Linear Cutoff
D
E
0 Vtn VDD/2 VDD+Vtp
VDD
Vin

5: DC and Transient Response CMOS VLSI Design 4th Ed. 14

 Beta Ratio
‰ If βp / βn ≠ 1, switching point will move from VDD/2
‰ Called skewed gate
‰ Other gates: collapse into equivalent inverter
VDD
βp
= 10
βn
Vout 2
1
0.5
βp
= 0.1
βn

0
VDD
Vin

5: DC and Transient Response CMOS VLSI Design 4th Ed. 15

 Noise Margins
‰ How much noise can a gate input see before it does
not recognize the input?

Output Characteristics Input Characteristics

VDD
Logical High
Output Range VOH Logical High
Input Range
NMH
VIH
Indeterminate
VIL Region
NML
Logical Low
Logical Low VOL Input Range
Output Range
GND

5: DC and Transient Response CMOS VLSI Design 4th Ed. 16

 Logic Levels
‰ To maximize noise margins, select logic levels at
– unity gain point of DC transfer characteristic

Vout

Unity Gain Points

VDD
Slope = -1
VOH

β p/β n > 1

Vin Vout

VOL
Vin
0
Vtn VIL VIH VDD- VDD
|Vtp|

5: DC and Transient Response CMOS VLSI Design 4th Ed. 17

 Transient Response
‰ DC analysis tells us Vout if Vin is constant
‰ Transient analysis tells us Vout(t) if Vin(t) changes
– Requires solving differential equations
‰ Input is usually considered to be a step or ramp
– From 0 to VDD or vice versa

5: DC and Transient Response CMOS VLSI Design 4th Ed. 18

 Inverter Step Response
‰ Ex: find step response of inverter driving load cap
Vin (t ) = u(t − t0 )VDD
Vin(t)
Vout (t < t0 ) = VDD Vout(t)
Cload
dVout (t ) I dsn (t )
=− Idsn(t)
dt Cload
Vin(t)
⎧
⎪ 0 t ≤ t0
⎪
I dsn (t ) = ⎨ β
( − ) Vout > VDD − Vt
2
2 V DD V Vout(t)
⎪ t
⎪ β ⎛⎜ VDD − Vt − out ⎞ V (t ) V < V − V
V (t )
⎟ out t0
⎩ ⎝ 2 ⎠
out DD t

5: DC and Transient Response CMOS VLSI Design 4th Ed. 19