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Decade Counter Design Overview

This document contains code for a decade counter implemented using two different architectures - behavioural and structural. The behavioural architecture uses a process sensitive to the clock and reset signals to increment the counter from 0 to 9 and then reset it to 0. The structural architecture instantiates JK flip flop components in a chain, with the output of each flip flop connected to the clock input of the next. It also instantiates a NAND gate component. A separate JK flip flop entity is defined with a behavioural architecture that describes its truth table functionality of toggling or maintaining its output based on the J and K inputs on the falling edge of the clock, unless reset.

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giridhar chikka
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18 views3 pages

Decade Counter Design Overview

This document contains code for a decade counter implemented using two different architectures - behavioural and structural. The behavioural architecture uses a process sensitive to the clock and reset signals to increment the counter from 0 to 9 and then reset it to 0. The structural architecture instantiates JK flip flop components in a chain, with the output of each flip flop connected to the clock input of the next. It also instantiates a NAND gate component. A separate JK flip flop entity is defined with a behavioural architecture that describes its truth table functionality of toggling or maintaining its output based on the J and K inputs on the falling edge of the clock, unless reset.

Uploaded by

giridhar chikka
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

DECADE COUNTER BEHAVIOURAL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DECADE_COUNTER is
Port (RESET: in STD_LOGIC;
CLK: in STD_LOGIC;
Q: inout STD_LOGIC_VECTOR (3 downto 0):="0000" );
end DECADE_COUNTER;
architecture BEHAVIOURAL of DECADE_COUNTER is
begin
PROCESS (CLK, RESET)
BEGIN
IF RESET='0' THEN
Q<="0000";
ELSIF FALLING_EDGE(CLK) THEN
IF Q="1001" THEN
Q<="0000";
ELSE
Q<=Q+"0001";
END IF;
END IF;
END PROCESS;
END BEHAVIOURAL;
DECADE COUNTER STRUCTURAL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity dec_str is
Port (CLK :IN STD_LOGIC;
RESET : IN STD_LOGIC;
Q : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0) );
end dec_str;

architecture structural of dec_str is


COMPONENT JK IS
Port ( J,K,C,CLR : IN STD_LOGIC;
Z: OUT STD_LOGIC );
END COMPONENT;
COMPONENT NAND1
Port ( D,C : in STD_LOGIC;
Y : out STD_LOGIC);
END COMPONENT;
begin
N : NAND1 PORT MAP (Q(3),Q(1),RESET);
JK1 : JK PORT MAP ('1','1',CLK,RESET,Q(0));
JK2 : JK PORT MAP ('1','1',Q(0),RESET,Q(1));
JK3 : JK PORT MAP ('1','1',Q(1),RESET,Q(2));
JK4 : JK PORT MAP ('1','1',Q(2),RESET,Q(3));
end structural;

COMPONENT INSTANTIATION –

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity JK is
Port ( J,K,C,CLR : IN STD_LOGIC;
Z: OUT STD_LOGIC );
end JK;

architecture Behavioral of JK is
begin
PROCESS (J,K,C,CLR)
VARIABLE A : STD_LOGIC:= '0';
BEGIN
IF CLR ='0' THEN
A:= '0';
ELSE
IF FALLING_EDGE(C) THEN
IF J= '0' AND K= '0' THEN
A := A;
ELSIF J= '0' AND K= '1' THEN
A := '0';
ELSIF J= '1' AND K= '0' THEN
A := '1';
ELSIF J= '1' AND K= '1' THEN
A := NOT A;
END IF;
END IF;
END IF;
Z<= A;
END PROCESS;

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