Tien Pham Van, Dr. rer. nat.
Hanoi University of Science and Technology
Compiled with reference to other presentations
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@[Link] C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Outlines
• Custom interfaces
• GPIO
• Communication
• Human machine
interfaces
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@[Link] C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Hardware: system view
Embedded system is a special-purpose computing device designed to perform dedicated function
EMBEDDED
INPUT OUTPUT
SYSTEM
- Keyboard Button - LCD Display
- Steering wheel position - Servo Engine
SOFTWARE
- Microphone APPLICATION SOFTWARE
- EEG signals
SYSTEM SOFTWARE
MIDDLEWARE
DEVICE DRIVERS
Analog Environment
Digital Environment HARDWARE
EMBEDDED BOARD
OUTPUT DEVICES
MCU
INPUT DEVICES
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@[Link] C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Embedded development trend
• Interconnection
– IoT/M2M
– Diversified communication physical means
• Distribution/decentralization
– More modules to co-work
– Higher parallelism
• Human machine interface
– Behavior recognition
– More intelligent
• Customizability
– Configurable hardware
– Universal ports
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@[Link] C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@[Link] C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Devices have different data Rates
different I/O techniques used
+ sensors, actuators, SSD, router
Embedded
2/16 Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@[Link] C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Interface Performance Measures
• Latency
delay between service request and service
completion
» includes both software and hardware delays
for real-time systems
» guarantee must be made for worst-case latency
• Bandwidth (or throughput)
maximum rate at which data can be processed
• Priority
determines service order when more than one
request is pending
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@[Link] C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Synchronizing SW w/ I/O Devices
• Problem: I/O devices operate in parallel w/ controller
pro: parallelism enhances performance
con: it’s hard for humans to get it right
• Hardware common case
3 states: idle, busy, or done
when not idle
» busy and done alternate
• I/O or CPU bound (unbuffered vs. buffered interfaces)
I/O bound is typical
» I/O devices often much slower than controller SW loop
• synchronization is required
• unbuffered interface works but SW has to do significantbabysitting
CPU bound
» still need synchronization for accurate information transfer
» buffering required to store I/O transactions
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@[Link] C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Synchronization Mechanisms
• Blind cycle
SW waits a fixed amount of time for the I/O to complete
» then samples input or produces another output
• Busy waiting
check I/O status flag once per iteration (previous example)
» waits for flag to indicate I/O done state
• Interrupt
I/O requests SW to become active
• Periodic polling
timer based interrupt requests software activity
» 6812 TCNT timer both more accurate and energy efficient than a cycle
counting software timer
• Direct Memory Access (DMA)
I/O device transfers data to/from controller memory
» memory used as a mailbox to facilitate communication
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@[Link] C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Scalable Embedded I/O Bus Architectures
- Device I/O interfaces and Drivers for
Real-time Systems | Coursera
[Link]
critical-systems-design/scalable-embedded-i-o-bus-
architectures-sGxqA
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@[Link] C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
I/O Basics
• I/O controller I/O devices ports
– Transfers data to/from device
– Synchronizes operations with software
• Command / control registers
• Status registers: device status, errors
• Data registers
– Write: data device eg Transmit
– Read: CPU device eg receive
– multiple I/O registers can map to same address
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@[Link] C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Device Drivers
• Device-specific – controls IO device, written by
manufacturer eg SSD driver, mouse,
– command registers, commands vary from device to device
• Part of kernel
– Compiled with OS, Dynamically loaded into OS
• Accept abstract R/W requests from device-independent layer ;
• Initialize device, Manage power, and log
• Check & translate input parameters
– e.g., convert linear block number into the head, track, sector and cylinder
number for disk access
• Check device status & Control sequence of commands
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@[Link] C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
CPU Bus I/O
• CPU needs to talk to I/O Address
Data
• Memory-mapped I/O CPU
Read
– Devices mapped to Write
reserved memory locations -
like RAM Memory I/O Device
– Uses load/store instructions
just like accesses to memory
Address
Data
• I/O mapped I/O CPU Memory I/O
– Special bus line Read
Write
– Special instructions
I/O Port
Memory
I/O Device
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@[Link] C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Memory Mapped I/O
Physical Layout Programmer’s View
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@[Link] C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
I/O Register operations
I/O Registers are NOT like normal memory
Device events can change their values (e.g., status registers)
Reading a register can change its value (e.g., error condition
reset)
For example, can't expect to get same value if read twice
Some are readonly (e.g., receive registers)
Some are writeonly (e.g., transmit registers)
Sometimes multiple I/O registers are mapped to same address
Selection of one based on other info (e.g., read vs. write or extra control
bits)
Cache must be disabled for memory-mapped addresses – why?
When polling I/O registers, should tell compiler that value can
change on its own and therefore should not be stored in a register
volatile int *ptr; (or int volatile *ptr;)
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@[Link] C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Parallel vs. Serial Digital Interfaces
Parallel $$$$
– Multiple parallel data lines
– Hi Speed
– Ex: PCI, ATA, CF cards
Serial convenient
– minimal data lines
– Low Power, length
– Ex: USB, SATA, SD (secure digital),
I2C, SPI, CAN, PCI-Express
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@[Link] C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Serial vs. Parallel
TX
Serial MCU 1 RX MCU 2
signal
Data[0:7]
Parallel MCU 1 MCU 2
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@[Link] C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Why Serial Communication?
Serial communication is a pin-efficient way of sending and
receiving bits of data
Sends and receives data one bit at a time over one wire
While it takes eight times as long to transfer each byte of data this way
(as compared to parallel communication), only a few wires are required
Typically one to send, one to receive (for full-duplex), and a common
signal ground wire
Simplistic way to visualize serial port
Two 8-bit shift registers connected together
Output of one shift register (transmitter) connected to the input of the
other shift register (receiver)
Common clock so that as a bit exits the transmitting shift register, the bit
enters the receiving shift register
Data rate depends on clock frequency
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@[Link] C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Simple Serial Port
Receive
Buffer Register
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
Receive
Shift Register
Transmit
Shift Register 0 1 2 3 4 5 6 7
Transmit 0 1 2 3 4 5 6 7
Hold Register
Processor Peripheral
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@[Link] C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Protecting Against Data Loss
How can data be lost?
If the transmitter starts to send the next byte before the
receiver has had a chance to process/read the current byte
If the next byte is loaded at the transmitter end before the
current byte has been completely transmitted
Most serial ports use FIFO buffers so that data
is not lost
Buffering of received bytes at receiver end for later processing
Buffering of loaded bytes at transmitter end for later
transmission
Shift registers free to transmit and receive data without worrying
about data loss
Why does the size of the FIFO buffers matter?
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@[Link] C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Serial Port
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
FIFO Buffer FIFO Buffer
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
Clock Clock
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
FIFO Buffer FIFO Buffer
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
Processor Peripheral
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@[Link] C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
What is RS-232?
So far, we’ve talked about clocks being synchronized and using the
clock as a reference for data transmission
Fine for short distances (e.g., within chips on the same board)
When data is transmitted over longer distances (off-chip), voltage
levels can be affected by cable capacitance
A logic “1” “1”might appear as an indeterminate voltage at the receiver
Wrong data might be accepted when clock edges become skewed
Enter RS232: Recommended Standard number 232
Serial ports for longer distances, typically, between PC and peripheral
Data transmitted asynchronously, i.e., no reference clock
Data provides its own reference clock
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@[Link] C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Types of Serial Communications
Synchronous communication
Data transmitted as a steady stream at regular intervals
All transmitted bits are synchronized to a common clock signal
The two devices initially synchronize themselves to each other, and
then continually send characters to stay synchronized
Faster data transfer rates than asynchronous methods, because it does
not require additional bits to mark the beginning and end of each data
byte
Asynchronous communication
Data transmitted intermittently at irregular intervals
Each device uses its own internal clock resulting in bytes that are
transferred at arbitrary times
Instead of using time as a way to synchronize the bits, the data format is
used
Data transmission is synchronized using the start bit of the word, while
one or more stop bits indicate the end of the word
Asynchronous communications slightly slower than synchronous
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@[Link] C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Sync vs. Async
Synchronous communications
Requires common clock (SPI)
Whoever controls the clock controls communication speed
Asynchronous communications
Has no clock (UART)
Speed must be agreed upon beforehand (the baud-rate configuration
accomplishes that)
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@[Link] C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
RS232 – Bits and Serial Bytes
Serial ports on IBM-style PCs support asynchronous communication only
A “serial byte” usually consists of
Characters: 5-8 data bits
Framing bits: 1 start bit, 1 parity bit (optional), 1-2 stop bits
When serial data is stored on your computer, framing bits are removed, and this
looks like a real 8-bit byte
Specified as number of data bits - parity type - number of stop bits
8-N-1 a eight data bits, no parity bit, and one stop bit
7-E-2 a seven data bits, even parity, and two stop bits
MSB LSB
0 1 2 3 4 5 6 7
7 6 5 4 3 2 1 0
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@[Link] C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
RS-232 Signal Levels
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@[Link] C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Serial Port Connector
9-pin (DB-9) or 25-pin (DB-25) connector
Inside a 9-pin connector
Carrier Detect - Determines if the DCE is connected to a working
phone line
Receive Data - Computer receives information sent from the DCE
Transmit Data - Computer sends information to the DCE
Data Terminal Ready - Computer tells the DCE that it is ready to talk
Signal Ground - Pin is grounded
Data Set Ready - DCE tells the computer that it is ready to talk
Request To Send - Computer asks the DCE if it can send information
Clear To Send - DCE tells the computer that it can send information
Ring Indicator – Asserted when a connected modem has detected an
incoming call
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@[Link] C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Embedded Real-Time Systems
RS-232 Pin Connections
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@[Link] C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Handshaking
Some RS232 connections using handshaking lines between DCE
and DTE
RTS (ReadyToSend)
• Sent by the DTE to signal the DCE it is Ready To Send
CTS (ClearToSend)
• Sent by the DCE to signal the DTE that it is Ready to Receive
DTR (DataTerminalReady)
• Sent to DTE to inform the DCE that it is ready to connect
DSR (DataSetRead)
• Sent to DCE to inform the DTE that it is ready to connect
Handshaking lines can make it difficult to set up the serial
communications, but seamless after set-up.
Also, software handshaking (XON/XOFF)
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@[Link] C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Interfacing Serial Data to Microprocessor
Processor has parallel buses for data need to convert serial data to
parallel (and vice versa)
Standard way is with UART
UART Universal asynchronous receiver and transmitter
Chip Reg
Select
Tx Clock
R/W
Control
Tx Data Reg Tx Shift Reg Tx Data
IRQ
Status Reg
CTS
D0-D7 Data Control Reg
Bus RTS
Buffers Rx Data Reg Rx Shift Reg Rx Data
Rx Clock
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@[Link] C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596