University of Thi -Qar Journal for Engineering Sciences ISSN :2664- 5572 ( online)

[Link] ISSN:2664-5564 (print)

Vol 12.2( December 2022) Available at [Link]
utjeng@ [Link]
Seven-Level Inverter Topology with Fewer Switching Components
Hussein S. Abdulazeez†, Rabee’ H. Thejel ‡, and Diyah K. Shary ϯ
†
Basrah Engineering Technical College, Southern Technical University, Iraq, [Link]@[Link]
‡
Basrah Engineering Technical College, Southern Technical University, Iraq, rabee_alabbasi@[Link]
ϯ
Basrah Engineering Technical College, Southern Technical University, Iraq, diyahpower@[Link]

Abstract
This work proposed a 7-level Inverter structure with minimum power components and controlling with pulse width
modulation (PWM) techniques. This topology has three times the greater capacity for voltage boosting. The aim of this
study is achieved using a single voltage source, eight switches, two diodes, and two capacitors. Three times voltage
boosting, a small number of switches, reduced voltage stress, and a self-balanced capacitor is the main characteristics of
this topology. The selective harmonic elimination pulse width modulation SHE-PWM technique, which is based on
genetic algorithm optimization, is also used to isolate or eliminate undesirable low-order harmonics of the output voltage.
To demonstrate the aforementioned benefits, a simulation was performed using MATLAB SIMULINK, and the
corresponding THD results were compared with various modulation indices.

Keywords: - Multilevel inverter, switched capacitors, PWM technique, Voltage boosting ability.

1. Introduction additional boosting circuits [6]. Furthermore, by

In recent years, multilevel inverters (MLIs) as a eliminating the requirement for an additional boosting
feasible solution for high-efficiency electric power- circuit, The circuit is simpler as a result of the fundamental
electronic conversion systems. idea of connecting SCs in parallel or series with the input
The primary reasons for using MLIs in a wide range of voltage source [7]-[8].
applications, including motor drives and the use of Solar To construct a structure with as few components as
and wind energy sources, to name a few, are their intrinsic possible, a variety of MLIs for more voltage levels have
characteristics, such as reduced voltage stress on power been described in the literature due to the advantages of the
electronic semiconductor switches, for switching in low SC technique. Ten switches and four dc sources are used in
frequency, the efficient output waveform, minimum filter a thirteen-level (13-L) inverter [9]. It is created in ML's
requirement, etc.[1]. The basic multilevel inverters MLIs kite structure in [10]. . another kite-type with switched
are listed as 1-Diode-Clamped (DC-MLI) 2-Flying- capacitance-voltage (K-Type SC-MLIs) which needed
capacitors (FC-MLI) 3-Cascaded H-bridge(CHB-MLI)[2] fourteen semiconductor switches, four capacitors, and a
Additionally, CHB-MLI needs many isolated dc sources, single dc source is presented in [11 According to the
whereas NPC-MLI and FLC-MLI still struggle with the literature review, it is evident that attempting to increase
balance of capacitor voltages. Although there are the output level causes the circuit to become more
numerous variations of these fundamental MLIs, such as complex. Implementation is more expensive.
symmetric cascade H-bridge (S-CHB), asymmetric Consequently, numerous investigations were conducted in
Cascade H-Bridge (A-CHB), hybrid Neutral point the literature that has a big impact on reducing the
clamped(NPC) with Cascade H-bridge CHB, etc., The consumption of various elements including voltage
overall structure increases the complexity of control by sources, power semiconductors, and switched capacitors.
involving a large number of components [3]. The electrical This study described a seven-level SC-based inverter with
energy produced by renewable energy sources, such as a three-voltage boosting gain. The following are a few of
photovoltaic (PV) arrays and fuel cells, is mostly low dc this topology's advantages:
voltage and must be converted to higher ac voltage. One of 1. To produce seven levels of synthesized output voltage,
the common approaches is to pair a front-end conventional only eight power switches and two diodes are needed (Vo).
MLI with a back-end dc-dc boost converter [4]. As an 2. It only needs two balanced switched capacitors, and no
alternative, switched-capacitor multilevel inverters (SC- additional circuits, sensors, or complicated control
MLIs) have been thoroughly researched as a new approach techniques.
strategy to dealing with the issues listed above. Here, a 3. inherent ability to change the polarity.
switched-capacitor-based multilevel boost inverter was 4. In the proposed technology, there are eight switches in
introduced in [5] while having no inductive-load ability, it total, but only four of them are active at any given voltage
helps to build seven levels with fewer components than level, which significantly lowers power switching losses.
standard topologies. Although the main aim of SC-MLIs is
buck-type devices, some systems that use solar Section 2 provides a detailed description of the circuit,
photovoltaics, fuel cells, or electric car batteries need operating modes for the proposed seven-level inverter, and

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Hussein S. Abdulazeez et al Seven-Level Inverter Topology

the developed pulse width modulation (PWM) scheme. In fully charge each capacitor (C1 and C2 )to its maximum
section 3, it was discussed how to optimize SHE-PWM source voltage(Vdc) rating. the capacitors C1 and C2 are
using a genetic algorithm to implement it in the suggested parallel connected to the source voltage in the voltage
topology. A thorough comparison with the current tripler section to C1 and C2 in charging operation. while
topology is presented in section 4 using various metrics. capacitors discharged by connecting in series with the
The findings are discussed in section 5. The conclusion is source Vdc, These two capacitors simultaneously
included in section 6. discharged to the source and the load. in three voltage
levels, self-voltage balancing of capacitors is ensured by
2- Proposed 7-level inverter connecting them in parallel for charging and in series to
discharge. Capacitors C1 and C2 are connected in parallel
2.1 Circuit Description: with the Vdc during the voltage levels ±1Vdc, therefore, as
The seven-level multilevel structure with a switched a result, charged at level ±1Vdc. Depending on the
capacitor is shown in Fig. 1. It includes a single DC selected switch state, either C1 or C2 discharges at voltage
source, eight switches, two diodes (D1, D2), and two levels below ±2Vdc while the other charges are, two
capacitors (C1, C2). There are four complementary capacitors in series with input source discharges, The
switches (S1, S2, S3, and S4). Van represents the inverter's operating modes are:
output as determined by the source voltage (Vdc).

1-Vab=0V: During this state as shown in Fig 2 d, through

the power semiconductor devices (S1’, S2 and S3’, S4’) in
the ON state position. the capacitors are not charged (idle),
the canceling voltage across the load by (S3’, S4’). As a
result, the load receives zero voltage.

2-Vab=Vdc: The state explains the capacitors C1 and C2

are simultaneously charged by the source voltage to
produce load voltage(Vdc), with the power switches
devices (S1, S2', S3, and S4') in the ON state. In a similar
manner, switches (S1, S2', S3', and S4) are activated in a
negative operation mode. The useful mode of operation is
proved in Fig .2 a.
Fig.1 Proposed 7- level MLI structure
3-Vab=2Vdc: During this state, the load voltage 2Vdc is
The topology here comprises two parts, The first part is a obtained by switching ON the switches under Table I in
tripler part consisting of (S1, S2, S1’, S2’, C1, C2, D1, D2, states 2 and 3.
and source voltage Vdc) of and is responsible for
boosting the voltage to three times the input voltage, as 4-Vab=3Vdc: During this state 4, the input voltage to
shown on the left of Fig.1. The second is a polarity part is supply is coupled in series with the voltage storing devices
working together with the first part and contains four capacitors C1 and C2, and the load voltage when (S2, S1’,
switches (S3, S3’, S4, and S'4, and load) to reverse the S3, and S4’ )are ON so, the total gain of state 4 is 3Vdc
polarity of the part (H-bridge).as shown on the right of alternated.
Fig.1. If C1 and C2 are large enough just to keep a constant
dc voltage without considering the forward voltage drop
and on-state resistance of the switching devices and Table 1 Switching states of a proposed 7-level inverter.
without the need for any closed-loop control, three
different dc-bus voltages (Vdc-bus) can be produced. In Stat Tripler Polarity Capacitors Van
other words, the series/parallel connection technique es circuit circuit
ensures the self-voltage balancing of SCs. Each component 1 1 0 1 0 charge Charge +Vdc
has experienced low voltage stress (Vdc). The proposed 2 1 1 1 0 Discharge charge +2Vdc
inverter is less complicated and more affordable because of 3 0 0 1 0 charge Discharge +2Vdc
this feature. 4 0 1 1 0 Discharge Discharge +3Vdc
5 0 1 0 0 Idle Idle 0
2.2 The Principle of Operation and SC Voltage 6 1 0 0 1 charge charge -Vdc
Balancing:
7 0 0 0 1 Discharge charge -2Vdc
8 1 1 0 1 charge Discharge -2Vdc
The current flow path for a resistive load is shown in Fig. 2
following the switching states in Table I. The nine 9 0 1 0 1 Discharge Discharge -3Vdc
operating states in the suggested topology have been
completed by
each cycle of operations. The switching table indicates the
entry "1" for the ON state and "0" for the OFF state. to

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Hussein S. Abdulazeez et al Seven-Level Inverter Topology

2.3 PWM Strategy

(a)

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Hussein S. Abdulazeez et al Seven-Level Inverter Topology

(b)
Fig .3. Logic for PWM Signal Generation (a) Logic circuit ,(b) PWM
Signals.
In multilevel inverters, the pulse width modulation 2.4 Capacitor analysis
(PWM) technique is used to control the switches ON and
OFF states. To achieve this, improve the quality of the The states of operation listed in Table I was successfully
output voltage waveform and balance of capacitors voltage arranged in one cycle of output voltage, taking into
by reducing voltages ripples in it. the signal produced is in account
Fig.3 b by simple level shifted pulse modulation the staircase output voltage depicted in Figure 4, to balance
(PWM).three high-frequency triangular waveforms the two capacitors. wherein α1, α2, and α3 are conducting
(Vcarr1, Vcarr2, and Vcarr3) are compared with a angles. C1 is used for double the voltage of 2Vdc in the
rectified sinusoidal reference (Vref).In the PWM range of α2 to α3 during the positive half cycle. C2 is used
technique, carrier signals ( Vcarr1, Vcarr2, and Vcarr3) for the voltage of 2Vdc from π- α3 to π- α2. And from α3
are shifted and in a similar phase. It is also working for to π- α3 both C1 and C2 provide 3Vdc. For the negative
higher and lower switching frequencies. the result of the half cycle, a similar arrangement is also made. As a result,
comparator between reference signals and carrier signals is [14] is used to express voltage ripples across the two
subjected to a suitable logic circuit[3]. which generates the capacitors:
level information for the output voltage to be produced as
𝟏 𝝅−𝜶𝟑
shown in Fig. 3. (a). For such an arrangement, the 𝐕𝐜𝟏 = ∫ 𝒊𝒐𝟏 𝒅(𝒘𝒕)
modulation index is given as: 𝟐𝝅𝒇 𝑪𝟏 𝜶𝟐

𝟏 𝝅−𝜶𝟑
𝑴𝒂 =
𝑽𝒓𝒆𝒇
(1) 𝐕𝐜𝟏 = ∫ 𝒊𝒄𝟏 𝒅(𝒘𝒕) (2)
𝟐𝝅𝒇 𝑪𝟏 𝜶𝟐
𝟑 𝑽𝒄𝒂𝒓𝒓
𝝅−𝜶𝟐
where V-ref is the reference signal amplitude, and V-carr is the 𝟏
𝐕𝐜𝟐 = ∫ 𝒊𝒐𝟐 𝒅(𝒘𝒕)
the triangular carrier signal amplitude. Only the switching state 𝟐𝝅𝒇 𝑪𝟐 𝜶𝟑
combination of switching states 2 and 8 with 3 and 7 will result in
𝝅−𝜶𝟐
an equal power-sharing between the capacitors C1 and C2 because 𝟏
𝐕𝐜𝟐 = ∫ 𝒊𝒄𝟐 𝒅(𝒘𝒕) (𝟑)
of the symmetrical charging and discharging. Thus, there will be 𝟐𝝅𝒇 𝑪𝟏 𝜶𝟑
no difference in the voltage ripple between them. The level
indicator signals and Table I are used to create the gating signals.
For example, if the selected combination of states is 2 and 8 with 1
Where io is the output current of the inverter and f is the
and 6, Switch S2 must be turned ON for states 2 and 4 during the frequency of the output voltage.
positive half cycle and 8 and 9 during the negative half cycle. The
The output current (io=Vo/R), io is inversely proportional
level outputs for these states are tapped, and the gating pulse signal
to the Vo, when the load is used as a purely resistive R.
The ripples of voltage can be described as:
is generated after the proper logic has been used. Similar progress
is repeated to derive gating pulse signals for the switches'
remaining modes.

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Hussein S. Abdulazeez et al Seven-Level Inverter Topology

𝟒𝑽
Vn= [𝐜𝐨𝐬(𝛂𝟏) − 𝐜𝐨𝐬(𝛂𝟐) − 𝐜𝐨𝐬(𝛂𝟑)]
𝒏𝝅
(10)

In the output voltage waveform, the 3rd harmonic (n=3),

7th harmonic (n=7), etc were eliminated[18].

𝟒𝐕
V1= [𝐜𝐨𝐬(𝛂𝟏) − 𝐜𝐨𝐬(𝛂𝟐) + 𝐜𝐨𝐬(𝛂𝟑)]
𝛑

𝟒𝐕
V3= [𝐜𝐨𝐬(𝟑𝛂𝟏) − 𝐜𝐨𝐬(𝟑𝛂𝟐) + 𝐜𝐨𝐬(𝟑𝛂𝟑)]
𝟑𝛑

𝟒𝐕
V5= [𝐜𝐨𝐬(𝟓𝛂𝟏) − 𝐜𝐨𝐬(𝟓𝛂𝟐) + 𝐜𝐨𝐬(𝟓𝛂𝟑)]
Fig .4. Operation describes how the 7-level inverter is 𝟓𝛑
configured for stair output. 𝟒𝐕
V7= [𝐜𝐨𝐬(𝟕𝛂𝟏) − 𝐜𝐨𝐬(𝟕𝛂𝟐) + 𝐜𝐨𝐬(𝟕𝛂𝟑)]
𝟕𝛑
(𝟑𝝅−𝟒𝜶𝟑−𝟐𝜶𝟐)𝑽𝒅𝒄
𝐕𝐂𝟏= (4) (11)
𝟐𝝅𝒇𝑪𝟏
(𝟑𝝅−𝟒𝜶𝟑−𝟐𝜶𝟐)𝑽𝒅𝒄
𝐕𝐂𝟐= (5) 𝟒𝐕
𝟐𝝅𝒇𝑪𝟐 V9= [𝐜𝐨𝐬(𝟗𝛂𝟏) − 𝐜𝐨𝐬(𝟗𝛂𝟐) + 𝐜𝐨𝐬(𝟗𝛂𝟑)]
𝟗𝛑

It indicates that there is no difference in the voltage 𝟒𝐕

ripple between the two capacitors. Both capacitors operate V11= [𝐜𝐨𝐬(𝟏𝟏𝛂𝟏) − 𝐜𝐨𝐬(𝟏𝟏𝛂𝟐) + 𝐜𝐨𝐬(𝟏𝟏𝛂𝟑)]
𝟏𝟏𝛑
twice, once in the positive half cycle and the negative half To reduce the (3rd,5th,7th,9th, and 11th )harmonics in the
cycle alternately. the capacitor voltage ripple can be output waveform, It has been set so that the corresponding
controlled by a suitable switching method. voltage is zero. Utilizing the selective harmonic
elimination technique, with the smallest number of
3-Selective Harmonic Elimination technique switching and selecting the optimum firing angles, only
particular harmonics are eliminated. This method is ideal
To eliminate the odd harmonics and control the for controlling inverters. This method makes it possible to
fundamental voltage, the selective harmonic eliminated obtain a low THD output waveform without the use of a
pulse width modulations (SHE-PWM) method is used to filter circuit. Another method reduces THD by optimizing
find the optimum switching angles, specifically the switching angle using a genetic algorithm.
(α1,α2,…..,αn). The Fourier series can be used to express
the output voltage (Vo) waveform mathematically[17]:
𝐕𝐨 = 𝐚𝐨 + ∑𝒏𝒊=𝟎 𝐚𝐧 𝐜𝐨𝐬[
𝟐𝝅𝒏𝒇
]+bn𝐬𝐢𝐧[
𝟐𝝅𝒏𝒇
] (6) 3.1 Genetic Algorithm(GA)
𝑻 𝑻
For the symmetric staircase waveform with a quarter- The goal is to determine the optimal switching angles that
wave, see [Link] amplitude of the dc component equals result in an output voltage with the required fundamental
zero (a0=0), and The amplitude of all even harmonics component and the fewest of THD that is logically
equals zero (bn=0). the fundamental component's, n=1, possible. . An optimization algorithm should be used to
and odd harmonic component's amplitudes are given by: resolve this issue. a genetic algorithm is used in this work.
𝟒𝑽𝒅𝒄
V1= [( ) ∑𝑲=𝟏 𝐜𝐨𝐬(𝜶𝒌)] (7) which is a simple, powerful, and evolutionary method
𝝅
𝟒𝑽𝒅𝒄 inspired by the concepts of genetics and natural selection.
V𝒏 = [( ) ∑𝑲=𝟏 𝐜𝐨𝐬(𝒏𝜶𝒌)] (8)
𝒏𝝅 It is a general-purpose stochastic global search algorithm
Where αk is the switching angles,n is odd harmonics, that looks for solutions without considering functional
and the staircase waveform's switching angles will be derivative data. which reduces (or expands) a given
adjustable to obtain the output voltage THD with the objective function. While addressing complex objective
lowest possible. The total harmonic distortion (THD) is functions, GA reduces computation and search time
represented as follows: requirements [19]. The SHE-PWM technique's genetic
∑ 𝑽𝒏^𝟐 algorithm is still an innovation. . To minimize the function
THD=√ (9)
𝑽𝟏^𝟐 f (x1,x2,……,xk )using GA. The first step is to encode each
Five categories of finding three firings are included in the Xi as a length binary or floating-point string. A binary
suggested topology to find the lower-order harmonics in string, such as in the following:
the waveform angles of the output voltage waveform. The
topology of a seven-level inverter,( 3rd,5th,7th,9th,11th) X1=[10011 ……….11010]
odd harmonic is selected from the output voltage X2=[00111 ……….11001]
waveform for harmonic elimination. the firing angle (α1,
α2, α3) that was calculated using the constraint relationship
[0<α1<α2<α3<π/2] is calculated using equation (10): Xk=[11010 ……...…01101]
Where collective {x1,x2,…..,xk} is called a chromosome,
and xi is the genes.
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 Hussein S. Abdulazeez et al Seven-Level Inverter Topology

3.2 Defining The Issue complementary switch. Complementary switches,( S1, S1’
Any application uses the same GA methodology. A GA )and (S2, S2’):
only requires a small number of parameters to be set for it
to function. The following are the procedures for Vs1 = Vs1’ =Vs1 =Vs1’= Vdc (14)
formulating a problem and using the GA: Complementary switches, S3, S3’ and S4, S4’
1- Choose between floating-point or binary strings.
2- Identify the variables that are important to the subject; Vs3 = Vs3’ =Vs4 =Vs4’= 3Vdc (15)
this amount will stand in for the number of genes on a TSV=∑𝟖𝒚=𝟏 𝑽𝒔𝒚 (16)
chromosome. The number of variables and the number of Therefore, substitute (14)– (15) in (16) yields:
programmable switching angles is the same in this TSV=16 Vdc
application. For a seven-level inverter, each chromosome The TSV of MLIs is 16Vdc and the TSV p.u. is computed
will have three switching angles, or. (α1, α2, α3). by[21],
3- Define the population size and start it out. The higher 𝐓𝐒𝐕 𝟏𝟔 𝑽𝒅𝒄
TSV p.u= = =5.333 p.u (17)
population may speed up convergence but at the expense 𝐕𝐨,𝐩𝐞𝐚𝐤 𝟑𝑽𝒅𝒄
of longer execution times. When initializing the population Where Vo,peak is the maximum output voltage.
with random angles between 0 and 90, consideration is
𝑽𝒐.𝒑𝒆𝒂𝒌 𝟑
given to the output voltage waveform's quarter-wave The Voltage gain = = =3 (18)
𝑽𝒅𝒄 𝟏
symmetry.
4- The cost function is the most crucial component in the The work [16] uses the fewest switches overall but the
GA evaluation of each chromosome's fitness. This study most diodes compared to the works [13] and [14], which
aims to reduce the output voltage's total harmonic both use the most switches but no diodes. However, the
distortion. In light of this, the cost function Fv is written total switch voltage (TSV) is essentially constant across all
as: inverters. The works [12], [13], [15], and [16] all use three
capacitors, whereas [14] and the proposed one only need
∑ (𝑽𝐧)² two.
Fv (α1, α2, α3)=√ 𝒏=𝟑,𝟓,𝟕…. (12) The three capacitors in [12] and [16] to divide the input
𝑽𝟏²
5-The GA is typically set up to run for a predetermined voltage and maintain the balance of the voltage, are often
number of iterations in order to find a solution (20 in this connected in series. Therefore, to ensure capacitor voltage
case). FVs are used to identify new offspring after the initial equalization, modulation techniques or additional
iteration. These undergo crossover and mutation processes, balancing circuits are needed. In contrast, capacitors’
and a new population is produced that follows the same cycle voltage in [13], [14], can be connected in parallel multiple
beginning with FV assessment. Sometimes, well before the times during one cycle of output voltage with the input
20 iterations are finished, the GA can converge to a solution. voltage source Vin, and the suggested one can be
The answer must also meet the following fundamental automatically balanced as a result. Additionally, as two H-
constraint[20]: bridges are formed by the eight power switches used in this
[0<α1<α2<α3<π/2] (13) proposed work, The proposed inverter benefits from a
4-Comparison with Other Recent SCMLI Topologies: simpler design, step-up capability, and self-balancing
Parameters comparison with existing seven-level inverters is capacitors voltages overall.
made in Table II. wherein E represents one level of the output
voltage,(Nswitches(NSW),Nsource(NSO),Ndiode(ND),Ncapaci 5-Results and Discussion
tance(NC), and N-level(NL)) represented the number of power
semiconductor switches, DC source, and diodes, capacitors, A less complicated and effective model has been
and, output level inverter respectively. constructed. It is investigated and assessed to show the
significance and contribution of the suggestion inverter of
Table 2 Parameters Comparision of 7-Level inverters seven levels in the Matlab simulation program. The
requirements and elements are listed in TableIII and the
T NSW Nso NC ND NL TSV C- Gain source voltage is 100Vdc. The PWM level shift is used to
Balance gating pulses control of the power semiconductor switches,
[12] 7 3 3 2 7 15E NO 1 wherein V-reference is equal 50Hz and V-carrier is equal
[13] 16 1 3 0 7 16E YES 3 to 2.5 kHz, and the Ma is set to 1. A 2200 µF capacitance
[14] 16 1 2 0 7 16E YES 3 was chosen for C1 and C2 respectively to minimize the
[15] 10 2 3 0 7 16E YES 1.5 capacitor ripple voltage. The resistive load of 100 ohms in
[16] 6 3 3 8 7 14E NO 1 the inverter and according to waveforms of output voltage,
P.w 8 1 2 2 7 16E YES 3 current.
The proposed 7-level inverter topology(p.w) is a
symmetrical circuit comprised of a single DC source of Table 3 Simulation parameters of the proposed 7-l inverter
Vdc=100V. For inverter configuration, the prime
parameter is Total Standing Voltage (TSV). It is the
summation of the absolute voltage across every switching
device, while the same voltage stress occurs in the

59
Hussein S. Abdulazeez et al Seven-Level Inverter Topology

Description Simulation
Source Voltage (Vin) 100 V
Load Voltage (Vo) 300 V
Carrier’s frequency 2.5KHz
Fundamental frequency 50Hz (d)
Switching frequency 2.5KHz
Capacitor ( C1) 2200 µF
Capacitor (C2) 2200 µF
Load 100 ohms

(a)

(b
)
(c)

Fig. 5. Shows (a) Output voltage and load current(e)with R load (b) capacitors Voltages (c),(d)Shows THD
with GAs optimized firing angle for Ma =1 (e ) Standing voltage across the switching power devices
(S1,and S3)..

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Hussein S. Abdulazeez et al Seven-Level Inverter Topology

the capacitor's voltage as shown in Fig.5 (a and b). [4] Máthé L, Séra D, Kerekes T. “Three-phase
Through this, it can see the triple reinforcement of the photovoltaic systems: Structures, topologies, and
input source, as well as the stability in the voltages of the control”. Renewable Energy Devices and Systems
capacitors, which is one of the most important advantages with Simulations in Matlab® and Ansys; CRC Press:
of the work of this inverter. Boca Raton, FL, USA. 2017,67.
[5 Hosseini SH, Gharehkoushan AZ, Tarzamni H. “A
The three firing angles (α1,α2,α3) help to significantly multilevel boost converter based on a switched-
reduce the THD as shown in Fig. 5(c,d) where we notice capacitor structure”. In2017 10th International
that the value of the total harmonic distortion has improved Conference on Electrical and Electronics Engineering
from(18,31% to 15.32%) as a result of the optimization (ELECO) 2017 Nov 30 (. 249). IEEE.
technique used to implement the GAs optimized selective [6] Forouzesh M, Siwakoti YP, Gorji SA, Blaabjerg F,
Lehman B. “Step-up DC-DC converters: a
harmonic elimination.
comprehensive review of voltage-boosting
The voltage stress of each switch in the tippler section (S1, techniques, topologies, and applications”. IEEE
S1’, S2, and S2’) was 100V. and their remaining polarity transactions on power electronics. 2017 Mar
section ( S3, S3’, S4, and S4’ ) is 300 volts, Fig .5.(e) shows 6;32,9143.
the stress voltage across switches S1 and S3. [7] Sathik MJ, Sandeep N, Almakhles D, Blaabjerg F.
These results confirm the mathematical analysis in the “Cross connected compact switched-capacitor
fourth section when comparing the proposed inverter with multilevel inverter (C 3-SCMLI) topology with reduced
other studies, through which it was proved that the total switch count”. IEEE Transactions on Circuits and
standing voltage is equal to (16Vd.c). Systems II: Express Briefs. 2020 Apr 15;67,3287.
[8] Sathik MJ, Bhatnagar K, Sandeep N, Blaabjerg F.
Conclusions “An improved seven-level PUC inverter topology with
This paper introduces a new inverter with seven levels with voltage boosting”. IEEE Transactions on Circuits and
reduce all components of the inverter circuit. Eight Systems II: Express Briefs. 2019 Mar 5;67,127.
switches, two diodes, two capacitors, and a single DC [9] Samadaei E, Gholamian SA, Sheikholeslami A,
source make up the topology that was designed. Simple Adabi J. “An envelope type (E-Type) module:
design work is produced by the output voltage's asymmetric multilevel inverters with reduced
symmetrical upper and lower halves. the voltage gain components”. IEEE Transactions on Industrial
Triple the input. Three firing angles were obtained using Electronics. 2016 Jan 22;63,7148.
the SHE with GAs to reduce the lower order harmonics, [10] Samadaei E, Kaviani M, Bertilsson K. “A 13-
which lower the THD value. Due to the proposed levels module (K-type) with two DC sources for
topology's ability to self-balance, the voltages of the multilevel inverters”. IEEE Transactions on industrial
capacitors are naturally balanced. The capacitor's voltages electronics. 2018 Sep 10;66,5186..
are maintained using a straightforward series-parallel [11] Zeng J, Lin W, Cen D, Liu J. “Novel K-type
method without any additional circuit or any sensors. The multilevel inverter with reduced components and self-
principle of operation and the simple pulse modulation balance”. IEEE Journal of Emerging and Selected
method were discussed. The results of comprehensive and Topics in Power Electronics. 2019 Sep 5;8,4343.
detailed studies are presented, and the operability and [12] Choi JS, Kang FS. “Seven-level PWM inverter
viability of the suggested topology are validated. Finally, employing series-connected capacitors paralleled to
A detailed comparison with the other operating topologies a single DC voltage source”. IEEE Transactions on
in terms of decreased components confirms the merits of Industrial Electronics. 2014 Nov 14;62,3448.
the suggested topology. [13] Choi JS, Kang FS. “Seven-level PWM inverter
It can be used as another optimization technique to employing series-connected capacitors paralleled to
improve THD and replace the D.C source with a single DC voltage source”. IEEE Transactions on
photovoltaic (PV) modeling in future works. Industrial Electronics. 2014 Nov 14;62,3448.
[14] Choi JS, Kang FS. “Seven-level PWM inverter
References employing series-connected capacitors paralleled to
a single DC voltage source”. IEEE Transactions on
[1] Franquelo LG, Rodriguez J, Leon JI, Kouro S, Industrial Electronics. 2014 Nov 14;62,3448.
Portillo R, Prats MA. “The age of multilevel converters [15] Liu J, Zhu X, Zeng J. “A seven-level inverter with
arrives”. IEEE industrial electronics magazine. 2008 self-balancing and low-voltage stress”. IEEE Journal
Jun 17;228. of Emerging and Selected Topics in Power
[2] Gupta KK, Ranjan A, Bhatnagar P, Sahu LK, Jain Electronics. 2018 Nov 9;8,685.
S. “Multilevel inverter topologies with reduced device [16] Rahim NA, Chaniago K, Selvaraj J. “Single-
count: A review”. IEEE Transactions on Power phase seven-level grid-connected inverter for
Electronics. 2015 Feb 26;31,135. photovoltaic system”. IEEE transactions on industrial
[3] Sandeep N. “A 13-level switched-capacitor-based electronics. 2010 Aug 30;58,2435.
boosting inverter”. IEEE Transactions on Circuits and
Systems II: Express Briefs. 2020 Aug 18;68,998. [17] Gera G, Bairwa RK, Kumar D. “Genetic
Algorithm based Approach for Reduction of Total

61
Hussein S. Abdulazeez et al Seven-Level Inverter Topology

Harmonic Distortion in Photo Voltaic Inverter”.

International Journal of Computer Applications.
2014;87.
[18] Siddique MD, Mekhilef S, Padmanaban S,
Memon MA, Kumar C. “Single-phase step-up
switched-capacitor-based multilevel inverter topology
with SHEPWM”. IEEE Transactions on Industry
Applications. 2020 Jun 12;57,3107.
[19] Ozpineci B, Tolbert LM, Chiasson JN. “Harmonic
optimization of multilevel converters using genetic
algorithms”. In2004 IEEE 35th Annual Power
Electronics Specialists Conference (IEEE Cat. No.
04CH37551) 2004 Jun 20 (5,. 3911). IEEE.
[20] Dahidah MS, Konstantinou G, Agelidis VG. “A
review of multilevel selective harmonic elimination
PWM: formulations, solving algorithms,
implementation and applications”. IEEE Transactions
on Power Electronics. 2014 Sep 5;30,4091.
[21] Kannan M, Kaliyaperumal S. “A High Step-up
Sextuple Voltage Boosting 13S-13L Inverter With
Fewer Switch Count”. IEEE Access. 2021 Dec
8;9:164090.

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