Digital register

Flip-flop is a 1 bit memory cell which can be used for storing the
digital data. To increase the storage capacity in terms of number
of bits, we have to use a group of flip-flop. Such a group of flip-
flop is known as a Register. The n-bit register will consist
of n number of flip-flop and it is capable of storing an n-bit word.

The binary data in a register can be moved within the register

from one flip-flop to another. The registers that allow such data
transfers are called as shift registers. There are four mode of
operations of a shift register.

 Serial Input Serial Output

 Serial Input Parallel Output
 Parallel Input Serial Output
 Parallel Input Parallel Output

Serial Input Serial Output

Let all the flip-flop be initially in the reset condition i.e. Q3 = Q2 = Q1 = Q0 = 0. If an entry of
a four bit binary number 1 1 1 1 is made into the register, this number should be applied
to Din bit with the LSB bit applied first. The D input of FF-3 i.e. D3 is connected to serial data
input Din. Output of FF-3 i.e. Q3 is connected to the input of the next flip-flop i.e. D2 and so
on.

Block Diagram

Operation
Before application of clock signal, let Q3 Q2 Q1 Q0 = 0000 and apply LSB bit of the number to
be entered to Din. So Din = D3 = 1. Apply the clock. On the first falling edge of clock, the FF-3
is set, and stored word in the register is Q3 Q2 Q1 Q0 = 1000.
Apply the next bit to Din. So Din = 1. As soon as the next negative edge of the clock hits, FF-2
will set and the stored word change to Q3 Q2 Q1 Q0 = 1100.

Apply the next bit to be stored i.e. 1 to Din. Apply the clock pulse. As soon as the third
negative clock edge hits, FF-1 will be set and output will be modified to Q3 Q2 Q1 Q0 = 1110.

Similarly with Din = 1 and with the fourth negative clock edge arriving, the stored word in the
register is Q3 Q2 Q1 Q0 = 1111.

Truth Table
Waveforms

Serial Input Parallel Output

 In such types of operations, the data is entered serially and taken out in parallel
fashion.
 Data is loaded bit by bit. The outputs are disabled as long as the data is loading.
 As soon as the data loading gets completed, all the flip-flops contain their required
data, the outputs are enabled so that all the loaded data is made available over all the
output lines at the same time.
 4 clock cycles are required to load a four bit word. Hence the speed of operation of
SIPO mode is same as that of SISO mode.

Block Diagram
Parallel Input Serial Output (PISO)
 Data bits are entered in parallel fashion.
 The circuit shown below is a four bit parallel input serial output register.
 Output of previous Flip Flop is connected to the input of the next one via a
combinational circuit.
 The binary input word B0, B1, B2, B3 is applied though the same combinational circuit.
 There are two modes in which this circuit can work namely - shift mode or load
mode.

Load mode
When the shift/load bar line is low (0), the AND gate 2, 4 and 6 become active they will pass
B1, B2, B3 bits to the corresponding flip-flops. On the low going edge of clock, the binary
input B0, B1, B2, B3 will get loaded into the corresponding flip-flops. Thus parallel loading
takes place.

Shift mode
When the shift/load bar line is low (1), the AND gate 2, 4 and 6 become inactive. Hence the
parallel loading of the data becomes impossible. But the AND gate 1,3 and 5 become active.
Therefore the shifting of data from left to right bit by bit on application of clock pulses. Thus
the parallel in serial out operation takes place.

Block Diagram
Parallel Input Parallel Output (PIPO)
In this mode, the 4 bit binary input B0, B1, B2, B3 is applied to the data inputs D0, D1, D2,
D3 respectively of the four flip-flops. As soon as a negative clock edge is applied, the input
binary bits will be loaded into the flip-flops simultaneously. The loaded bits will appear
simultaneously to the output side. Only clock pulse is essential to load all the bits.

Block Diagram

Bidirectional Shift Register

  If a binary number is shifted left by one position then it is equivalent to multiplying
the original number by 2. Similarly if a binary number is shifted right by one position
then it is equivalent to dividing the original number by 2.
 Hence if we want to use the shift register to multiply and divide the given binary
number, then we should be able to move the data in either left or right direction.
 Such a register is called bi-directional register. A four bit bi-directional shift register
is shown in fig.
 There are two serial inputs namely the serial right shift data input DR, and the serial
left shift data input DL along with a mode select input (M).

Block Diagram

Operation

S.N. Condition Operation

If M = 1, then the AND

gates 1, 3, 5 and 7 are
enabled whereas the
remaining AND gates 2, 4, 6
and 8 will be disabled.
1 With M = 1 − Shift right operation The data at DR is shifted to
right bit by bit from FF-3 to
FF-0 on the application of
clock pulses. Thus with M =
1 we get the serial right shift
operation.

2 With M = 0 − Shift left operation When the mode control M is

connected to 0 then the AND
gates 2, 4, 6 and 8 are
enabled while 1, 3, 5 and 7
 are disabled.
The data at DL is shifted left
bit by bit from FF-0 to FF-3
on the application of clock
pulses. Thus with M = 0 we
get the serial right shift
operation.

Universal Shift Register

A shift register which can shift the data in only one direction is called a uni-directional shift
register. A shift register which can shift the data in both directions is called a bi-directional
shift register. Applying the same logic, a shift register which can shift the data in both
directions as well as load it parallely, is known as a universal shift register. The shift register
is capable of performing the following operation −

 Parallel loading
 Left Shifting
 Right shifting

The mode control input is connected to logic 1 for parallel loading operation whereas it is
connected to 0 for serial shifting. With mode control pin connected to ground, the universal
shift register acts as a bi-directional register. For serial left operation, the input is applied to
the serial input which goes to AND gate-1 shown in figure. Whereas for the shift right
operation, the serial input is applied to D input.
Block Diagram

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Counters play a crucial role in digital logic circuits, enabling tasks such as clock
frequency division and sequencing. This article explores the concept of ripple
counters, a type of asynchronous counter, their operation, advantages, and
disadvantages in digital logic design.
What is a Counter?
Counter is basically used to count the number of clock pulses applied to a flip-flop.
It can also be used for Frequency divider, time measurement, frequency
measurement, distance measurement, and also for generating square waveforms. In
this, the flip-flops are asynchronous counters and are supplied with different clock
signals, there may be a delay in producing output. Also, a few numbers of logic
gates are needed to design asynchronous counters. So they are elementary in design
and also are less expensive.
What is a Ripple counter?
Ripple counter is a cascaded arrangement of flip-flops where the output of one flip-
flop drives the clock input of the following flip-flop. The number of flip flops in the
cascaded arrangement depends upon the number of different logic states that it goes
through before it repeats the sequence a parameter known as the modulus of the
counter. A n-bit ripple counter can count up to 2 n states. It is also known as MOD n
counter. It is known as ripple counter because of the way the clock pulse ripples its
way through the flip-flops. Some of the features of ripple counter are:
 It is an asynchronous counter.
 Different flip-flops are used with a different clock pulse.
 All the flip-flops are used in toggle mode.
 Only one flip-flop is applied with an external clock pulse and another flip-
flop clock is obtained from the output of the previous flip-flop.
  The flip-flop applied with an external clock pulse act as LSB (Least
Significant Bit) in the counting sequence.
A counter may be an up counter that counts upwards or can be a down counter that
counts downwards or can do both [Link] up as well as count downwards
depending on the input control. The sequence of counting usually gets repeated after
a limit. When counting up, for the n-bit counter the count sequence goes from 000,
001, 010, … 110, 111, 000, 001, … etc. When counting down the count sequence
goes in the opposite manner: 111, 110, … 010, 001, 000, 111, 110, … etc.

1. Asynchronous Counter
In asynchronous counter we don’t use universal clock, only first flip flop is driven
by main clock and the clock input of rest of the following flip flop is driven by
output of previous flip flops. We can understand it by following diagram-
It is evident from timing diagram that Q0 is changing as soon as the rising edge of
clock pulse is encountered, Q1 is changing when rising edge of Q0 is
encountered(because Q0 is like clock pulse for second flip flop) and so on. In this
way ripples are generated through Q0,Q1,Q2,Q3 hence it is also
called RIPPLE counter and serial counter. A ripple counter is a cascaded
arrangement of flip flops where the output of one flip flop drives the clock input of
the following flip flop
2. Synchronous Counter
Unlike the asynchronous counter, synchronous counter has one global clock which
drives each flip flop so output changes in parallel. The one advantage of
synchronous counter over asynchronous counter is, it can operate on higher
frequency than asynchronous counter as it does not have cumulative delay because
of same clock is given to each flip flop. It is also called as parallel counter.

Synchronous counter circuit

 Timing diagram synchronous counter
From circuit diagram we see that Q0 bit gives response to each falling edge of clock
while Q1 is dependent on Q0, Q2 is dependent on Q1 and Q0 , Q3 is dependent on
Q2,Q1 and Q0.

Decade Counter
A decade counter counts ten different states and then reset to its initial states. A
simple decade counter will count from 0 to 9 but we can also make the decade
counters which can go through any ten states between 0 to 15(for 4 bit counter).

Clock pulse Q3 Q2 Q1 Q0

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 0 0 0 0

Truth table for simple decade counter

 Decade counter circuit diagram
We see from circuit diagram that we have used nand gate for Q3 and Q1 and feeding
this to clear input line because binary representation of 10 is—
1010
And we see Q3 and Q1 are 1 here, if we give NAND of these two bits to clear input
then counter will be clear at 10 and again start from beginning.
Important point: Number of flip flops used in counter a