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Microinstruction Sequencing Techniques

Microinstruction sequencing controls the generation of addresses for the next microinstruction. There are three techniques for determining the next address based on the microinstruction format: 1. Two Address Field technique stores two address fields in each microinstruction and a multiplexer selects the next address. 2. Single Address Field technique stores a single address field and can also select the next sequential address or an address from the instruction register. 3. Variable Format technique uses two different microinstruction formats, one to activate controls and the other to provide the address or specify a branch.

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37 views4 pages

Microinstruction Sequencing Techniques

Microinstruction sequencing controls the generation of addresses for the next microinstruction. There are three techniques for determining the next address based on the microinstruction format: 1. Two Address Field technique stores two address fields in each microinstruction and a multiplexer selects the next address. 2. Single Address Field technique stores a single address field and can also select the next sequential address or an address from the instruction register. 3. Variable Format technique uses two different microinstruction formats, one to activate controls and the other to provide the address or specify a branch.

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Sakshi More
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Microinstruction Sequencing:

A micro-program control unit can be viewed as consisting of two parts:

The control memory that stores the microinstructions.

Sequencing circuit that controls the generation of the next address.

A micro-program sequencer attached to a control memory inputs certain bits of the microinstruction,
from which it determines the next address for control memory. A typical sequencer provides the
following address-sequencing capabilities:

[Link] the present address for control memory.

[Link] to an address as specified by the address field of the micro instruction.

[Link] to a given address if a specified status bit is equal to 1.

[Link] control to a new address as specified by an external source (Instruction Register).

[Link] a facility for subroutine calls and returns.

Depending on the current microinstruction condition flags, and the contents of the instruction register, a
control memory address must be generated for the next micro instruction.

There are three general techniques based on the format of the address information in the
microinstruction:

[Link] Address Field.

[Link] Address Field.

[Link] Format
Two Address Field:

The simplest approach is to provide two address field in each microinstruction and multiplexer is
provided to select:

1. Address from the first address field.

[Link] from the second address field.

[Link] address based on the OPcode field in the current instruction.

The address selection signals are provided by a branch logic module whose input consists of control unit
flags plus bits from the control partition of the micro instruction.
Single Address Field:
Two-address approach is simple but it requires more bits in the microinstruction. With a simpler
approach, we can have a single address field in the micro instruction with the following options for the
next address.

 Address Field.
 Based on OPcode in instruction register.
 Next Sequential Address.

The address selection signals determine which option is selected. This approach reduces the number
of address field to one. In most cases (in case of sequential execution) the address field will not be
used. Thus the microinstruction encoding does not efficiently utilize the entire microinstruction.
Variable Format:

In this approach, there are two entirely different microinstruction formats. One bit designates which
format is being used. In this first format, the remaining bits are used to activate control signals. In
the second format, some bits drive the branch logic module, and the remaining bits provide the
address. With the first format, the next address is either the next sequential address or an address
derived from the instruction register. With the second format, either a conditional or unconditional
branch is specified.

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