2120923, 358 PM ‘VLSI Guru floorplan-pp-saurabh -VLSI Guru J +91-9986194181 & [Link]@[Link] CourseCalendar Resources Course Registration Training Overview video Internship Contact us IVLSIGURU L_] Home > floorplan-ppt-saurabh ‘IVLSIGURU’ Floor Planning Course Registration = [Link]-saurabh! ser2120123, 358 PM ‘VLSI Guru floorplan-pp-saurabh - VLSI Guru Physical Design Course Schedule ‘IVLSIGURU + WEEK_1: VLSI Physical Design Traini vi straints Timing, jifferent units) WEEK 3 : Floorplan, PowerPlan ‘Area calculation, Shapes(Rectangle, Rectilinear) of Floorplans, 1O/Macro placement, Special Cells(DOCAP/WELLTAP/ENDCAP) usage, Placement/Routing Blockages, Regions/Guides, Congestion Power Routing: Need for separate Power Routing, Types of Power Routing, PG-Rings/Strap/Mesh and std cell rail ASIC Design and PD Flow TIVLSIGURU ») sete Course Registration = [Link]-saurabh! 2er2120123, 358 PM ‘VLSI Guru floorplan-pp-saurabh = VLSI Guru Other PD Flow -Representations TIVLSIGURU eee] “me ‘ERE rating Rr _ ephcnet Ca 1 aie Fog PomeTson. + CHATS + precTsOnt. | on on : = on Ew I EE) ot {bor rowcinss | anne ea Agenda : Floorplanning IVLSIGURU O Related Terms O Goals and Objectives of Floorplanning Q Die Size Estimation O Flat and Hierarchical Floorplan (Advantages/Disadvantages) O Hierarchical Block : Pin Assignment Channels: Floorplan with Channels /Abutted Floorplan Macro Placement Guidelines O Blockages(Hard/Soft), PG Rings, Straps O Special cells O Floorplan sign-off checks 2 Course Registration = [Link]-saurabh!2720725, 358 PM ‘VLSI Guru floorplan-pp-saurabh - VLSI Guru Floorplanning : Related Terms/Objects ‘IVLSIGURU Q Width, Height, Shape, Aspect Ratio Q Chip Boundary/Size 0 Core Boundary 0 Pads, Macros, Halos, KeepOut Margin Q Location, Orientation of Macros. QO Ring, Power Grid 1 Module Guide, Region, Fence O Placement Blockage(Hard/Soft, Full/Partial), Routing Blockage Q WellTap Cells, EndCap Cells Q Density/Utilization Visi Demonstrating few Terms = FY CoretolO Space |__ i Bt oo -(Sianaaracars paceman = ——{MeROFeSHOTEMASS py wy = _ TT wy pa a = ‘Spacingaround Macros [Link]-saurabh 472120123, 358 PM ‘VLSI Guru floorplan-pp-saurabh -VLSI Guru TIVLSIGURU 73 Sais ining Wrenn Assign shape and location of Blocks/Macros = 1G Decide location of 1/0 pads. SSS! 1 ect toes cic ie >= 1G Daaatypa tteyerawteiiatoe, Q. Decide locationand type of clock distribution. S > Objectives panei cos (leap lady connie Biacl a gaicaliyeloacto aatirediae Minimize chip area(low cost) 1 Maries deg igh oT Sy) © Minimize wirelength. Atypical SoC could include hundreds of RAMS, soft and hard IP(Intellectual property), analog blocks. 8 as 6) 375 25 | je Size Estim: n - Factors Total Die Area comprises - Core Area 1, Standard cell area ~ Total area ofall modes inthe design and area of al buffers added for timing fixes 2, Memonyitacros area 2. Analog/Other Macros area +10 Area 4. Total no of Signal Pads 2-Totalno of Power Pads Aspect Ratio + Aspect Ratio = Width/Height + Decide the aspect ratio based on the avaiable horizontal & vertical routing tracks, Utilization (Thumb rule): Should be less than 70% ) Course Registration = tps [Link]-saurabh! 5272120123, 358 PM ‘VLSI Guru floorplan-pp-saurabh = VLSI Guru Die Size Estimation TIVLSIGURU Design can become (2) Core limited Design The size of the chip is decided based on the size of the core region (logic). The number of pads are less, so that the pads can be placed around the core. (b) Pad Limited Design Size of the chip is decided based on the No. of pads, because the core region is very small ‘The size of the die is decided based on the below factors = Core Limited/Pad Limited Die = Number of 0's = = = im [Link] limited _b, Pad Lifted core Limited Design tthe core areas more than the 1/0 padsarea thea the dle size willbe deterned by core area 1 Incoreiinited design we hhavolarge nof cls and lesser no of1/0 pads Wlimitations@ Pad Limited Design rte 1/0 pa areas more ‘ham the core area then the cle size willbe determined by 1/0 padares| Din padiimited design we hayelarge noo /O pads and lesser no ofloi cel 10 Chip Level Floorplans : Flat and Hierarchical VVLSIGURU Flat Chip Floorplan Hierarchical Chip Floorplan hitpssww. [Link]-saurabh! " Course Registration = ear2120123, 358 PM VAS! Guru tloorpa rab -VLSI Guru ‘Flat Floorplan Design : BIvisieuRU > It support optimization across functional boundaries resulting in smaller, faster chips > This design easily maps with todays flat place and route technologies > It requires EDA tools to support high capacity. > Does not help scope with the complexity 2 . ; __ BIVLSIGURU Hierarchical Floor Planning (Design Planning) > Ahierarchical design methodology is an efficient approach for managing large designs. > By dividing the design into multiple blocks, different design teams can work on each block in parallel, from RTL through physical implementation. > Working with smallerblocks and using multiply-instantiated blocks can reduce overallruntime. > Design planning is performed during the first stage of the hierarchical flow to partition the design into blocks, ‘generate hierarchical physical design constraints, and allocate top-level timing budgets to lower-level physical blocks. > Divided portions are termed as BLOCK, TILE, SUB-BLOCK, SUB-CHIP; Can be of Rectangular/Rectilinearshape. Closing smaller BLOCKsis fast and easy and independent while Chip level instantiates Black Boxes. > Once completed, can be integrated into chip. Fullchip Desian Skt] [Bk2] [ens Par] [Par] [Par Fiow| [Flow | | Flow © Fulichip Timing & Verification Course Registration = tps [Link]-saurabh! rer212073, 958 PM VSI Gun forplanppt-saurabn “VLSI Guns TIVLSIGURU Hierarchical Design Plan: Advantages / DisAdvantages > Advantages ¥ Faster runtime, ess memory needed for EDA tools ¥ Faster ecoturn-around time % Ability to do design re-use > Disadvantages Much more difficult for fullchip timing closure. > More intensivedesign planning needed Feedthrough generation, repeater insertion Timing constraint budgeting Hierarchical Chip Floorplan : A Sample ‘IVLSIGURU Ct Coe OOO aaa era ad i a a = io a io a a io Oo GGSGS0S00R8 See ebsebeeseeee Hierarchical Chip Floorplan Block-3 [Link]-saurabh a72720725, 358 PM ‘VLSI Guru floorplan-pp-saurabh - VLSI Guru Floorplanning : Pin(or IO) Assignment > Pin constraints include parameters such as, ¥ Layer,spacing Size([Link]) Overlap(in different layers) allowed or not Pin guides ane Types of Floorplan > Channeled Floorplan ¥ Channeled floorplans contain spacing between blocks for the placement of top-level macro cells. ¥ The spacing enables the tool to place standard cells between blocks. » Abutted Floorplan ¥ Inthe abutted floorplan style, blocksare touching and the tool does not allocatespace for macro cell placement between blocks. ¥- Designs with abutted floorplans do not require top-level optimization, as alllogicis pushed down into the blocks @ 2 [Link]-saurabh TIVLSIGURU Pin guide + Pin guide 2 Parton 16 TIVLSIGURU Blocks 972120123, 358 PM VLSI Guru floorplan-pp-saurabh - VLSI Guru TWIVLSIGURU Wiig Wr eng Ba = Macro placement Guidelines » Macro should be placed near to the Boundary/Edges. + Macro should be placed according to their hierarchy » Macro channel space(calculation) should be proper » Macro pins should be accessible » Macro pins orientation should correct or towards the core » Maximum space for the standard cell and routing, » Fly line Analysis, port Connectivity to be considered. » Orientation, Alignment of Macros has significance. 18 ‘Macro Grouping “TIVLSIGURU > Ramsare grouped based on module ames / data flow / timing / congestion. > Adjacent ram pins should align, iframs Delong to same logic/heightto get better routing tps [Link]-saurabh! 10272720725, 358 PM ‘VLSI Guru floorplan-pp-saurabh = VLSI Guru Macro Grouping TIVLSIGURU Bad Floorplan Good Floorplan Channel Width Calculation TBIVLSIGURU > To calculate the channel length b/w macros No of Pins Spacing b/w macros = ~ Available layers > Channel should accommodateat least 1 to 2 powersstraps + Block Halos + End caps cells + Switch cells (if [Link]-pp-saurabhi war2720725, 358 PM ‘VLSI Guru floorplan-pp-saurabh = VLSI Guru TIVLSIGURU Floor plan : Other Objects > Blockages can also be added in the floorplan to rohibit standards cells from being placed in those areas 2 Special Cells IVLSIGURU > Well Taps Y Well tap cellsare used to connect the VDD or GND to substrate or n-well respectively. This tohelp prevention of latch-up, Ore leet eet etree emt as eer [Link]-pp-saurabhi wer2720725, 358 PM ‘VLSI Guru floorplan-pp-saurabh = VLSI Guru Special cells TIVLSIGURU > Endeaps cells ¥ During fabrication, Poly variation is more at the edges. To account for that poly variation, dummy cells are inserted at the edges of the row so that manufacturing defects are reduced. LI ‘ | a = Sia Rows Endcops i. 2 endcaps “il Ei Hi IT 1 4 Special cells TIVLSIGURU Y These cells are used in Low-power applications. ¥ These cells are used to switch off the power domain when blocks are not in active state thus reducing leakage current, Normal SWITCHES, Staggered [Link]-pp-saurabhi 13272120123, 358 PM ‘VLSI Guru floorplan-pp-saurabh = VLSI Guru Floorplan signoff checks SMS > Visual checks Macros should be grouped based on data flow diagram ‘Should check macro are placed based on floorplan guidelines and have fixed attribute. ‘Should check end caps are placed and have fixed attribute. ‘Should check welltaps are added at regular intervals and have fixed attribute ‘Should check macro power tapping has done properly or not. ‘Should check Standard cell power rails to top layermetal vias are dropped properly or not. SAS Sean > Reports checks > Utilizationshould be under controlsafter floorplanning is done. ¥ IR drop should be within the limit. 26 What isa FlipiChip 2 BvescuRU Based on Packaging, Bond Pads placement, Chips Floor Plan can be classified as: 1. Wire Bond Chip 2. Flip Chip 27 2 Course Registration = tps [Link]-saurabh! wor2720725, 358 PM ‘VLSI Guru floorplan-pp-saurabh = VLSI Guru TIVLSIGURU IC Compiler GUI Floorplanning Toolbars(ICC) IVLSIGURU — 16272720725, 358 PM ‘VLSI Guru floorplan-pp-saurabh = VLSI Guru TIVLSIGURU Creating Floorplan (ICC Tool Command) create floorplan [bottom io2core distance] [control type aspect ratio | width and height | boundary] [core aspect ratio ratio] [core utilization ratio] [flip first_row] [-keep_io place] |-macro_place] [-keop std cell place] [left io2core distance] [-min_pad height] [-ne double back] [pad limit] [right io2cor [start first_row] [top io2core distance] [use vertical row] cance] TIVLSIGURU Power Planning [Link]-pp-saurabhi 16272120123, 358 PM ‘VLSI Guru floorplan-pp-saurabh = VLSI Guru Agenda : Power Planning TIVLSIGURU O Related Terms O Objectives of Power Planning O Power Estimation 0 Types of Power (Static, Dynamic, Leakage) O Power Planning Power Mesh Ci Issues : (IR Drop,Ground Bounce, EM) EM and IR-Drop Violations : Reasons and Solutions O Power Planning : Sanity Checks 0 Power Analysis(sign-off checks) 32 Power Planning : Related Terms/Objects @1VLSIGURU O Power Distribution, Power Network, Power Grid CEM : Electro Migration CEMIR(or EMR), IR-Drop, Power EM 10 Ring, PG Ring O Power & Ground (PG) CIR-Drop (Static, Dynamic, Vector-less) OQ Ground Bounce C Low Power Chip/Design, Multiple Power Domains C Level Shifters, Power Switches, O AlwaysON Block ; ON/OFF Block Qa Is for P ¥ Apache ; RedHawk ¥ — Cadence:Voltus (Earlier: EPS-Encounter Power System, Voltage Storm) ¥ Synopsys : PrimeRail+PTPX 33 ») sete Course Registration = tps [Link]-saurabh! wer2120123, 358 PM ‘VLSI Guru floorplan-pp-saurabh - VLSI Guru TIVLSIGURU Objectives of Power Planning/Routing > To distribute the power from power pads to all elements of the chip. > Unified supply of power with less voltage drop. > Aproper Power design should aim at using as less routing resources as possible. > Power Analysis checks (IR/EM) should be done after power planning is Completed au . . TIVLSIGURU Power Estimation Power Estimation is based on Total Power consumed by the Chip : > 10 Power > Core Power ([Link]) + Memory/Macro Power Core Power = Combinational logic Power + Sequential + Clock Power Where does the all power go to? 35 Course Registration = tps [Link]-saurabh! 180272120123, 358 PM ‘VLSI Guru floorplan-pp-saurabh - VLSI Guru Cl avtsicuRU Types of Power + Internal power (Static) Power dissipated due to cell internal loads and short circuit current, current flowing from VDD to VSS when both PMOS and NMOS are completely/partially ON + Switching power(Dynamic) Power dissipated due to standard cell, pads and macros charging and discharging the output load (interconnect + fanout loads) + Leakage power Due to leakage current in MOS Designs can have as high as 40% leakage contributions Power Planning > Power Planning includes : ¥ proper Estimation of power of chip ¥ power routing the design based on the estimation. > We create a mesh kind of structure, so that instance(s) can take direct supply from the nearest point > We create multiple VDD and VSS lines(for each power domain) > Hierarchical Mesh from upper metal layers to lowest(Mlor M2 layers for standard cells). Connection from higher to adjacent lower metal layer is through VIAs ® > tps [Link]-saurabh! 36 TIVisIGURU Power Ring, Power Straps, Power Mesh 37 Course Registration = 1927TIVLSIGURU Why create mesh kind of structure ? > To distribute the Power from power pads/pins to all elements of the chip. > Provides multiple paths from PG sources to destinations (less series resistance) > Uniformly distribute power with less voltage drop. > To meet IR/EM targets > For meeting timing requirements > Simultaneous Switching : Sometime it happens that, many instances switch from 0 to Lor vice-versa) almost at the same time, needing a huge amount of current; In this scenario this mesh kind of structure is very helpful ! ‘Simultaneous Switching: Sometime it happens that, ‘many instances switch from 0 to (or vice-versa) almostat the same time, needinga huge amount of current; In this scenario this mesh kind of structure Is very helpful ! Power Mesh : Sample Pictures VertialPower Stand Stipes Power Rall, Conuect Core Power Pads to Core Poser Rings visicuRU * @ 2 tps [Link]-saurabh! 20272120123, 358 PM ‘VLSI Guru floorplan-pp-saurabh = VLSI Guru a vesicu Power Planning Issues » IR Drop » Ground bounce > EM violations 40 "Wivisieuru! Reduction in voltage that occurs on power supply networks (VDD) IC design expects availabilty of ideal power supply In reality, localized voltage drops within the power grid > Increasing current/area on die > Narrower metal line widths (increases power grid resistance) Results in decreased power supply voltage at cells/transistors, > Decreases the operating voltage of the chip, resultingiin timing and functional failures vvy a IR Drop on Power Rail 2, ,Current through = “Sop (Shave ams = 4 2 Course Registration = tps [Link]-saurabh! er2120123, 358 PM ‘VLSI Guru floorplan-pp-saurabh - VLSI Guru eneanele la ee TIVLSIGURU jroun. 1c > Increase in voltage that occurs on ground networks (VSS or GND) in integrated circuits > Increase in ground voltage decreases the operating voltage of the chip, resulting in timing and, functional problems Lr ra TL be [ew] ne “a ‘Current 2 f EM violations @visicuru! | > electromigration (EM) refers to the unwanted movement of materials ina [em a conductor. If the current density is high enough, there can be a momentum transfer from moving electrons to the metal ions that make up the lattice of the interconnect material. The ions will drift in the direction of the electron flow. The results the gradual displacement of metal atoms in a conductor. > The effect is important in applications where high direct current densities are used, such as in microelectronics and related structures. As the structure size in electronics such as integrated circuits (ICs) decreases, the practical significance of this effect increases > Results of EM in ICs: The VOIDs and HILLOCKs gets created and potentially causing open and short circuits. (0) Mek A oe 43 2 Course Registration = tps [Link]-saurabh! ar2120123, 358 PM ‘VLSI Guru floorplan-pp-saurabh - VLSI Guru CC avtsicuRU Reasons of IR Drop Violations » Power structure is not proper. > Cell density is very high. - Instances are not get proper power because of no straps over there » Mesh structure is proper but there is no via. 44 I vesicuRU How to reduce IR drop ? » Routing should be from Top Layer. » By adding some more Power Stripes. - By increasing the width of the metal. v By adding Decaps(DCAP cells). v By using some Low Power Techniques 45 ») scuation # Course Registration = tps [Link]-saurabh! paar2120123, 358 PM ‘VLSI Guru floorplan-pp-saurabh = VLSI Guru @vesicURUTN EM violations : Reasons and Solution in PD > Reasons of EM violation: 1. High Fanout Net (multiple fanout cells switch simultaneously, draws larger current from driver) 2. Higher Driver Strength Cells(delivers large current unnecessarily, heating up the wire) 3, Higher frequency (quick transitions) 4, Narrow metal width 5, Metal slotting (resulting into narrower widths) 6. Long Nets (because of larger resistance, higher localized temperature) » Solutions of EM violations [Link] Driver's drive Strength 2. NonDefault (wider) rule based routing. 3. Insert buffer on long nets. 4, Route with higher metal layers(less resistive, higher tolerance (current carrying capabilities) 5. Use multi-Cut Via 6. Break the fanout (have lesser fanouts) 7. Use wider metals (more width) lS aveisicuRU Power Plan Checks « There should be no open connection + All the Macros should be hooked up with Power/Ground. . IR/EM target should be met. . Missing Vias should be taken care + There should be no Hot Spots (during IR-Drop Analysis) 47 2 Course Registration = [Link]-saurabh a72120123, 358 PM ‘VLSI Guru floorplan-pp-saurabh - VLSI Guru Whatis a Flip-Chip ? TIVLSIGURU Based on packaging, Chips can be classified as : 1. Wire Bond Chip 2. Flip Chip IR drop Map Hot Spot Voltage Drop Map Of Bumped Design [Link]-saurabh 28272720725, 358 PM ‘VLSI Guru floorplan-pp-saurabh - VLSI Guru Please put 100% efforts on WIVLsicuRU Weekly Assignments and Labs \ TIVLSIGURU visiGuru is a top VLSI training institute based in Bangalore. Setup in 2012 with the motto of ‘quality education at affordable fee’ and providing 100% job oriented courses. E-Learning Internship Request FAQS Course Registration Functional / ASIC verification Physical Design [Link]-saurabh 2s2120923, 358 PM ‘VLSI Guru floorplan-pp-saurabh -VLSI Guru RTL design and integration Functional verification Design for testability (DFT) Physical verification Custom and Analog Layout FPGA system design synthesis and STA Embedded systems IR Drop analysis using RedHawk PERL Training ‘Custom/Analog layout Physical Design OU000 © 2022 - VSI Guru. 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