Basic Language
Constructs of VHDL
Based on slides from Pong P. Chou
Outline
1. Basic VHDL program
2. Lexical elements and program format
3. Objects
4. Data type and operators
COEN313 - 2
1. Basic VHDL
program
Design unit
è Building blocks in a VHDL program
è Each design unit is analyzed and stored
independently
è Types of design unit:
– entity declaration
– architecture body
– package declaration
– package body
– configuration
COEN313 - 4
Entity declaration
• Simplified syntax
COEN313 - 5
• mode:
– in: flow into the circuit
– out: flow out of the circuit
– inout: bi-directional
• E.g.
COEN313 - 6
• A common mistake with mode
COEN313 - 7
• Fix: use an internal signal
COEN313 - 8
Architecture body
• Simplified syntax
• An entity declaration can be associated
with multiple architecture bodies
COEN313 - 9
E.g.
COEN313 - 10
VHDL Library
• A place to store the analyzed design units
• Normally mapped to a directory in host
computer
• Software define the mapping between the
symbolic library and physical location
• Default library: “work”
• Library “ieee” is used for many ieee
packages
COEN313 - 12
• E.g.
• Line 1: invoke a library named ieee
• Line 2: makes std_logic_1164 package visible to the
subsequent design units
• The package is normally needed for the
std_logic/std_logic_vector data type
COEN313 - 13
Processing of VHDL code
• Analysis
– Performed on “design unit” basis
– Check the syntax and translate the unit
into an intermediate form
– Store it in a library
• Elaboration
– Bind architecture body with entity
– Substitute the instantiated
components with architecture
description
– Create a “flattened”' description
• Execution
– Simulation or synthesis
COEN313 - 14
2. Lexical elements and
program format
Lexical elements
• Lexical element:
– Basic syntactical units in a VHDL program
• Types of Lexical elements:
– Comments
– Identifiers
– Reserved words
– Numbers
– Characters
– Strings
COEN313 - 16
Comments
• Starts with - -
• Just for clarity
• e.g.,
COEN313 - 17
Identifier
• Identifier is the name of an object
• Basic rules:
– Can only contain alphabetic letters, decimal
digits and underscore
– The first character must be a letter
– The last character cannot be an
underscore
– Two successive underscores are not
allowed
COEN313 - 18
Identifier
• Valid examples:
A10, next_state, NextState,
mem_addr_enable
• Invalid examples:
sig#3, _X10, 7segment, X10_, hi_ _there
• VHDL is case insensitive:
– Following identifiers are the same:
nextstate, NextState, NEXTSTATE,
nEXTsTATE
COEN313 - 19
Reserved words
COEN313 - 20
Numbers, characters
and strings
• Number:
– Integer: 0, 1234, 98E7
– Real: 0.0, 1.23456 or 9.87E6
– Base 2: 2#101101#
• Character:
– ‘A’, ‘Z’, ‘1’
• Strings
– “Hello”, “101101”
• Note
– 0 and ‘0’ are different
– 2#101101# and “101101” are different COEN313 - 21
Program format
• VHDL is “free-format”: blank space, tab, new-
line can be freely inserted
• e.g., the following are the same
COEN313 - 22
COEN313 - 23
• A good
“header”
COEN313 - 24
3. Objects
Objects
• A named item that hold a value of specific
data type
• Four kinds of objects
– Signal
– Variable
– Constant
– File (cannot be synthesized)
• Related construct
– Alias
COEN313 - 26
Signal
• Declared in the architecture body's
declaration section
• Signal declaration:
signal signal_name, signal_name, ... : data_type
• Signal assignment:
signal_name <= projected_waveform;
• Ports in entity declaration are considered as
signals
• Can be interpreted as wires or “wires with
memory” (i.e., FFs, latches etc.)
COEN313 - 27
Variable
• Declared and used inside a process
• Variable declaration:
variable variable_name, ... : data_type
• Variable assignment:
variable_name := value_expression;
• Contains no “timing info” (immediate assignment)
• Used as in traditional PL: a “symbolic memory
location” where a value can be stored and modified
• No direct hardware counterpart
COEN313 - 28
Constant
• Value cannot be changed
• Constant declaration:
constant const_name, ... : data_type :=
value_expression
• Used to enhance readability
– E.g.,
COEN313 - 29
Alias
• Not a object
• Alternative name for an object
• Used to enhance readability
– E.g.,
COEN313 - 30
4. Data type and
operators
Standard VHDL
IEEE1164_std_logic package
IEEE numeric_std package
Data type
• Definition of data type
– A set of values that an object can assume.
– A set of operations that can be performed
on objects of this data type.
• VHDL is a strongly-typed language
– an object can only be assigned with a value
of its type
– only the operations defined with the data
type can be performed on the object
COEN313 - 32
Data types in standard VHDL
• integer:
– Minimal range: -(2^31-1) to 2^31-1
– Two subtypes: natural, positive
• boolean: (false, true)
• bit: ('0', '1')
• bit_vector: a one-dimensional array of bit
COEN313 - 33
Multi-valued Types
Multi-valued logic-systems are declared via new datatypes:
–‘U’
–uninitialized
–‘X’
–unknown
–‘Z’
–high impedance (tri-state)
–‘W’
–Weak Unknown
–‘L’
–Weak 0
–‘H’
–Weak 1
–‘-’
–Don’t care
–‘0’
–Logical 0
–‘1’
–Logical 1
STD_LOGIC and STD_ULOGIC IEEE standard types.
Package: STD_LOGIC_1164
COEN313 - 34
• std_logic_vector
– an array of elements with std_logic data type
– Imply a bus
– E.g.,
signal a: std_logic_vector(7 downto 0);
– Another form (less desired)
signal a: std_logic_vector(0 to 7);
• Need to invoke package to use the data type:
library ieee;
use ieee.std_logic_1164.all;
COEN313 - 35
Operators over an array data
type
• Concatenation operator (&)
• e.g.,
y <= "00" & a(7 downto 2);
y <= a(7) & a(7) & a(7 downto 2);
y <= a(1 downto 0) & a(7 downto 2);
Assume a = “10101010”; What’s the value of
Signal y after the execution of each of the above
statement?
COEN313 - 36
Array aggregate
• Aggregate is a VHDL construct to assign a value to
an array-typed object
• E.g.,
a <= "10100000";
a <= (7=>'1', 6=>'0', 0=>'0', 1=>'0', 5=>'1',
4=>'0', 3=>'0', 2=>'1');
a <= (7|5=>'1', 6|4|3|2|1|0=>'0');
a <= (7|5=>'1', others=>'0');
• E.g.,
a <= "00000000"
a <= (others=>'0');
COEN313 - 37