Femtoampere Input Bias Current

Electrometer Amplifier
Data Sheet ADA4530-1
FEATURES PIN CONNECTION DIAGRAM
Low input bias current ADA4530-1
±20 fA maximum at TA = 25°C (guaranteed at production test) +IN 1 8 –IN
± 20 fA maximum at −40°C < TA < +85°C GRD 2 7 GRD
± 250 fA maximum at −40°C < TA < +125°C (guaranteed at IC 3 6 OUT
production test)
V– 4 5 V+
Low offset voltage: 50 μV maximum over specified CMRR range
Offset drift: 0.13 μV/°C typical, 0.5 μV/°C maximum NOTES
1. IC = INTERNAL CONNECTION. THIS

13405-001
Integrated guard buffer with 100 μV maximum offset PIN MUST BE CONNECTED TO V–
OR LEFT UNCONNECTED.
Low voltage noise density: 14 nV/√Hz at 10 kHz
Figure 1.
Wide bandwidth: 2 MHz unity-gain crossover
Supply voltage: 4.5 V to 16 V (±2.25 V to ±8 V)
Operating temperature: −40°C to +125°C

APPLICATIONS
Laboratory and analytical instrumentation:
spectrophotometers, chromatographs, mass
spectrometers, and potentiostatic and amperostatic
coulometry
Instrumentation: picoammeters and coulombmeters
Transimpedance amplifier (TIA) for photodiodes, ion
chambers, and working electrode measurements
High impedance buffering for chemical sensors and
capacitive sensors

GENERAL DESCRIPTION
The ADA4530-1 is a femtoampere (10−15 A) level input bias output stage that can typically drive to within 30 mV of the
current operational amplifier suitable for use as an electrometer supply rails under a 10 kΩ load.
that also includes an integrated guard buffer. It has an operating The ADA4530-1 operates over the −40°C to +125°C industrial
voltage range of 4.5 V to 16 V enabling it to operate in conven- temperature range and is available in an 8-lead SOIC package.
tional 5 V and 10 V single supply systems as well as ±2.5 V and 1000
±5 V dual supply systems. VSY = 10V –40°C TO +125°C LIMIT
VCM = VSY/2
It provides ultralow input bias currents that are production 100 RH < 10%
–40°C TO +85°C LIMIT
tested at temperature to ensure the device meets its perfor-
mance goals in user systems. The integrated guard buffer is 10

provided to isolate the input pins from leakage in the printed

IB (fA)

circuit board (PCB), minimize board component count, and 1

enable ease of system design. The ADA4530-1 is available in an

industry-standard surface-mount 8-lead SOIC package with a 0.1 IB+
IB–
unique pinout optimized to prevent signals from coupling
between the sensitive input pins, the power supplies, and the 0.01

output pin while enabling easy routing of the guard ring traces.
0.001
13405-202

The ADA4530-1 also offers low offset voltage, low offset drift, 0 10 20 30 40 50 60 70 80 90 100 110 120 130
and low voltage and current noise needed for the types of TEMPERATURE (°C)

applications that require such low leakages. To maximize the Figure 2. Input Bias Current (IB) vs. Temperature, VSY = 10 V
dynamic range of the system, the ADA4530-1 has a rail-to-rail

Rev. A Document Feedback

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Trademarks and registered trademarks are the property of their respective owners. Technical Support [Link]
ADA4530-1* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017

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ADA4530-1 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1  Input Bias Current ...................................................................... 32 
Applications ....................................................................................... 1  Input Resistance.......................................................................... 33 
Pin Connection Diagram ................................................................ 1  Input Offset Voltage ................................................................... 33 
General Description ......................................................................... 1  Insulation Resistance ................................................................. 33 
Revision History ............................................................................... 2  Guarding ...................................................................................... 34 
Specifications..................................................................................... 3  Dielectric Relaxation.................................................................. 34 
5 V Nominal Electrical Characteristics ..................................... 3  Humidity Effects......................................................................... 36 
10 V Nominal Electrical Characteristics ................................... 5  Contamination............................................................................ 37 
15 V Nominal Electrical Characteristics ................................... 7  Cleaning and Handling ............................................................. 38 
Absolute Maximum Ratings............................................................ 9  Solder Paste Selection ................................................................ 38 
Thermal Resistance ...................................................................... 9  Current Noise Considerations ...................................................... 39 
ESD Caution .................................................................................. 9  Layout Guidelines ........................................................................... 42 
Pin Configuration and Function Descriptions ........................... 10  Physical Implementation of Guarding Techniques................ 42 
Typical Performance Characteristics ........................................... 11  Guard Ring .................................................................................. 42 
Main Amplifier, DC Performance ............................................ 11  Guard Plane................................................................................. 42 
Main Amplifier, AC Performance ............................................ 20  Via Fence ..................................................................................... 43 
Guard Amplifier ......................................................................... 26  Cables and Connectors .............................................................. 43 
Theory of Operation ...................................................................... 28  Electrostatic Interferance .......................................................... 43 
ESD Structure.............................................................................. 28  Photodiode Interface...................................................................... 44 
Input Stage ................................................................................... 28  DC Error Analysis ...................................................................... 44 
Gain Stage .................................................................................... 29  AC Error Analysis ...................................................................... 44 
Output Stage ................................................................................ 29  Noise Analysis ............................................................................. 45 
Guard Buffer ............................................................................... 29  Design Recommendations ........................................................ 46 
Applications Information .............................................................. 30  Design Example .......................................................................... 46 
Input Protection.......................................................................... 30  Power Supply Recommendations ................................................. 49 
Single-Supply and Rail-to-Rail Output ................................... 30  Power Supply Considerations ................................................... 49 
Capacitive Load Stability ........................................................... 30  Outline Dimensions ....................................................................... 50 
EMI Rejection Ratio ................................................................... 31  Ordering Guide .......................................................................... 50 
High Impedance Measurements ................................................... 32 

REVISION HISTORY
3/16—Rev. 0 to Rev. A
Changed DNC Pin to IC Pin ........................................ Throughout
Changes to Figure 1 .......................................................................... 1
Changes to Figure 3 and Table 6 ................................................... 10
Changes to Figure 29 ...................................................................... 15
Changes to Theory of Operation Section .................................... 28
Changes to Humidity Effects Section and Figure 112 ............... 36
Added Power Supply Recommendations Section, Power
Supply Considerations Section, Table 16, and Figure 133 to
Figure 135 ........................................................................................ 49

10/15—Revision 0: Initial Version

Rev. A | Page 2 of 50
Data Sheet ADA4530-1

SPECIFICATIONS
5 V NOMINAL ELECTRICAL CHARACTERISTICS
VSY = 4.5 V, VCM = VSY/2, TA = 25°C, unless otherwise specified. Typical specifications are equal to the average of the distribution from
characterization, unless otherwise noted. Minimum and maximum specifications are tested in production, unless otherwise noted.

Table 1.
Parameter1 Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Input Bias Current2, 3 IB RH < 50% <1 ±20 fA
−40°C < TA < +85°C, RH < 50% ±20 fA
−40°C < TA < +125°C, RH < 50% ±250 fA
Input Offset Current3 IOS RH < 50% <1 ±20 fA
−40°C < TA < +125°C, RH < 50% ±150 fA
Offset Voltage2, 4 VOS +8 ±40 μV
VCM = 1.5 V to 3 V +9 ±50 μV
VCM = 1.5 V to 3 V, 0°C < TA < 125°C ±70 μV
VCM = 1.5 V to 3 V, −40°C < TA < 0°C ±150 μV
VCM = 0 V to 3 V ±300 μV
Offset Voltage Drift2, 4 ΔVOS/ΔT 0°C < TA < 125°C +0.13 ±0.5 μV/°C
−40°C < TA < 0°C −0.7 ±2.8 μV/°C
Input Voltage Range IVR 0 3 V
Common-Mode Rejection Ratio CMRR VCM = 1.5 V to 3 V 92 114 dB
−40°C < TA < +125°C 90 dB
VCM = 0 V to 3 V 73 dB
Large Signal Voltage Gain AVO RL = 2 kΩ to VCM, VOUT = 0.2 V to 4.3 V 120 143 dB
−40°C < TA < +125°C 120 dB
Input Resistance RIN −40°C < TA < +125°C >100 TΩ
Input Capacitance CIN 8 pF
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 10 kΩ to VCM 4.47 4.49 V
−40°C < TA < +125°C 4.46 V
RL = 2 kΩ to VCM 4.4 4.45 V
−40°C < TA < +125°C 4.38 V
Output Voltage Low VOL RL = 10 kΩ to VCM 10 30 mV
−40°C < TA < +125°C 40 mV
RL = 2 kΩ to VCM 30 100 mV
−40°C < TA < +125°C 120 mV
Short-Circuit Current ISC
Source 15 mA
Sink −30 mA
Closed-Loop Output Impedance ZOUT f = 1 MHz, AV = 1 20 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = 4.5 V to 16 V 130 150 dB
−40°C < TA < +125°C 130 dB
Supply Current ISY IOUT = 0 mA 0.9 1.3 mA
−40°C < TA < +125°C 1.5 mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 10 kΩ, CL = 10 pF, AV = 1 1.4 V/μs
Gain Bandwidth Product GBP VIN = 10 mV rms, RL = 10 kΩ, CL = 10 pF, 2 MHz
AV = 100
Unity-Gain Crossover UGC VIN = 10 mV rms, RL = 10 kΩ, CL = 10 pF, 2 MHz
AVO = 1
−3 dB Closed-Loop Bandwidth f−3dB VIN=10 mV rms, RL = 10 kΩ, CL = 10 pF, 6 MHz
AV = 1
Rev. A | Page 3 of 50
ADA4530-1 Data Sheet
Parameter1 Symbol Test Conditions/Comments Min Typ Max Unit
Phase Margin ΦM VIN = 10 mV rms, RL = 10 kΩ, CL = 10 pF, 62 Degrees
AVO = 1
Settling Time to 0.1% tS VIN = 0.5 V step, RL = 10 kΩ, CL= 10 pF, 5 μs
AV = −1
EMI Rejection Ratio of +IN EMIRR VIN = 100 mV peak, f = 400 MHz 50 dB
VIN = 100 mV peak, f = 900 MHz 60 dB
VIN = 100 mV peak, f = 1800 MHz 80 dB
VIN = 100 mV peak, f = 2400 MHz 90 dB
NOISE PERFORMANCE
Peak-to-Peak Voltage Noise eN p-p f = 0.1 Hz to 10 Hz 4 μV p-p
Voltage Noise Density eN f = 10 Hz 80 nV/√Hz
f = 1 kHz 16 nV/√Hz
f = 10 kHz 14 nV/√Hz
Current Noise Density IN f = 0.1 Hz 0.07 fA/√Hz
Total Harmonic Distortion + Noise THD + N AV = 1, f = 1 kHz, VIN = 0.5 V rms
Bandwidth = 90 kHz 0.003 %
Bandwidth = 500 kHz 0.0045 %
GUARD BUFFER
Guard Offset Voltage2, 4, 5 VGOS VCM = 1.5 V to 3 V 15 100 μV
VCM = 1.5 V to 3 V, 0°C < TA < 125°C 120 μV
VCM = 1.5 V to 3 V, −40°C < TA < 0°C 250 μV
VCM = 0.1 V to 3 V 150 μV
Guard Offset Voltage Drift2, 4 ΔVGOS/ΔT 0°C < TA < +125°C 0.18 1 μV/°C
−40°C < TA < 0°C 1.4 7 μV/°C
Output Impedance ZGOUT 1 kΩ
Output Voltage Range VGOS < 150 μV 0.1 3 V
−3 dB Bandwidth f−3dBGUARD VIN = 10 mV rms, CL = 10 pF 5.5 MHz
1
These specifications represent the performance for 5 V ± 10% power supplies. All specifications are measured at the worst case 4.5 V supply voltage.
2
The maximum specifications at −40°C < TA < +85°C and −40°C < TA < 0°C are guaranteed from characterization.
3
RH is relative humidity (see the Humidity Effects section for more information).
4
The typical specifications are equal to the average plus the standard deviation of the distribution from characterization.
5
The guard offset voltage is the voltage difference between the guard output and the noninverting input.

Rev. A | Page 4 of 50
Data Sheet ADA4530-1
10 V NOMINAL ELECTRICAL CHARACTERISTICS
VSY = 10 V, VCM = VSY/2, TA = 25°C, unless otherwise noted. Typical specifications are equal to the average of the distribution from
characterization, unless otherwise noted. Minimum and maximum specifications are tested in production, unless otherwise noted.
Table 2.
Parameter1 Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Input Bias Current2, 3 IB RH < 50% <1 ±20 fA
−40°C < TA < +85°C, RH < 50% ±20 fA
−40°C < TA < +125°C, RH < 50% ±250 fA
Input Offset Current3 IOS RH < 50% <1 ±20 fA
−40°C < TA < +125°C, RH < 50% ±150 fA
Offset Voltage2, 4 VOS +8 ±40 μV
VCM = 1.5 V to 8.5 V +9 ±50 μV
VCM = 1.5 V to 8.5 V, 0°C < TA < 125°C ±70 μV
VCM = 1.5 V to 8.5 V, −40°C < TA < 0°C ±150 μV
VCM = 0 V to 8.5 V ±300 μV
Offset Voltage Drift2, 4 ΔVOS/ΔT 0°C < TA < 125°C +0.13 ±0.5 μV/°C
−40°C < TA < 0°C −0.7 ±2.8 μV/°C
Input Voltage Range IVR 0 8.5 V
Common-Mode Rejection Ratio CMRR VCM = 1.5 V to 8.5 V 105 114 dB
−40°C < TA < +125°C 100 dB
VCM = 0 V to 8.5 V 87 dB
Large Signal Voltage Gain AVO RL = 2 kΩ to VCM, VOUT = 0.5 V to 9.5 V 125 150 dB
−40°C < TA < +125°C 125 dB
Input Resistance RIN −40°C < TA < +125°C >100 TΩ
Input Capacitance CIN 8 pF
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 10 kΩ to VCM 9.96 9.97 V
−40°C < TA < +125°C 9.94 V
RL = 2 kΩ to VCM 9.93 9.87 V
−40°C < TA < +125°C 9.75 V
Output Voltage Low VOL RL = 10 kΩ to VCM 15 40 mV
−40°C < TA < +125°C 60 mV
RL = 2 kΩ to VCM 70 170 mV
−40°C < TA < +125°C 250 mV
Short-Circuit Current ISC
Source 15 mA
Sink −30 mA
Closed-Loop Output Impedance ZOUT f = 1 MHz, AV = 1 20 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = 4.5 V to 16 V 130 150 dB
−40°C < TA < +125°C 130 dB
Supply Current ISY IOUT = 0 mA 0.9 1.3 mA
−40°C < TA < +125°C 1.5 mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 10 kΩ, CL = 10 pF, AV = 1 1.4 V/μs
Gain Bandwidth Product GBP VIN = 10 mV rms, RL = 10 kΩ, CL = 10 pF, 2 MHz
AV = 100
Unity-Gain Crossover UGC VIN = 10 mV rms, RL = 10 kΩ, CL = 10 pF, 2 MHz
AVO = 1
−3 dB Closed-Loop Bandwidth f−3dB VIN = 10 mV rms, RL = 10 kΩ, CL = 10 pF, 6 MHz
AV = 1
Phase Margin ΦM VIN = 10 mV rms, RL = 10 kΩ, CL = 10 pF, 62 Degrees
AVO = 1
Rev. A | Page 5 of 50
ADA4530-1 Data Sheet
Parameter1 Symbol Test Conditions/Comments Min Typ Max Unit
Settling Time to 0.1% tS VIN = 1 V step, RL = 10 kΩ, CL = 10 pF, 6 μs
AV = −1
EMI Rejection Ratio of +IN EMIRR VIN = 100 mV peak, f = 400 MHz 50 dB
VIN = 100 mV peak, f = 900 MHz 60 dB
VIN = 100 mV peak, f = 1800 MHz 80 dB
VIN = 100 mV peak, f = 2400 MHz 90 dB
NOISE PERFORMANCE
Peak-to-Peak Voltage Noise eN p-p f = 0.1 Hz to 10 Hz 4 μV p-p
Voltage Noise Density eN f = 10 Hz 80 nV/√Hz
f = 1 kHz 16 nV/√Hz
f = 10 kHz 14 nV/√Hz
Current Noise Density IN f = 0.1 Hz 0.07 fA/√Hz
Total Harmonic Distortion + Noise THD + N AV = 1, f = 1 kHz, VIN = 2 V rms
Bandwidth = 90 kHz 0.0015 %
Bandwidth = 500 kHz 0.0025 %
GUARD BUFFER
Guard Offset Voltage2, 4, 5 VGOS VCM = 1.5 V to 8.5 V 15 100 μV
VCM = 1.5 V to 8.5 V, 0°C < TA < 125°C 120 μV
VCM = 1.5 V to 8.5 V, −40°C < TA < 0°C 250 μV
VCM = 0.1 V to 8.5 V 150 μV
Guard Offset Voltage Drift2, 4 ΔVGOS/ΔT 0°C < TA < 125°C 0.18 1 μV/°C
−40°C < TA < 0°C 1.4 7 μV/°C
Output Impedance ZGOUT 1 kΩ
Output Voltage Range VGOS < 150 μV 0.1 8.5 V
−3 dB Bandwidth f−3dBGUARD VIN = 10 mV rms, CL = 10 pF 5.5 MHz
1
These specifications represent the performance for 10 V ± 10% power supplies. All specifications are measured at the 10 V supply voltage.
2
The maximum specifications at −40°C < TA < +85°C and −40°C < TA < 0°C are guaranteed from characterization.
3
RH is relative humidity (see the Humidity Effects section for more information).
4
These typical specifications are equal to the average plus the standard deviation of the distribution from characterization.
5
The guard offset voltage is the voltage difference between the guard output and the noninverting input.

Rev. A | Page 6 of 50
Data Sheet ADA4530-1
15 V NOMINAL ELECTRICAL CHARACTERISTICS
VSY = 16 V, VCM = VSY/2, TA = 25°C, unless otherwise noted. Typical specifications are equal to the average of the distribution from
characterization, unless otherwise noted. Minimum and maximum specifications are tested in production, unless otherwise noted.

Table 3.
Parameter1 Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Input Bias Current2, 3 IB RH < 50% <1 ±20 fA
−40°C < TA < +85°C, RH < 50% ±20 fA
−40°C < TA < +125°C, RH < 50% ±250 fA
Input Offset Current IOS RH < 50% <1 ±20 fA
−40°C < TA < +125°C, RH < 50% ±150 fA
Offset Voltage2, 4 VOS +8 ±40 μV
VCM = 1.5 V to 14.5 V +9 ±50 μV
VCM = 1.5 V to 14.5 V, 0°C < TA < 125°C ±70 μV
VCM = 1.5 V to 14.5 V, −40°C < TA < 0°C ±150 μV
VCM = 0 V to 14.5 V ±300 μV
Offset Voltage Drift2, 4 ΔVOS/ΔT 0°C < TA < 125°C +0.13 ±0.5 μV/°C
−40°C < TA < 0°C −0.7 ±2.8 μV/°C
Input Voltage Range IVR 0 14.5 V
Common-Mode Rejection Ratio CMRR VCM = 1.5 V to 14.5 V 110 114 dB
−40°C < TA < +125°C 105 dB
VCM = 0 V to 14.5 V 93 dB
Large Signal Voltage Gain AVO RL = 2 kΩ to VCM, VOUT = 0.5 V to 15.5 V 130 155 dB
−40°C < TA < +125°C 125 dB
Input Resistance RIN −40°C < TA < +125°C >100 TΩ
Input Capacitance CIN 8 pF
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 10 kΩ to VCM 15.93 15.95 V
−40°C < TA < +125°C 15.9 V
RL = 2 kΩ to VCM 15.72 15.78 V
−40°C < TA < +125°C 15.58 V
Output Voltage Low VOL RL = 10 kΩ to VCM 25 70 mV
−40°C < TA < +125°C 100 mV
RL = 2 kΩ to VCM 115 280 mV
−40°C < TA < +125°C 420 mV
Short-Circuit Current ISC
Source 15 mA
Sink −30 mA
Closed-Loop Output Impedance ZOUT f = 1 MHz, AV = 1 20 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = 4.5 V to 16 V 130 150 dB
−40°C < TA < +125°C 130 dB
Supply Current ISY IOUT = 0 mA 0.9 1.3 mA
−40°C < TA < +125°C 1.5 mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 10 kΩ, CL = 10 pF, AV = 1 1.4 V/μs
Gain bandwidth Product GBP VIN = 10 mV rms, RL = 10 kΩ, CL = 10 pF, 2 MHz
AV = 100
Unity-Gain Crossover UGC VIN = 10 mV rms, RL = 10 kΩ, CL = 10 pF, 2 MHz
AVO = 1
−3 dB Closed-Loop Bandwidth f−3 dB VIN = 10 mV rms, RL = 10 kΩ, CL = 10 pF, 6 MHz
AV = 1
Phase Margin ΦM VIN =10 mV rms, RL = 10 kΩ, CL = 10 pF, 62 Degrees
AVO = 1
Rev. A | Page 7 of 50
ADA4530-1 Data Sheet
Parameter1 Symbol Test Conditions/Comments Min Typ Max Unit
Settling Time to 0.1% tS VIN = 1 V step, RL = 10 kΩ, CL = 10 pF, 6 μs
AV = −1
EMI Rejection Ratio of +IN EMIRR VIN = 100 mV peak, f = 400 MHz 50 dB
VIN = 100 mV peak, f = 900 MHz 60 dB
VIN = 100 mV peak, f = 1800 MHz 80 dB
VIN = 100 mV peak, f = 2400 MHz 90 dB
NOISE PERFORMANCE
Peak-to-Peak Voltage Noise eN p-p f = 0.1 Hz to 10 Hz 4 μV p-p
Voltage Noise Density eN f = 10 Hz 80 nV/√Hz
eN f = 1 kHz 16 nV/√Hz
eN f = 10 kHz 14 nV/√Hz
Current Noise Density IN f = 0.1 Hz 0.07 fA/√Hz
Total Harmonic Distortion + Noise THD + N AV = 1, f = 1 kHz, VIN = 4.5 V rms
Bandwidth = 90 kHz 0.0012 %
Bandwidth = 500 kHz 0.003 %
GUARD BUFFER
Guard Offset Voltage4, 5 VGOS VCM = 1.5 V to 14.5 V 15 100 μV
VCM = 1.5 V to 14.5 V, 0°C < TA < 125°C 120 μV
VCM = 1.5 V to 14.5 V, −40°C < TA < 0°C 250 μV
VCM = 0.1 V to 14.5 V 150 μV
Guard Offset Voltage Drift2, 4 ΔVGOS/ΔT 0°C < TA < +125°C 0.18 1 μV/°C
−40°C < TA < 0°C 1.4 7 μV/°C
Output Impedance ZGOUT 1 kΩ
Output Voltage Range VGOS < 150 μV 0.1 14.5 V
−3 dB Bandwidth f−3 dB GUARD VIN = 10 mV rms, CL = 10 pF 5.5 MHz
1
These specifications represent the performance for 15 V ± 1 V power supplies. All specifications are measured at the worst case 16 V supply voltage.
2
The maximum specifications at −40°C < TA < +85°C and −40°C < TA < 0°C are guaranteed from characterization.
3
RH is relative humidity (see the Humidity Effects section for more information).
4
These typical specifications are equal to the average plus the standard deviation of the distribution from characterization.
5
The guard offset voltage is the voltage difference between the guard output and the noninverting input.

Rev. A | Page 8 of 50
Data Sheet ADA4530-1

ABSOLUTE MAXIMUM RATINGS

Table 4. Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
Parameter Rating
stress rating only; functional operation of the product at these
Supply Voltage 17 V
or any other conditions above those indicated in the operational
Input Voltage (V−) − 0.3 V to (V+) + 0.3 V
section of this specification is not implied. Operation beyond
Input Current1 10 mA
the maximum operating conditions for extended periods may
Differential Input Voltage ±0.7 V
affect product reliability.
Output Short-Circuit Duration to GND Indefinite
Storage Temperature Range −65°C to +150°C THERMAL RESISTANCE
Operating Temperature Range −40°C to +125°C θJA is specified for the worst case conditions, that is, a device
Junction Temperature Range −65°C to +150°C soldered in a circuit board for surface-mount packages using a
Lead Temperature (Soldering, 60 sec) 300°C standard 4-layer JEDEC board.
ESD
Human Body Model2 4 kV Table 5. Thermal Resistance
Field Induced Charged Device 1.25 kV Package Type θJA θJC Unit
Model (FICDM)3 8-Lead SOIC 122 41 °C/W
1
The input pins have clamp diodes to the power supply pins. Limit the input
current to 10 mA or less whenever input signals exceed the power supply ESD CAUTION
rail by 0.3 V.
2
Applicable Standard ESDA/JEDEC JS-001-2012.
3
Applicable Standard JESD22-C101-E (ESD FICDM standard of JEDEC).

Rev. A | Page 9 of 50
ADA4530-1 Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADA4530-1

+IN 1 8 –IN

GRD 2 7 GRD

IC 3 6 OUT

V– 4 5 V+

NOTES
1. IC = INTERNAL CONNECTION. THIS

13405-003
PIN MUST BE CONNECTED TO V–
OR LEFT UNCONNECTED.

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description
1 +IN Noninverting Input.
2 GRD Guard.
3 IC Internal Connection. This pin must be connected to V− or left unconnected.
4 V− Negative Supply Voltage.
5 V+ Positive Supply Voltage.
6 OUT Output.
7 GRD Guard.
8 −IN Inverting Input.

Rev. A | Page 10 of 50
Data Sheet ADA4530-1

TYPICAL PERFORMANCE CHARACTERISTICS

MAIN AMPLIFIER, DC PERFORMANCE
TA = 25°C, unless otherwise noted.
100 80
VSY = 4.5V VSY = 4.5V
90
VCM = VSY/2 60 VCM = VSY/2
590 CHANNELS 574 CHANNELS
80
x = 2.31µV
NUMBER OF AMPLIFIERS

σ = 5.48µV 40
70

60
20

VOS (µV)
50
0
40

30 –20

20
–40
10

0 –60

13405-007
13405-004
0
4
8
–8
–4

12
16
20
24
28
32
36
40
–40
–36
–32
–28
–24
–20
–16
–12

–50 –25 0 25 50 75 100 125

VOS (µV) TEMPERATURE (°C)

Figure 4. Input Offset Voltage Distribution, VSY = 4.5 V Figure 7. Input Offset Voltage (VOS) vs. Temperature, VSY = 4.5 V

100 80
VSY = 10V VSY = 10V
90
VCM = VSY/2 60 VCM = VSY/2
590 CHANNELS 574 CHANNELS
80
x = 2.27µV
NUMBER OF AMPLIFIERS

70 σ = 5.45µV 40

60
20
VOS (µV)

50
0
40

30 –20

20
–40
10

0 –60

13405-008
13405-005

–50 –25 0 25 50 75 100 125

0
4
8

40
–8
–4
–40
–36
–32
–28
–24
–20
–16
–12

12
16
20
24
28
32
36

VOS (µV) TEMPERATURE (°C)

Figure 5. Input Offset Voltage Distribution, VSY = 10 V Figure 8. Input Offset Voltage (VOS) vs. Temperature, VSY = 10 V

100 80
VSY = 16V VSY = 16V
90
VCM = VSY/2 60 VCM = VSY/2
590 CHANNELS 574 CHANNELS
80
x = 2.15µV
NUMBER OF AMPLIFIERS

70 σ = 5.47µV 40

60
20
VOS (µV)

50
0
40

30 –20

20
–40
10

0 –60
13405-009
13405-006
0
4
8
–8
–4

12
16
20
24
28
32
36
40
–40
–36
–32
–28
–24
–20
–16
–12

–50 –25 0 25 50 75 100 125

VOS (µV) TEMPERATURE (°C)

Figure 6. Input Offset Voltage Distribution, VSY = 16 V Figure 9. Input Offset Voltage (VOS) vs. Temperature, VSY = 16 V

Rev. A | Page 11 of 50
ADA4530-1 Data Sheet
120 120
VSY = 4.5V VSY = 4.5V
VCM = VSY/2 VCM = VSY/2
100 574 CHANNELS 100 574 CHANNELS
–40°C ≤ TA ≤ 0°C 0°C ≤ TA ≤ 125°C
NUMBER OF AMPLIFIERS

NUMBER OF AMPLIFIERS
x = –0.29µV/°C x = –0.025µV/°C
80 σ = 0.42µV/°C 80 σ = 0.107µV/°C

60 60

40 40

20 20

0 0

13405-010
0

0.4

2.8
–2.8

–2.4

–2.0

–1.6

0.8

1.2

1.6

2.0

2.4
–1.2

–0.8

–0.4

13405-013
–0.5 –0.4 –0.3 –0.2 –1.0 0 0.1 0.2 0.3 0.4 0.5
TCVOS (µV/°C) TCVOS (µV/°C)

Figure 10. Input Offset Voltage Drift Distribution, −40°C ≤ TA ≤ 0°C, VSY = 4.5 V Figure 13. Input Offset Voltage Drift Distribution, 0°C ≤ TA ≤ 125°C, VSY = 4.5 V

120 120
VSY = 10V VSY = 10V
VCM = VSY/2 VCM = VSY/2
100 574 CHANNELS 100 574 CHANNELS
–40°C ≤ TA ≤ 0°C 0°C ≤ TA ≤ 125°C

NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS

x = –0.29µV/°C x = –0.025µV/°C
80 σ = 0.42µV/°C 80 σ = 0.107µV/°C

60 60

40 40

20 20

0 0

13405-011
0

0.4

0.8

1.2

2.8
–2.8

–2.4

–2.0

–1.6

–1.2

–0.8

1.6

2.0

2.4
–0.4

–0.5 –0.4 –0.3 –0.2 –1.0 0 0.1 0.2 0.3 0.4 0.5
13405-014

TCVOS (µV/°C) TCVOS (µV/°C)

Figure 11. Input Offset Voltage Drift Distribution, −40°C ≤ TA ≤ 0°C, VSY = 10 V Figure 14. Input Offset Voltage Drift Distribution, 0°C ≤ TA ≤ 125°C, VSY = 10 V

120 120
VSY = 16V VSY = 16V
VCM = VSY/2 VCM = VSY/2
100 574 CHANNELS 100 574 CHANNELS
–40°C ≤ TA ≤ 0°C 0°C ≤ TA ≤ 125°C
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS

x = –0.29µV/°C x = –0.024µV/°C
80 σ = 0.41µV/°C 80 σ = 0.107µV/°C

60 60

40 40

20 20

0 0
13405-012

–0.5 –0.4 –0.3 –0.2 –1.0 0 0.1 0.2 0.3 0.4 0.5
2.8
–2.8

0.4

0.8

1.2

1.6

2.0

2.4
–2.4

–2.0

–1.6

–1.2

–0.8

–0.4

13405-015

TCVOS (µV/°C)
TCVOS (µV/°C)

Figure 12. Input Offset Voltage Drift Distribution, −40°C ≤ TA ≤ 0°C, VSY = 16 V Figure 15. Input Offset Voltage Drift Distribution, 0°C ≤ TA ≤ 125°C, VSY = 16 V

Rev. A | Page 12 of 50
Data Sheet ADA4530-1
60 10
VSY = 4.5V
590 CHANNELS 8
40 PREFERRED TA = 25°C
6

INPUT OFFSET VOLTAGE (µV)

COMMON-MODE
RANGE
4
20
2
VOS (µV)

0 0

–2
–20
–4

–6
–40
VSY = 10V
–8 27 CHANNELS
TA = 25°C
–60 –10

13405-219
13405-016
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 500 1000 1500 2000 2500 3000 3500 4000 4500
VCM (V) TIME (Hours)

Figure 16. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM), VSY = 4.5 V Figure 19. VOS Long-Term Drift

60 2.5
VSY = 10V
TA = 25°C
PREFERRED
40 COMMON-MODE 2.0

INPUT OFFSET VOLTAGE (µV)

RANGE

20
1.5
VOS (µV)

1.0
–20

0.5
–40 VSY = 10V
590 CHANNELS
TA = 25°C
–60 0

13405-220
13405-017

0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5
VCM (V) TIME AFTER POWER-ON (Minutes)

Figure 17. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM), Figure 20. VOS Warm-Up Time
VSY = 10 V

60 0
VSY = 10V
–20 ∆VCM = 400mV
PREFERRED
40 COMMON-MODE –40
RANGE
SMALL SIGNAL CMRR (dB)

–60 PREFERRED COMMON-MODE RANGE

20
–80
VOS (µV)

0 –100

–120
–20
–140

–160
–40 VSY = 16V
590 CHANNELS –180
TA = 25°C
–60 –200
13405-221
13405-018

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 1 2 3 4 5 6 7 8 9 10
VCM (V) VCM (V)

Figure 18. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM), Figure 21. Small Signal CMRR vs. Common-Mode Voltage
VSY = 16 V

Rev. A | Page 13 of 50
ADA4530-1 Data Sheet
20 20
VSY = 4.5V VSY = 4.5V
15 27 CHANNELS 15 27 CHANNELS
TA = 85°C TA = 85°C

10 PREFERRED 10 PREFERRED
COMMON-MODE COMMON-MODE
5 RANGE 5 RANGE

IB+ (fA)
IB– (fA)

0 0

–5 –5

–10 –10

–15 –15

–20 –20

13405-022

13405-025
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VCM (V) VCM (V)

Figure 22. Inverting Input Bias Current (IB−) vs. Common-Mode Voltage (VCM), Figure 25. Noninverting Input Bias Current (IB+) vs. Common-Mode Voltage (VCM),
VSY = 4.5 V, TA = 85°C VSY = 4.5 V, TA = 85°C

20 20
VSY = 10V VSY = 10V
15 27 CHANNELS 15 27 CHANNELS
TA = 85°C TA = 85°C

10 10
PREFERRED PREFERRED
5 COMMON-MODE RANGE 5 COMMON-MODE RANGE
IB+ (fA)
IB– (fA)

0 0

–5 –5

–10 –10

–15 –15

–20 –20
13405-023

13405-026
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
VCM (V) VCM (V)

Figure 23. Inverting Input Bias Current (IB−) vs. Common-Mode Voltage (VCM), Figure 26. Noninverting Input Bias Current (IB+) vs. Common-Mode Voltage (VCM),
VSY = 10 V, TA = 85°C VSY = 10 V, TA = 85°C

20 20
VSY = 16V VSY = 16V
15 27 CHANNELS 15 27 CHANNELS
TA = 85°C TA = 85°C

10 10
PREFERRED PREFERRED
COMMON-MODE RANGE COMMON-MODE RANGE
5 5
IB+ (fA)
IB– (fA)

0 0

–5 –5

–10 –10

–15 –15

–20 –20
13405-024

13405-027

0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16
VCM (V) VCM (V)

Figure 24. Inverting Input Bias Current (IB−) vs. Common-Mode Voltage (VCM), Figure 27. Noninverting Input Bias Current (IB+) vs. Common-Mode Voltage (VCM),
VSY = 16 V, TA = 85°C VSY = 16 V, TA = 85°C

Rev. A | Page 14 of 50
Data Sheet ADA4530-1
300 300
VSY = 4.5V VSY = 4.5V
27 CHANNELS 27 CHANNELS
200 TA = 125°C 200 TA = 125°C

PREFERRED PREFERRED
100 COMMON-MODE 100 COMMON-MODE
RANGE RANGE

IB+ (fA)
IB– (fA)

0 0

–100 –100

–200 –200

–300 –300

13405-028

13405-031
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VCM (V) VCM (V)

Figure 28. Inverting Input Bias Current (IB−) vs. Common-Mode Voltage (VCM), Figure 31. Noninverting Input Bias Current (IB+) vs. Common-Mode Voltage (VCM),
VSY = 4.5 V, TA = 125°C VSY = 4.5 V, TA = 125°C

300 300
VSY = 10V VSY = 10V
200 27 CHANNELS 200 27 CHANNELS
TA = 125°C TA = 125°C
100 PREFERRED 100 PREFERRED
COMMON-MODE RANGE COMMON-MODE RANGE
0 0

–100 IB+ (fA) –100

IB– (fA)

–200 –200

–300 –300

–400 –400

–500 –500

–600 –600
13405-029

13405-032
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
VCM (V) VCM (V)

Figure 29. Inverting Input Bias Current (IB−) vs. Common-Mode Voltage (VCM), Figure 32. Noninverting Input Bias Current (IB+) vs. Common-Mode Voltage (VCM),
VSY = 10 V, TA = 125°C VSY = 10 V, TA = 125°C

300 300
VSY = 16V VSY = 16V
27 CHANNELS 200 27 CHANNELS
200 TA = 125°C TA = 125°C
100
PREFERRED PREFERRED
100 COMMON-MODE RANGE 0 COMMON-MODE RANGE

–100
IB+ (fA)
IB– (fA)

0
–200

–100 –300

–400
–200
–500

–300 –600
13405-030

13405-033

0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16
VCM (V) VCM (V)

Figure 30. Inverting Input Bias Current (IB−) vs. Common-Mode Voltage (VCM), Figure 33. Noninverting Input Bias Current (IB+) vs. Common-Mode Voltage (VCM),
VSY = 16 V, TA = 125°C VSY = 16 V, TA = 125°C

Rev. A | Page 15 of 50
ADA4530-1 Data Sheet
1000 120
VSY = 4.5V –40°C TO +125°C LIMIT VSY = 10V
VCM = VSY/2 VCM = VSY/2
100 RH < 10% 100 590 CHANNELS
–40°C TO +85°C LIMIT TA = 125°C

NUMBER OF AMPLIFIERS
x = –40.69fA
80 σ = 24.54fA
10
IB (fA)

1 60

0.1 40
IB+
IB–

0.01 20

0.001 0

13405-234

13405-019
0 10 20 30 40 50 60 70 80 90 100 110 120 130 –250 –200 –150 –100 –50 0 50 100 150 200 250
TEMPERATURE (°C) IB– (fA)

Figure 34. Input Bias Current (IB) vs. Temperature, VSY = 4.5 V Figure 37. Inverting Input Bias Current Histogram, TA = 125C, VSY = 10 V

1000 120
VSY = 10V –40°C TO +125°C LIMIT VSY = 10V
VCM = VSY/2 VCM = VSY/2
100 RH < 10% 100 590 CHANNELS
–40°C TO +85°C LIMIT TA = 125°C

NUMBER OF AMPLIFIERS
x = –74.59fA
10 80 σ = 23.66fA
IB (fA)

1 60

0.1 IB+ 40
IB–

0.01 20

0.001 0
13405-235

13405-020
0 10 20 30 40 50 60 70 80 90 100 110 120 130 –250 –200 –150 –100 –50 0 50 100 150 200 250
TEMPERATURE (°C) IB+ (fA)

Figure 35. Input Bias Current (IB) vs. Temperature, VSY = 10 V Figure 38. Noninverting Input Bias Current Histogram, TA = 125°C, VSY = 10 V

1000 160
VSY = 16V –40°C TO +125°C LIMIT VSY = 10V
VCM = VSY/2 VCM = VSY/2
RH < 10% 140
100 590 CHANNELS
TA = 125°C
–40°C TO +85°C LIMIT 120
NUMBER OF AMPLIFIERS

x = 33.9fA
σ = 17.9fA
10
100
IB (fA)

1 80

60
0.1 IB+
IB– 40

0.01
20

0.001 0
13405-239
13405-236

0 10 20 30 40 50 60 70 80 90 100 110 120 130 –150 –120 –90 –60 –30 0 30 60 90 120 150
TEMPERATURE (°C) IOS (fA)

Figure 36. Input Bias Current (IB) vs. Temperature, VSY = 16 V Figure 39. Input Offset Current Histogram

Rev. A | Page 16 of 50
Data Sheet ADA4530-1

OUTPUT VOLTAGE HIGH (VOH) TO SUPPLY RAIL (V)

OUTPUT VOLTAGE LOW (VOL) TO SUPPLY RAIL (V)

10 10
–40°C –40°C
+25°C +25°C
+85°C +85°C
+125°C +125°C
1
VSY = 4.5V 1 VSY = 4.5V

0.1

0.1

0.01

0.01
0.001

0.0001 0.001

13405-037

13405-040
0.01 0.1 1 10 100 0.01 0.1 1 10 100
LOAD CURRENT (mA) LOAD CURRENT (mA)

Figure 40. Output Voltage Low (VOL) to Supply Rail vs. Load Current (ILOAD), Figure 43. Output Voltage High (VOH) to Supply Rail vs. Load Current (ILOAD),
VSY = 4.5 V VSY = 4.5 V
OUTPUT VOLTAGE LOW (VOL) TO SUPPLY RAIL (V)

OUTPUT VOLTAGE HIGH (VOH) TO SUPPLY RAIL (V)

10 10
–40°C –40°C
+25°C +25°C
+85°C +85°C
+125°C +125°C
1
VSY = 10V VSY = 10V
1

0.1

0.1

0.01

0.01
0.001

0.0001 0.001
13405-038

13405-041
0.01 0.1 1 10 100 0.01 0.1 1 10 100
LOAD CURRENT (mA) LOAD CURRENT (mA)
Figure 41 Output Voltage Low (VOL) to Supply Rail vs. Load Current (ILOAD), Figure 44. Output Voltage High (VOH) to Supply Rail vs. Load Current (ILOAD),
VSY = 10 V VSY = 10 V
OUTPUT VOLTAGE LOW (VOL) TO SUPPLY RAIL (V)

10
OUTPUT VOLTAGE HIGH (VOH) TO SUPPLY RAIL (V)

10
–40°C –40°C
+25°C +25°C
+85°C +85°C
+125°C +125°C
1
VSY = 16V VSY = 16V
1

0.1

0.1

0.01

0.01
0.001

0.0001 0.001
13405-039

13405-042

0.01 0.1 1 10 100 0.01 0.1 1 10 100

LOAD CURRENT (mA) LOAD CURRENT (mA)
Figure 42. Output Voltage Low (VOL) to Supply Rail vs. Load Current (ILOAD), Figure 45. Output Voltage High (VOH) to Supply Rail vs. Load Current (ILOAD),
VSY = 16 V VSY = 16 V

Rev. A | Page 17 of 50
ADA4530-1 Data Sheet
OUTPUT VOLTAGE LOW (VOL) TO SUPPLY RAIL (mV)

OUTPUT VOLTAGE HIGH (VOH) TO SUPPLY RAIL (mV)

100 100

90 VSY = 4.5V VSY = 4.5V

90

80 80

70 70
RL = 2kΩ
60 60

50 50

40 RL = 2kΩ
40

30 30

20 20 RL = 10kΩ
RL = 10kΩ
10 10

0 0

13405-043

13405-046
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 46. Output Voltage Low (VOL) to Supply Rail vs. Temperature, Figure 49. Output Voltage High (VOH) to Supply Rail vs. Temperature,
VSY = 4.5 V VSY = 4.5 V
OUTPUT VOLTAGE LOW (VOL) TO SUPPLY RAIL (mV)

225

OUTPUT VOLTAGE HIGH (VOH) TO SUPPLY RAIL (mV)

225
VSY = 10V
200 VSY = 10V
200
175
175
150 RL = 2kΩ
150
125
125
100
RL = 2kΩ 100
75
75
50
50 RL = 10kΩ
RL = 10kΩ
25
25
0
13405-044

–50 –25 0 25 50 75 100 125 0

13405-047
–50 –25 0 25 50 75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 47. Output Voltage Low (VOL) to Supply Rail vs. Temperature,
Figure 50. Output Voltage High (VOH) to Supply Rail vs. Temperature,
VSY = 10 V
VSY = 10 V
OUTPUT VOLTAGE LOW (VOL) TO SUPPLY RAIL (mV)

360
OUTPUT VOLTAGE HIGH (VOH) TO SUPPLY RAIL (mV)

360
330 VSY = 16V
330 VSY = 16V
300
300
270
270
240 RL = 2kΩ
240
210
210
180
180
150 RL = 2kΩ
150
120
120
90
90
60 RL = 10kΩ 60 RL = 10kΩ
30
30
0
13405-045

–50 –25 0 25 50 75 100 125 0

13405-048

–50 –25 0 25 50 75 100 125

TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 48. Output Voltage Low (VOL) to Supply Rail vs. Temperature,
Figure 51. Output Voltage High (VOH) to Supply Rail vs. Temperature,
VSY = 16 V
VSY = 16 V

Rev. A | Page 18 of 50
Data Sheet ADA4530-1
1.4 0
–40°C
+25°C VSY = 10V PSRR–
+85°C –20 ∆VCM = 400mV PSRR+
1.2 +125°C
–40
VCM = VSY/2

SMALL SIGNAL PSRR (dB)

ISY PER AMPLIFIER (mA)

1.0 –60
PREFERRED INPUT VOLTAGE
–80 RANGE
0.8
–100
0.6
–120

–140
0.4
–160
0.2
–180

0 –200

13405-049

13405-254
0 2 4 6 8 10 11 14 16 0 1 2 3 4 5 6 7 8 9 10
SUPPLY VOLTAGE (V) VCM (V)

Figure 52. Supply Current (ISY) per Amplifier vs. Supply Voltage (VSY) Figure 54. Small Signal PSRR vs. Common-Mode Voltage (VCM)

1.4
VCM = VSY/2

1.2
ISY PER AMPLIFIER (mA)

1.0

0.8

0.6

0.4

0.2 4.5V
10V
16V
0
13405-050

–50 –25 0 25 50 75 100 125

TEMPERATURE (°C)

Figure 53. Supply Current (ISY) per Amplifier vs. Temperature

Rev. A | Page 19 of 50
ADA4530-1 Data Sheet
MAIN AMPLIFIER, AC PERFORMANCE
VSY = 4.5 V to 16 V, data taken at VSY = 10 V, TA = 25°C, unless otherwise noted.
120 120 60
VSY = 10V
100 100 RL = 10kΩ
50 CL = 10pF
AV = +100
80 80
40

PHASE MARGIN (Degrees)

CLOSED-LOOP GAIN (dB)

OPEN-LOOP GAIN (dB)

60 60
30
40 40 AV = +10
20
20 20
10
0 0
10pF AV = +1
10pF 0
–20 100pF –20
100pF
–40 VSY = 10V –40 –10
RL = 10kΩ
–60 –60 –20

13405-055

13405-058
10k 100k 1M 10M 1k 10k 100k 1M 10M
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 55. Open-Loop Gain and Phase Margin vs. Frequency Figure 58. Closed-Loop Gain vs. Frequency

100 10k
VSY = 10V VSY = 10V
VCM = VSY/2 VCM = VSY/2
90
CLOSED-LOOP OUTPUT IMPEDANCE (Ω)
RL = 10kΩ 1k
80 CL = 10pF
100
70 AV = +10

10
60
CMRR (dB)

50 1 AV = +100

40 AV = +1
0.1
30
0.01
20
0.001
10

0 0.0001

13405-059
13405-056

10k 100k 1M 10M 100 1k 10k 100k 1M 10M

FREQUENCY (Hz) FREQUENCY (Hz)

Figure 56. CMRR vs. Frequency Figure 59. Closed-Loop Output Impedance vs. Frequency

60 60
VSY = 10V
PSSR+ VIN = 100mV p-p
PSSR–
AV = +1
50 VSY = 10V 50 RL = 10kΩ
VCM = VSY/2
RL = 10kΩ
CL = 10pF 40
40
OVERSHOOT (%)

OS–
PSRR (dB)

30 30

20 20
OS+

10 10

0 0
13405-060
13405-057

10k 100k 1M 10M 0 30 60 90 120 150 180 210 240 270

FREQUENCY (Hz) LOAD CAPACITANCE (pF)

Figure 57. PSRR vs. Frequency Figure 60. Small Signal Overshoot vs. Load Capacitance

Rev. A | Page 20 of 50
Data Sheet ADA4530-1
80 1.0

60 0.5

40
0
VSY = 4.5V
VOLTAGE (mV)

20 VIN = 100mV p-p VSY = 4.5V

VOLTAGE (V)
AV = +1 –0.5 VIN = 2.75V p-p
RL = 10kΩ AV = +1
0 CL = 10pF RL = 10kΩ
RS = 1kΩ –1.0 CL = 10pF
–20 RS = 1kΩ

–1.5
–40

–60 –2.0

13405-061

13405-064
–80 –2.5
TIME (2µs/DIV) TIME (2µs/DIV)

Figure 61. Small Signal Transient Response, VSY = 4.5 V Figure 64. Large Signal Transient Response, VSY = 4.5 V

80 6
VSY = 10V
VIN = 8.25V p-p
60 AV = +1
4
RL = 10kΩ
40 CL = 10pF
RS = 1kΩ
2
VOLTAGE (mV)

20

VOLTAGE (V)
VSY = 10V
VIN = 100mV p-p
0 0
AV = +1
RL = 10kΩ
–20 CL = 10pF
RS = 1kΩ –2
–40
–4
–60
13405-062

13405-065
–80 –6
TIME (2µs/DIV) TIME (5µs/DIV)

Figure 62. Small Signal Transient Response, VSY = 10 V Figure 65. Large Signal Transient Response, VSY = 10 V

80 10
VSY = 16V
8 VIN = 14.25V p-p
60 AV = +1
6 RL = 10kΩ
40 CL = 10pF
4 RS = 1kΩ
VOLTAGE (mV)

20
VOLTAGE (V)

2
VSY = 16V
VIN = 100mV p-p
0 0
AV = +1
RL = 10kΩ
–2
–20 CL = 10pF
RS = 1kΩ
–4
–40
–6
–60
–8
13405-063

13405-066

–80 –10
TIME (2µs/DIV) TIME (20µs/DIV)

Figure 63. Small Signal Transient Response, VSY = 16 V Figure 66. Large Signal Transient Response, VSY = 16 V

Rev. A | Page 21 of 50
ADA4530-1 Data Sheet
0.2 7 0.6 2.5

0.4 2.0
0 6 VIN
VSY = 4.5V 0.2 1.5
–0.2 VIN = 450mV 5

OUTPUT VOLTAGE (V)

0 1.0

OUTPUT VOLTAGE (V)

INPUT VOLTAGE (V)

AV = –10
INPUT VOLTAGE (V)

–0.4 RL = 10kΩ 4 –0.2 0.5

CL = 10pF
VIN
–0.4 0
–0.6 3
–0.6 –0.5
–0.8 VOUT 2
–0.8 VSY = 4.5V –1.0

–1.0 1 VIN = 400mV

–1.0 AV = –10 –1.5
RL = 10kΩ
–1.2 0 –1.2 VOUT CL = 10pF –2.0

13405-070
–1.4 –2.5

13405-067
–1.4 –1 TIME (2µs/DIV)
TIME (2µs/DIV)
Figure 67. Positive Overload Recovery, VSY = 4.5 V Figure 70. Negative Overload Recovery, VSY = 4.5 V

0.2 16 1.2 7
0 15 1.0
–0.2 14
VSY = 10V 0.8 5
–0.4 VIN = 900mV 13 VIN
–0.6 12 0.6
AV = –10
RL = 10kΩ 0.4 3
OUTPUT VOLTAGE (V)

–0.8 11

OUTPUT VOLTAGE (V)

INPUT VOLTAGE (V)

INPUT VOLTAGE (V)

–1.0 CL = 10pF 10 0.2
–1.2 VIN 9 0 1
–1.4 8
–0.2
–1.6 7
–1.8 VOUT 6 –0.4 –1
–2.0 5 –0.6
–2.2 4 –0.8 VSY = 10V –3
–2.4 3 VOUT VIN = 900mV
–1.0
–2.6 2 AV = –10
–1.2 RL = 10kΩ –5
–2.8 1
–1.4 CL = 10pF
–3.0 0
13405-068

13405-071
–3.2 –1 –1.6 –7
TIME (2µs/DIV) TIME (2µs/DIV)
Figure 68. Positive Overload Recovery, VSY = 10 V Figure 71. Negative Overload Recovery, VSY = 10 V

1 24 2 12

0 21
1 VIN 8
VSY = 16V
–1 VIN = 1.5V 18
AV = –10
OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

INPUT VOLTAGE (V)

INPUT VOLTAGE (V)

–2 RL = 10kΩ 15 0 4
VIN
CL = 10pF
–3 12
–1 0
VOUT
–4 9

–5 6 –2 –4
VSY = 16V
–6 3 VOUT VIN = 1.5V
–3 AV = –10 –8
RL = 10kΩ
–7 0
CL = 10pF
13405-069

13405-072

–8 –3 –4 –12
TIME (2µs/DIV) TIME (2µs/DIV)
Figure 69. Positive Overload Recovery, VSY = 16 V Figure 72. Negative Overload Recovery, VSY = 16 V

Rev. A | Page 22 of 50
Data Sheet ADA4530-1
INPUT VOLTAGES (250mV/DIV)

INPUT VOLTAGES (250mV/DIV)

VSY = 4.5V VSY = 4.5V
DUT AV = –1 DUT AV = –1
RL = 10kΩ RL = 10kΩ
CL = 10pF INPUT CL = 10pF

INPUT

OUTPUT VOLTAGE (5mV/DIV)

OUTPUT VOLTAGE (5mV/DIV)

OUTPUT
OUTPUT

ERROR BAND ERROR BAND

POST GAIN = 20

13405-273
POST GAIN = 20

13405-276
TIME (1µs/DIV) TIME (1µs/DIV)

Figure 73. Negative Settling Time to 0.1%, VSY = 4.5 V Figure 76. Positive Settling Time to 0.1%, VSY = 4.5 V

INPUT VOLTAGES (250mV/DIV)

INPUT VOLTAGES (250mV/DIV)

VSY = 10V
DUT AV = –1 INPUT
RL = 10kΩ
CL = 10pF

INPUT VSY = 10V

DUT AV = –1
OUTPUT VOLTAGE (5mV/DIV)

OUTPUT VOLTAGE (5mV/DIV)

RL = 10kΩ
CL = 10pF

OUTPUT
OUTPUT

ERROR BAND ERROR BAND

13405-274

POST GAIN = 20 POST GAIN = 20

13405-277
TIME (1µs/DIV) TIME (1µs/DIV)
Figure 74. Negative Settling Time to 0.1%, VSY = 10 V Figure 77. Positive Settling Time to 0.1%, VSY = 10 V
INPUT VOLTAGES (250mV/DIV)

INPUT VOLTAGES (250mV/DIV)

VSY = 16V
DUT AV = –1 INPUT
RL = 10kΩ
CL = 10pF

INPUT VSY = 16V

DUT AV = –1
OUTPUT VOLTAGE (5mV/DIV)

OUTPUT VOLTAGE (5mV/DIV)

RL = 10kΩ
CL = 10pF

OUTPUT
OUTPUT

ERROR BAND ERROR BAND

POST GAIN = 20 POST GAIN = 20
13405-275

13405-278

TIME (1µs/DIV) TIME (1µs/DIV)

Figure 75. Negative Settling Time to 0.1%, VSY = 16 V Figure 78. Positive Settling Time to 0.1%, VSY = 16 V

Rev. A | Page 23 of 50
ADA4530-1 Data Sheet
0.1 10
90kHz LOW-PASS FILTER VSY = 4.5V VSY = 4.5V
500kHz LOW-PASS FILTER AV = +1 AV = +1
RL = 10kΩ RL = 10kΩ
VIN = 0.5V rms f = 1kHz
1
THD + N (%)

THD + N (%)
0.01 0.1

0.01

90kHz LOW-PASS FILTER

500kHz LOW-PASS FILTER
0.001 0.001

13405-279

13405-282
10 100 1k 10k 100k 0.001 0.01 0.1 1
FREQUENCY (Hz) AMPLITUDE (V rms)

Figure 79. THD + N vs. Frequency, VSY = 4.5 V Figure 82. THD + N vs. Amplitude, VSY = 4.5 V

0.1 10
VSY = 10V VSY = 10V
90kHz LOW-PASS FILTER
500kHz LOW-PASS FILTER AV = +1 AV = +1
RL = 10kΩ RL = 10kΩ
VIN = 2V rms f = 1kHz
1

0.1
THD + N (%)

THD + N (%)

0.01

0.01

0.001
90kHz LOW-PASS FILTER
500kHz LOW-PASS FILTER
0.001 0.0001
13405-280

13405-283
10 100 1k 10k 100k 0.001 0.01 0.1 1 10
FREQUENCY (Hz) AMPLITUDE (V rms)

Figure 80. THD + N vs. Frequency, VSY = 10 V Figure 83. THD + N vs. Amplitude, VSY = 10 V

1 10
VSY = 16V VSY = 16V
90kHz LOW-PASS FILTER
500kHz LOW-PASS FILTER AV = +1 AV = +1
RL = 10kΩ RL = 10kΩ
VIN = 4.5V rms f = 1kHz
1
0.1
THD + N (%)

THD + N (%)

0.1

0.01
0.01

90kHz LOW-PASS FILTER

500kHz LOW-PASS FILTER
0.001 0.001
13405-281

13405-284

10 100 1k 10k 100k 0.001 0.01 0.1 1 10

FREQUENCY (Hz) AMPLITUDE (V rms)

Figure 81. THD + N vs. Frequency, VSY = 16 V Figure 84. THD + N vs. Amplitude, VSY = 16 V

Rev. A | Page 24 of 50
Data Sheet ADA4530-1
1000 3
VSY = 10V VSY = 10V
AV = +1 NOISE = 4µV p-p
RL = 10kΩ
VOLTAGE NOISE DENSITY (nV/√Hz)

CL = 10pF 2

INPUT REFERRED VOLTAGE (µV)

100 1

10 –1

–2

13405-286
1 –3

13405-285
0.1 1 10 100 1k 10k 100k 1M 10M 100M TIME (1s/DIV)
FREQUENCY (Hz)

Figure 85. Voltage Noise Density, VSY = 10 V Figure 86. 0.1 Hz to 10 Hz Noise

Rev. A | Page 25 of 50
ADA4530-1 Data Sheet
GUARD AMPLIFIER
TA = 25°C, unless otherwise noted.
120 100
VSY = 4.5V
VCM = VSY/2
100 590 CHANNELS
50
TA = 25°C
NUMBER OF AMPLIFIERS

x = –3.68µV
80 σ = 12.35µV
0

VOS (µV)
60

–50
40

–100 VSY = 4.5V

20
VCM = VSY/2
574 CHANNELS

0 –150

13405-094
13405-091
0
10
20
30
40
50
60
70
80
90
–90
–80
–70
–60
–50
–40
–30
–20
–10

100
–100

–50 –25 0 25 50 75 100 125

VOS (µV) TEMPERATURE (°C)

Figure 87. Input Offset Voltage Distribution, VSY = 4.5 V Figure 90. Input Offset Voltage (VOS) vs. Temperature, VSY = 4.5 V

120 100
VSY = 10V
VCM = VSY/2
100 590 CHANNELS 50
TA = 25°C
NUMBER OF AMPLIFIERS

x = –3.8µV
80 σ = 12.4µV
0
VOS (µV)

60

–50
40

–100 VSY = 10V

20 VCM = VSY/2
574 CHANNELS

0 –150

13405-095
13405-092
0
10
20
30
40
50
60
70
80
90
–90
–80
–70
–60
–50
–40
–30
–20
–10

100
–100

–50 –25 0 25 50 75 100 125

VOS (µV) TEMPERATURE (°C)

Figure 88. Input Offset Voltage Distribution, VSY = 10 V Figure 91. Input Offset Voltage (VOS) vs. Temperature, VSY = 10 V

120 100
VSY = 16V
VCM = VSY/2
100 590 CHANNELS
50
TA = 25°C
NUMBER OF AMPLIFIERS

x = –3.86µV
80 σ = 12.2µV
0
VOS (µV)

60

–50
40

–100 VSY = 16V

20
VCM = VSY/2
574 CHANNELS

0 –150
13405-096
13405-093
0
10
20
30
40
50
60
70
80
90
–90
–80
–70
–60
–50
–40
–30
–20
–10

100
–100

–50 –25 0 25 50 75 100 125

VOS (µV) TEMPERATURE (°C)

Figure 89. Input Offset Voltage Distribution, VSY = 16 V Figure 92. Input Offset Voltage (VOS) vs. Temperature, VSY = 16 V

Rev. A | Page 26 of 50
Data Sheet ADA4530-1
120 160
VSY = 4.5V VSY = 4.5V
VCM = VSY/2 140 VCM = VSY/2
100 574 CHANNELS 574 CHANNELS
–40°C ≤ TA ≤ 0°C 120 0°C ≤ TA ≤ 125°C
NUMBER OF AMPLIFIERS

NUMBER OF AMPLIFIERS
x = 0.26µV/°C x = 0.014µV/°C
80 σ = 1.14µV/°C σ = 0.168µV/°C
100

60 80

60
40
40
20
20

0 0

13405-097

13405-100
–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0

7
0

6
–7

–6

–5

–4

–3

–2

–1

TCVOS (µV/°C) TCVOS (µV/°C)

Figure 93. Input Offset Voltage Drift Distribution, −40°C ≤ TA ≤ 0°C, VSY = 4.5 V Figure 96. Input Offset Voltage Drift Distribution, 0°C ≤ TA ≤ 125°C, VSY = 4.5 V

120 160
VSY = 10V VSY = 10V
VCM = VSY/2 140 VCM = VSY/2
100 574 CHANNELS 574 CHANNELS
–40°C ≤ TA ≤ 0°C 120 0°C ≤ TA ≤ 125°C

NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS

x = 0.26µV/°C x = 0.017µV/°C
80 σ = 1.14µV/°C σ = 0.168µV/°C
100

60 80

60
40
40

20
20

0 0

13405-101
13405-098

–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0
7
0

6
–7

–6

–5

–4

–3

–2

–1

TCVOS (µV/°C) TCVOS (µV/°C)

Figure 94. Input Offset Voltage Drift Distribution, −40°C ≤ TA ≤ 0°C, VSY = 10 V Figure 97. Input Offset Voltage Drift Distribution, 0°C ≤ TA ≤ 125°C, VSY = 10 V

120 160
VSY = 16V VSY = 16V
VCM = VSY/2 140 VCM = VSY/2
100 574 CHANNELS 574 CHANNELS
–40°C ≤ TA ≤ 0°C 120 0°C ≤ TA ≤ 125°C
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS

x = 0.27µV/°C x = 0.02µV/°C
80 σ = 1.14µV/°C σ = 0.168µV/°C
100

60 80

60
40
40

20
20

0 0
13405-102
13405-099

–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0
7
0

6
–7

–6

–5

–4

–3

–2

–1

TCVOS (µV/°C) TCVOS (µV/°C)

Figure 95. Input Offset Voltage Drift Distribution, −40°C ≤ TA ≤ 0°C, VSY = 16 V Figure 98. Input Offset Voltage Drift Distribution, 0°C ≤ TA ≤ 125°C, VSY = 16 V

Rev. A | Page 27 of 50
ADA4530-1 Data Sheet

THEORY OF OPERATION
The ADA4530-1 is an operational amplifier specifically The guard pins are connected to the power supplies through
designed to interface with the extremely high impedance Diode D5 and Diode D6. During ESD events, the transient
sensors used in electrometer applications. current flows from the input pins through one of the antiparallel
A MOSFET input stage eliminates the gate leakage currents diodes and harmlessly into the supplies through one of the power
associated with legacy junction gate field effect transistor supply diodes. During normal operation, the guard buffer (BUF1)
(JFET) electrometers. The ADA4530-1 achieves extremely low forces the voltage across the antiparallel diodes to 0 V. Resistor R1
input bias currents while simultaneously providing robust shields the guard buffer from potentially large capacitances
protection against ESD damage. A unique ESD diode structure connected to the guard pins. Its value is nominally 1 kΩ.
provides protection while also allowing the diodes to be INPUT STAGE
guarded to minimize leakage currents to the input pins. The The input stage comprises a PMOS differential pair (M1, M2),
ADA4530-1 integrates the precision buffer used to guard folded cascode transistors (M5 to M12), and current source I1.
internal ESD diode leakage paths. The output of this guard
buffer is also connected to external pins to allow the user to The ADA4530-1 achieves its high performance specifications by
guard external components against leakage currents. using low voltage MOS devices for its differential inputs. These
low voltage MOS devices offer better 1/f noise and bandwidth
The input bias current is determined by the accuracy of the per unit current compared to high voltage devices. The input
guard voltage applied across the ESD diodes. The offset voltages stage is isolated from the high system voltages with proprietary
of the amplifier and guard buffer set the accuracy of the guard protection circuitry. This regulation circuitry protects the input
voltage and, therefore, the input bias current. devices from the high supply voltages in which the amplifier
The ADA4530-1 uses Analog Devices, Inc., DigiTrim™ can operate.
technology to achieve its superior performance. The proprietary high voltage protection circuitry in the
DigiTrim is used to trim the offset voltage of the amplifier and ADA4530-1 operates in such a way that it minimizes the
guard buffer to reject changes in the common-mode voltage, common-mode voltage changes seen by the amplifier input
power supply voltage, and temperature. This technique stage for most of the input common-mode range. This circuitry
significantly improves VOS, CMRR, PSRR, and TCVOS results in excellent disturbance rejection when operating in this
specifications. preferred input common-mode range. The performance
Figure 99 shows the simplified schematic of the ADA4530-1. benefits of operating within this preferred range are shown in
The amplifier uses a three-stage architecture with a fully the VOS vs. VCM graphs (see Figure 16 to Figure 18), the small
differential input stage to achieve excellent dc performance signal CMRR vs. VCM graph (see Figure 21), and the small signal
specifications. PSRR vs. VCM graph (see Figure 54).

ESD STRUCTURE These input devices are protected from large differential input
voltages by the antiparallel ESD diodes (D1 to D4). The diodes
The input ESD structure consists of Diode D1 to Diode D6. can conduct significant current when the differential voltage
The noninverting input is coupled to the guard pins (GRD) exceeds 700 mV. The user must ensure that the current flowing
by the D1 and D2 antiparallel diodes. The inverting input is into the input pins is limited to the absolute maximum of 10 mA.
coupled to the guard pins by the D3 and D4 antiparallel diodes.
V+

M19 M20
HIGH VOLTAGE PROTECTION
D5
I1 M11 M12
M17 M18

+IN M22
M1 M2
M9 M10 C2
D1 D2 C1
GRD
M3 M4
R1
OUT
V1
GRD BUF1 C3
D3 D4
M7 M8
–IN
M21
M15 M16
I2
M5 M6

D6
HIGH VOLTAGE PROTECTION M13 M14
13405-299

V–

Figure 99. Simplified Schematic

Rev. A | Page 28 of 50
Data Sheet ADA4530-1
GAIN STAGE The guard buffer uses a three-stage architecture similar to that
The second stage of the amplifier comprises an NMOS differen- of the amplifier. The guard buffer uses a rail-to-rail output stage
tial pair (M3, M4) and folded cascode transistors (M13 to M20). that allows the guard voltage to swing within 100 mV of the
The amplifier features nested Miller compensation (C1 to C3). supply rails. Because the guard buffer output follows the input
common-mode voltage, this output swing limits the effectiveness
OUTPUT STAGE of the guard buffer at low input common-mode voltages. This
The ADA4530-1 features a complementary common-source limit can be seen as a significant increase in input bias current
output stage consisting of the M21 and M22 transistors. These at low common-mode voltages in the input bias current vs.
transistors are configured in a Class AB topology and are biased common-mode voltage graphs (see Figure 22 to Figure 33). For
by the voltage source, V1. This topology allows the output this reason, it is not recommended to operate the circuit with an
voltage to be within tens of millivolts of the supply rails, input common-mode voltage of less than 100 mV from the V−
achieving a rail-to-rail output swing. The output voltage is supply rail.
limited by the output impedance of the transistors. The output The guard buffer output voltage can be degraded from excessive
voltage swing is a function of the load current and can be loading. The 1 kΩ output resistance adds 1 μV of guard voltage
estimated using the output voltage to the supply rail vs. load error per 1 nA of load current. It is possible to drive the guard
current graphs (see Figure 40 to Figure 45). offset voltage out of its specifications with a few tens of nano-
GUARD BUFFER amperes of load current. For this reason, it is not recommended
to drive anything except insulation resistance (see the Insulation
The guard buffer (BUF1) is a unity-gain amplifier that creates a
Resistance and Guarding section) with the guard buffer. If more
low impedance replica of the input common-mode voltage. The
drive strength is needed, the guard voltage can be buffered with
buffer input is connected to the noninverting input (IN+). The
a low offset, low input bias current op amp such as the
noninverting input voltage is approximately equal to the input
ADA4661-2.
common-mode voltage when the main amplifier feedback loop
is settled.

Rev. A | Page 29 of 50
ADA4530-1 Data Sheet

APPLICATIONS INFORMATION
The ADA4530-1 is a single, electrometer grade, CMOS Figure 100 shows the input and output waveforms of the
operational amplifier with femtoampere input bias current and ADA4530-1 configured as a unity-gain buffer with a supply
ultralow offset voltage. It operates over a wide supply voltage voltage of ±8 V. The output tracks the input voltage over the
range of 4.5 V (or ±2.25 V dual supply) to 16 V (or ±8 V dual entire range until the output voltage is clamped at its maximum
supply). It is a single-supply amplifier, where its input voltage output swing. Note that the amplifier still operates even when
range includes the lower supply rail and has a rail-to-rail output. the signal is outside the specified input voltage range (−8 V ≤
The ADA4530-1 also achieves a low offset voltage of ±40 μV IVR ≤ +6.5 V); this is due to the keep alive stage. Additionally, it
maximum and offset voltage drift of ±0.5 μV/C maximum. does not phase reverse. It is not recommended to apply an input
The ADA4530-1 has ultralow input bias currents that are voltage that is outside of the input voltage range.
10
production tested at 25°C and 125°C to ensure that the device VSY = ±8V
VIN = ±8.3V
meets its performance goals in a system application. An 8
AV = +1
integrated guard buffer is provided to minimize input pin 6 RL = 10kΩ
CL = 10pF
leakage in a printed circuit board (PCB) design, minimize 4
board component count, and enable ease of system design.

VOLTAGE (V)
2
The guard buffer output pins are also strategically placed next
0
to the input pins to enable easy routing of the guard ring and
to prevent coupling between the inputs, power supplies, and –2

the output pin. –4

–6 VIN
The ADA4530-1 is suited for applications requiring very low VOUT
input bias current and low offset voltage, including, but not –8

13405-300
limited to, preamplifier applications, for a wide variety of –10
current output transducers (photodiodes, photomultiplier TIME (200µs/DIV)

tubes), spectrometry, chromatography, and high impedance Figure 100. No Phase Reversal
buffering for chemical sensors. CAPACITIVE LOAD STABILITY
INPUT PROTECTION The ADA4530-1 can safely drive capacitive loads of up to
When either input of the ADA4530-1 exceeds one of the supply 250 pF in any configuration. As with most amplifiers, driving
rails by more than 300 mV, the input ESD diodes become larger capacitive loads than specified may cause excessive
forward-biased and large amounts of current begin to flow overshoot and ringing, or even oscillation. A heavy capacitive
through them. Without current limiting, this excessive fault load reduces phase margin and causes the amplifier frequency
current causes permanent damage to the device. If the inputs response to peak. Peaking corresponds to overshooting or
are expected to be subject to overvoltage conditions, insert a ringing in the time domain. Therefore, it is recommended that
resistor in series with each input to limit the input current to external compensation be used if the ADA4530-1 must drive a
10 mA maximum. However, consider the resistor thermal noise load exceeding 250 pF. This compensation is particularly
effect on the entire circuit. important in the unity-gain configuration, which is the worst
case for stability.
SINGLE-SUPPLY AND RAIL-TO-RAIL OUTPUT
A quick and easy way to stabilize the op amp for capacitive load
The ADA4530-1 is a single supply amplifier with an input
drive is by adding a series resistor, RISO, between the amplifier
voltage range (IVR) from V− to V+ − 1.5 V. The amplifier has a
output terminal and the load capacitance, as shown in Figure 101.
small keep alive input stage that allows it to function properly
RISO isolates the amplifier output and feedback network from
when the input common-mode voltage is greater than the
the capacitive load. However, with this compensation scheme,
specified IVR. This feature allows the ADA4530-1 to start up
the output impedance as seen by the load increases, and this
and recover quickly in certain types of circuits where the IVR is
reduces gain accuracy.
violated at power-up. The ac and dc performance of this keep
alive stage is poor; do not rely upon this keep alive stage for +VSY

normal use. RISO VOUT

VIN
ADA4530-1 CL
13405-201

–VSY

Figure 101. Stability Compensation with Isolating Resistor, RISO

Rev. A | Page 30 of 50
Data Sheet ADA4530-1
Figure 102 shows the phase margin of the ADA4530-1 with EMI REJECTION RATIO
different values of output isolating resistors and capacitive Circuit performance is often adversely affected by high frequency
loads. Figure 103 shows the frequency response with 1 nF electromagnetic interference (EMI). When the signal strength is
capacitive load and different isolating resistors. low and transmission lines are long, an op amp must accurately
80
VSY = 10V
amplify the input signals. However, all op amp pins—the
AV = +1 noninverting input, inverting input, positive supply, negative
supply, and output pins—are susceptible to EMI signals. These high
70
PHASE MARGIN (Degrees)

frequency signals are coupled into an op amp by various means,

such as conduction, near field radiation, or far field radiation. For
example, wires and PCB traces can act as antennas and pick up
60
high frequency EMI signals.
Amplifiers do not amplify EMI or RF signals due to their
50 relatively low bandwidth. However, due to the nonlinearities of
RISO = 301Ω the input devices, op amps can rectify these out of band signals.
RISO = 499Ω
RISO = 732Ω
When these high frequency signals are rectified, they appear as
40 a dc offset at the output.
100 1000 10000 13405-302
CAPACITIVE LOAD (pF) To describe the ability of the ADA4530-1 to perform as intended
Figure 102. Phase Margin vs. Load Capacitance with Various Output in the presence of electromagnetic energy, the electromagnetic
Isolating Resistors interference rejection ratio (EMIRR) of the noninverting pin is
100 100 specified in Table 1, Table 2, and Table 3 of the Specifications
VSY = 10V
AV = +1 section. A mathematical method of measuring EMIRR is
80 PHASE CL = 1nF 80
defined as follows:
60 60 EMIRR = 20log(VIN_PEAK/ΔVOS)
PHASE (Degrees)

Figure 104 shows the typical EMIRR vs. frequency performance

GAIN (dB)

40 GAIN 40
for each of the specified supply voltages.
20 20 120
VSY = 4.5V TO 16V
GAIN (RISO = 0Ω) 110
0 PHASE (RISO = 0Ω) 0
GAIN (RISO = 301Ω) 100

–20 PHASE (RISO = 301Ω) –20 90

GAIN (RISO = 732Ω)
PHASE (RISO = 732Ω) 80
EMIRR (dB)

–40 –40
13405-303

1k 10k 100k 1M 10M

70
FREQUENCY (Hz)
60
Figure 103. Frequency Response with CL = 1 nF and Various Isolating
Resistors 50

40 VSY = 4.5V
VSY = 10V
30 VSY = 16V

20
13405-304
10M 100M 1G 10G
FREQUENCY (Hz)

Figure 104. EMIRR vs. Frequency

Rev. A | Page 31 of 50
ADA4530-1 Data Sheet

HIGH IMPEDANCE MEASUREMENTS

The ADA4530-1 is designed to maximize the performance of very current through the feedback resistor. If all error sources are
high impedance circuits. Its performance advantages make it useful ignored, the output of the circuit is as follows:
for circuit impedances ranging from 100 MΩ to over 10 TΩ. VOUT = ISRCRF
Measurements of high impedance circuits are subject to a number V+ IRF
of error sources. General information about making measurements RF
RSHUNT
from high resistance sources can be found in the Low Level
CURRENT
Measurements Handbook, sixth edition (Keithley Instruments, SENSOR
ADA4530-1
Inc., 2004). A
8

The ADA4530-1 is typically used in two kinds of circuits: a buffer RIN IB –

ISRC RSRC 6
and a TIA. Buffer circuits are useful for measuring voltage output
sensors with high output resistance. Some example sensors include B
1
VOUT
VOS
pH probes and reference electrodes (RE) in coulometry control
loops. TIA circuits are useful for converting the signal from a

13405-311
current output sensor to an output voltage. Some example
sensors include photodiodes and ion chambers. Figure 106. Transimpedance Amplifier Circuit

The following sections describe some of the most important INPUT BIAS CURRENT
error sources when using the ADA4530-1 in these circuits. The input bias current of the amplifier is a major error source in
Simplified models with error sources are provided for the buffer high impedance electrometer circuits.
(see Figure 105) and the TIA (see Figure 106).
Like other semiconductor amplifiers, the input bias current of
The buffer circuit models the voltage output sensor as a voltage the ADA4530-1 has an exponential dependence on temperature.
source (VSRC) with an output resistance (RSRC). The voltage on The input bias current of the ADA4530-1 increases by a factor
the A terminal is sensed by Pin 1 of the ADA4530-1 in a of 2.5 for every 10°C increase in temperature. Refer to the input
noninverting gain configuration (or a unity-gain configuration). bias current vs. temperature graphs (see Figure 34 to Figure 36)
The B terminal is driven to a suitable reference voltage (signal for typical temperature performance. Notice that the exponen-
ground in this case). tial diode currents cease to be the dominate contributor to the
If all errors sources are ignored, the output of the circuit is as input bias current at temperatures below 60°C to 70°C. The
follows: residual 100 aA to 200 aA (aA = 10−18 A) bias currents are
dominated by other leakage paths that are highly sensitive to
 R 
VOUT  VSRC 1  F 

environmental conditions. These vanishingly small bias currents
 RS  require highly controlled laboratory conditions to measure.
VOLTAGE Most practical applications are dominated by other errors, and
SENSOR
ADA4530-1 the ADA4530-1 input bias current can be considered to be zero
A +IN
1 for temperatures less than 70°C. The input bias current of the
RIN IB + OUT ADA4530-1 can only be guaranteed to ±20 fA due to the
6 VOUT
RSRC RSHUNT measurement limitations of a production environment even
–IN
8
RF
though the achievable input bias currents are more than an
VSRC VOS order of magnitude lower.
The input bias current affects the buffer circuit by loading down the
RS voltage sensor. The input bias current is forced to flow through the
13405-310

output resistance of the sensor, which creates an error voltage.

B
VERR = IB+(RSRC)
Figure 105. Voltage Buffer Circuit
The magnitude of this voltage error can be significant with very
The TIA circuit models the current output sensor as a current
high impedance sensors operating at high temperature. For
source (ISRC) with a shunt resistance (RSRC). The current from
example, the input bias current can generate a maximum voltage
the A terminal is connected to the inverting input pin of the
error of 25 mV from a 100 GΩ sensor operating at 125°C.
ADA4530-1 and the feedback resistor (RF). The B terminal and
the noninverting input of the amplifier are driven to a suitable The input bias current affects the TIA circuit by summing
reference voltage (signal ground in this case). The negative together with the sensor current. Both of these currents flow
feedback of the circuit suppresses any voltage changes at the through the feedback resistor to generate the output voltage as
A terminal. This suppression is accomplished by forcing all follows:
VOUT = (ISRC + IB−)RF
Rev. A | Page 32 of 50
Data Sheet ADA4530-1
The magnitude of the input bias current limits how small of a equal to a few fA, which is the same magnitude as the input bias
signal current may be resolved accurately. For example, if the current itself. These uncertainties make it impossible to calcu-
acceptable error level is 10%, the minimum measurable signal late input resistances higher than a few hundred teraohms.
current is 2.25 pA for a circuit operating at 125°C. The input resistance affects the buffer circuit by loading down
ISRC = IB−(1/err – 1) the voltage sensor. This resistance acts as a voltage divider so
where err is the error level. the voltage measured by the amplifier is some fraction of the
unloaded voltage of the sensor. This voltage drop is calculated
2.25 pA  250 fA  1
1 as follows:
 0.1 
RIN
VA  VSRC
INPUT RESISTANCE RIN  RSRC
The input resistance of the amplifier is another error source that Consider the previous example of a 100 GΩ sensor operating at
must be considered. Input resistance typically has two compo- 125°C. The 100 TΩ input resistance causes the measured
nents: differential and common mode. The differential input voltage to equal 99.9% of the actual voltage, a 0.1% gain error.
resistance is suppressed by the negative feedback of the circuit.
The ADA4530-1 has enough gain that the differential input The input resistance has much less of an effect on the TIA
resistance is much too large to measure. The common-mode circuit. The input common-mode voltage does not change in
input resistance (hereafter referred to as input resistance) is a this circuit; therefore, the error created is vanishingly small.
more important error source. The input resistance affects the noise gain of the circuit, which
changes the input offset voltage error (see the Photodiode
The input resistance is equal to the change in input bias current Interface section for more information).
relative to the change in input voltage. This change is not caused
by a physical resistance inside the ADA4530-1; it is the result of INPUT OFFSET VOLTAGE
a complex relationship between the accuracy of the guard voltage The input offset voltage of the amplifier affects the buffer circuit
across the ESD structures and the input common-mode voltage; by adding directly to the voltage output of the sensor. This error
that is, the input resistance changes with common mode voltage. It is typically much smaller than other errors.
is also possible for the input resistance to be negative. Negative
The input offset voltage affects the TIA circuit in a different
input resistance means the input bias current decreases as the
manner. The burden voltage of the TIA is equal to the input
common-mode voltage increases.
offset voltage. This burden voltage appears between the A and B
The input resistance, RIN, can be approximated by calculating terminals. An error current is created by applying this burden
the slope of the input bias current vs. common-mode voltage voltage across the sensor shunt resistance. For sensors with low
graphs (see Figure 22 to Figure 33). For example, the noninverting output resistances such as photodiodes, this error can be
input resistance can be calculated at 125°C from Figure 32. Note significant. Consider a sensor with a 1 GΩ output resistance.
that the input bias current changes by approximately 20 fA for The 50 μV maximum offset voltage of the ADA4530-1 creates a
common-mode voltages from 4 V to 6 V. 50 fA error current.
VCM INSULATION RESISTANCE
RIN 
I B  The ADA4530-1 has such low input bias current and such high
2V input resistance that the insulation resistance of the materials
R IN   100 TΩ that are used to construct the circuit is often the largest error
20 fA
source. Any insulators with finite resistance that come in
The slope of the curves in the input bias current vs. common- contact with the high impedance conductor contribute to the
mode voltage graphs increases rapidly outside the preferred error current. Some examples include the printed circuit board
common-mode range (see Figure 22 to Figure 33). The input (PCB) laminate material, cable, and connector insulation.
resistance drops rapidly outside this range. This drop in input
The physical insulation resistance is distributed across the
resistance must be considered before operating these circuits
entire contact surface of the high impedance conductor, and it
with input voltages close to the V− power supply.
may end at several different conductors at different potentials. It
Like the input bias current, the input resistance has a strong is useful to make a simple model where all of these resistance
temperature dependence. At lower temperatures, the amplifier paths are lumped into a single resistor. This lumped element is
input resistance is so high that it is dominated by other error shown as RSHUNT in the voltage buffer circuit (see Figure 105).
sources. It is important to recognize the limitations of calculating
The insulation resistance affects the buffer circuit in the same
input resistance at lower temperatures. Measurement uncertain-
way as the amplifier input resistance. This resistance acts as a
ties make it difficult to accurately calculate the ΔIB term. Consider
voltage divider so that the voltage measured by the amplifier is
the 85°C input bias current vs. common-mode voltage graphs
some fraction of the unloaded voltage of the sensor. This error
(see Figure 22 to Figure 27); the measurement uncertainties are
is significant because it is very difficult to maintain high
Rev. A | Page 33 of 50
ADA4530-1 Data Sheet
insulation resistance values in glass epoxy (such as FR-4) PCB In practice, the voltage across RSHUNT1 cannot be 0 V, the guard
materials. Resistance values of 10 TΩ to 100 TΩ are achievable. buffer offset voltage contributes to the difference in voltage
A 10 TΩ insulation resistance creates a 1% error with the 100 GΩ potential between the A node and VGRD node. For the
sensor used in previous examples. Insulation resistance does not ADA4530-1, this offset voltage is trimmed to provide offsets
have an exponential temperature dependence like the amplifier less than 100 μV when the input common-mode voltage is 1.5 V
errors previously discussed in the Input Bias Current section and from the supply rails. The guard buffer offset voltage and drift
the Input Resistance section, which makes insulation resistance are specified in Table 1, Table 2, and Table 3.
the dominate error source at lower temperatures (less than 70°C). For example, assume that the voltage sensor produces an output
The effect on the insulation resistance on the TIA circuit depends of 1 V. Without guarding, the 10 TΩ insulation resistance
on the leakage path. The insulation resistance between the A creates an error current of 100 fA. With the guard, the voltage
terminal and B terminal of the current sensor affects the circuit across the insulation resistance is limited to 100 μV. The guard
in the same way as the amplifier input resistance. This error is limits the error current to 0.01 fA. In this example, the guard
extremely small because the voltage across the insulation is reduces the error by a factor of 104 to an insignificant level.
equal to the offset voltage of the amplifier. A much more VOLTAGE
SENSOR
significant error is created from insulation paths to conductors ADA4530-1
A
with significantly different potentials. This type of leakage path 1

is shown as lumped element, RSHUNT, in the TIA circuit (see RSHUNT1 2

VGRD 6 VOUT
Figure 106). In this example, the leakage path is created from RSRC 7

the positive supply voltage (V+) to the A terminal. If the 8

RF
RSHUNT2
positive supply voltage is 5 V relative to signal ground, 500 fA VSRC

flows through the insulation resistance of 10 TΩ. This large RS

error dominates the amplifier input bias current and input

13405-313
B
resistance errors over the entire temperature range.
Leakage paths to high voltages can also affect the buffer circuit Figure 107. Voltage Buffer Circuit with Guard
with equally ruinous results. DIELECTRIC RELAXATION
GUARDING Dielectric relaxation (also known as dielectric absorption or
High source impedances and low error requirements can create soakage) is a property of all insulating materials that can limit
insulation resistance requirements that are unrealistically high. the performance of electrometer circuits that need to settle to a
Fortunately, a technique called guarding can reduce these few femtoamperes.
requirements to a reasonable level. The concept of guarding is Dielectric relaxation is the delay in polarization of the dielectric
to surround the high impedance conductor with another molecules in response to a changing electric field. This delay is
conductor (guard) that is driven to the same voltage potential. If a property of all insulating materials. The magnitude and the
there is no voltage across the insulation resistance (between time constant of the delay depend on the specific dielectric
high impedance conductor and guard), there cannot be any material. The delays in some materials can be minutes or even
current flowing through it. hours.
The ADA4530-1 uses guarding techniques internally, and it has Dielectric relaxation is a problem for electrometer circuits
a very high performance guard buffer integrated. The output of because small displacement currents flow through the insulator
this buffer is made available externally to simplify the in response to the polarization of the molecules. Delays in
implementation of guarding at the circuit level. polarization cause delays in the dissipation of these currents,
The voltage buffer circuit (see Figure 105) has been modified to which can dominate the settling time in these circuits.
show the implementation of the guard (see Figure 107). In this In the context of capacitors, dielectric relaxation is called
model, a conductor (VGRD) is added, and it completely separates dielectric absorption. Capacitors are specified with a test that
the high impedance (A) node from the low impedance (B) node measures the residual open-circuit voltage after a specific
at a different voltage. The insulation resistance is modeled as charge/discharge cycle. For electrometer circuits, it is more
two resistances: all of the insulation between the A conductor useful to consider the short-circuit currents produced from step
and the guard conductor (RSHUNT1), and all of the insulation changes in a test voltage.
between the guard conductor and the B conductor (RSHUNT2).
A simple lumped circuit model of an insulator is connected to
The ADA4530-1 guard buffer then drives this guard conductor
the test voltage source (see Figure 108). The majority of the
(through Pin 2 and Pin 7) to the A terminal voltage. If the A
dielectric polarizes instantly; this is modeled as Capacitor C1. A
node and VGRD node are exactly the same voltage, no current
small percentage of the dielectric polarizes slowly with a time
flows through the insulation resistance, RSHUNT1.
constant of τ2, modeled as Capacitor C2 and Resistor R2.

Rev. A | Page 34 of 50
Data Sheet ADA4530-1
125 20
The size of C2 reflects the proportion of slow molecules. The
VSRC
size depends on the material but it is typically 100 to 10,000 100 ISRC 16

times smaller than C1. The size of R2 sets the time constant. 75 12

APPLIED VOLTAGE (V)

τ2 = R2 × C2 50 8

CURRENT (fA)
INSULATOR 25 4
MODEL
RS 0 0

–25 –4
ISRC R2
–50 –8
C1 C2
VSRC –75 –12

13405-326
–100 –16

–125 –20

13405-315
Figure 108. Dielectric Relaxation Model Test Circuit 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
ELAPSED TIME (Hours)

Figure 110. Glass Epoxy Dielectric Relaxation Performance

VSRC
An alternative PCB laminate to consider is Rogers 4350B.
Rogers 4350B is a ceramic laminate designed for RF/microwave
1 = RS × C1 circuits. Rogers 4350B is compatible with standard PCB produc-
tion techniques and is widely available. The measurement
2 = R2 × C2
ISRC results for the Rogers 4350B material are shown in Figure 111.
13405-314

This material requires less than 20 sec to dissipate the dielectric

TIME
relaxation current to less than 1 fA.
Figure 109. Step Response of Dielectric Relaxation Model
Based on its superior performance, it is recommended to use
The current step response (ISRC) of the insulator to a voltage step
Rogers 4350B laminates with the ADA4530-1 in the highest
is shown in Figure 108. A large initial current charges Capacitor C1
performance applications. All of the critical characterization
with a fast time constant. This time constant, τ1, equals the source
measurements of the ADA4530-1 are taken using Rogers 4350B.
resistance RS × C1 (see Figure 109). Long after Capacitor C1 is
125 10
charged, a much smaller current continues to flow, which charges VSRC
Capacitor C2. The time constant of charging is not affected by 100 ISRC 8

the external circuitry; it depends only on the material proper- 75 6

ties of the insulator. The magnitude of the current depends on

APPLIED VOLTAGE (V)

50 4
the magnitude of the voltage change across the insulator.

CURRENT (fA)
25 2

The dielectric relaxation performance was measured for a 0 0

variety of PCB laminates using the test circuit in Figure 108. –25 –2
An electrometer grade source measurement unit (SMU),
–50 –4
Keithley 6430, applies a ±100 V test stimulus and measures the
–75 –6
resulting current. The large alternating polarity test voltage
distinguishes the small dielectric relaxation current from the –100 –8

input offset current of the SMU. –125 –10

13405-316
0 20 40 60 80 100 120 140 160 180 200
The first PCB laminate tested is the industry-standard FR-4 ELAPSED TIME (Seconds)
glass epoxy. The measurement results are shown in Figure 110. Figure 111. Rogers 4350B Dielectric Relaxation Performance
The glass epoxy laminate requires 1 hour to dissipate the
dielectric relaxation current to less than 10 fA. This result shows
that glass epoxy laminates are unsuitable for the highest
performance electrometer circuits.

Rev. A | Page 35 of 50
ADA4530-1 Data Sheet
HUMIDITY EFFECTS on Rogers 4350B PCBs (glass epoxy boards have poor humidity
The insulation resistance of the materials used to construct absorption properties).
circuits is sensitive to moisture. At lower temperatures (<70°C) Figure 112 shows the effective input bias current vs. relative
the insulation resistance creates more significant leakage humidity for seven characterization units. Figure 112 is plotted
current errors than the amplifier itself. This means that the with a split log axis to effectively show the magnitude and polarity
relative humidity of the air is the most important error source at of the bias current. The magnitude of the leakage currents
lower temperatures. The dependence on humidity is evident in changes by more than factor of 100 across the relative humidity
the input bias current vs. temperature graphs (see Figure 34 to span from 5% to 80%. The effective bias current is much less
Figure 36). There is significant deviation in the low temperature than 1 fA for typical conditioned environments (RH < 50%).
measurements due to the difficulty maintaining a consistently 100
VSY = 10V
low relative humidity at low temperatures. 10
TA = 25°C
VCM = VSY/2
To evaluate the humidity sensitivity of insulation resistance, 7 UNITS
1
there are two mechanisms which must be considered:
0.1
adsorption and absorption.

IB (fA)
Adsorption is a process where thin films of molecules adhere to
the surface of a material. Water molecules are subject to this –0.1

process. The magnitude of the effect depends on the insulating –1

material and the relative humidity. Thin films of moisture are
–10
conductive, and they act as leakage resistances in parallel with
the insulation resistance of the material. Because this is a –100

surface effect, guard ring techniques are effective at reducing it. –1000

13405-112
0 20 40 60 80
Absorption is a process where molecules enter the bulk of a RELATIVE HUMIDITY (%)
material. Water molecules can diffuse into a material and affect Figure 112. Effective Input Bias Current vs. Relative Humidity
the bulk conductivity of that material. Because the leakage paths
The magnitude of the effective input bias current becomes very
are through the bulk of the material, guard rings are not
sensitive to the relative humidity at higher humidity levels
effective at reducing it.
(>60%). Some of the units show an exponential dependence on
It is not possible to completely guard all the leakage paths: bulk humidity (see the blue curve in Figure 112). Other units show a
or surface. A relevant example of this limitation is the molding less predictable dependence; the leakage current magnitude
compound of the SOIC package housing the ADA4530-1. increases rapidly, but the polarity can change. The net leakage
Surface and bulk paths exist from the input pins to all other current is the sum of the currents sourced from higher voltages
pins of the package. The nature of the resulting current depends (like V+) with the currents sunk by lower voltages (like V−). As
on the specific leakage path: paths to V+ increase the bias the humidity changes, the relative magnitudes of each of these
current flowing out of the amplifier, paths to V− increase the leakage paths can change, which can result in changes in the
bias current flowing into the amplifier, and paths to VOUT lower polarity of the leakage current (see the red and green curves in
the effective feedback resistance in TIA circuits. Figure 112).
Consider the example of a circuit powered from ±5 V power The response time of these leakage currents depends on the
supplies with an input common-mode voltage of 0 V. Assume physical process that causes them. Because adsorption is a
that all of the leakage resistance between the input and V+ is surface effect, the film thickness rapidly achieves equilibrium
effectively 100 TΩ. This resistance creates a current equal to with changes in the relative humidity of the air. Because
50 fA flowing from V+. Assume that the leakage resistance absorption is a bulk diffusion process, it is very slow compared
between the input and V− is effectively 250 TΩ. This resistance to the adsorption process.
creates a current equal to 20 fA flowing to V−. The net current
These widely different time constants mean that the effective
equals −30 fA flowing out of the input pin.
input bias current responds quickly to a step change in relative
All of these leakage currents can be combined with the humidity, but has a very long settling time. The step response of
amplifier input bias current and treated as an effective input one amplifier to a 50% to 60% relative humidity change is
bias current. The effective input bias current sensitivity to shown in Figure 113. The high frequency response of the initial
relative humidity of the ADA4530-1 is characterized for several humidity step (and the overshoot recovery) is on the order of
units. The test amplifiers are configured in TIA and unity buffer seconds to tens of seconds. Complete settling takes over a week
circuits with 100 GΩ, hermetically sealed resistors (RX-1M1009FE) as the moisture slowly diffuses through the PCB insulation and
as the feedback and source resistors, respectively. These glass package molding compound. Note that each data point in
bodied resistors have a silicone coating (glass has poor humidity Figure 112 was taken after one week of settling time.
adsorption properties). The ADA4530-1 amplifiers are mounted

Rev. A | Page 36 of 50
Data Sheet ADA4530-1
In practical applications, the relative humidity of the air changes In summary, the ADA4530-1 can be designed using the specified
rapidly with daily and seasonal variations. The effective input performance for normal laboratory (<60%) relative humidity
bias current response to these humidity changes has two parts. conditions. In applications that must operate in uncontrolled or
The response due to the adsorption process follows the rapid high humidity environments, some additional derating of the
changes immediately. The response due to the absorption input bias current is prudent. Characterize the amount of derating
process low-pass filters the humidity changes. This low-pass on a per product basis because the net leakage depends on the
response causes the effective input bias current to have long- material types and physical dimensions of the insulators.
term memory of the relative humidity fluctuations.
CONTAMINATION
In this environment, measurements of the effective input bias The effective insulation resistance of an electrometer circuit can
current appear to drift with time because the leakage currents be substantially degraded if the insulators are contaminated.
depend on the relative humidity for the previous week. This Solder flux, body oils, dust, and dirt are all possible sources of
long-term memory due to the absorption process may need to contamination. Some of these contaminants form a parallel
be taken in account in certain circumstances (that is, long-term leakage path across the surface of the existing insulator effec-
product storage in an unconditioned high humidity environ- tively lowering the insulation resistance. Guarding techniques
ment prior to use). help to suppress these effects.
The rapid adsorption response can change the effective bias The effects are more severe when the source of contamination
current in response to local fluctuations in humidity. These contains ionic compounds. In the presence of humidity, these
current fluctuations can be much larger than the low frequency contaminates act as an electrolyte, which can form a weak
current noise of the amplifier and thermal noise of the resistors. battery. Flux residue and body oils are particularly effective at
The sensitive circuitry can be isolated from these local humidity creating these parasitic batteries.
fluctuations by restricting the airflow around the circuitry with
an air baffle. Electrostatic shielding added to reduce interfer- As an example, the PCB insulation between two high imped-
ence can also function as an air baffle. Remove or reduce the ance nodes was purposefully contaminated with a 3 mm drop of
sources of humidity fluctuations whenever possible. Avoid rosin mildly activated (RMA) type solder flux. This sample was
breathing on the high impedance circuitry, for example. dried and allowed to stabilize in laboratory conditions (25°C,
6 70
40% RH) for several days. After this time, the voltage vs. current
relationship was measured with an electrometer grade SMU
4 60 (see Figure 114).
VSY = 10V
TA = 25°C This contamination formed a weak battery with an open circuit
RELATIVE HUMIDITY (%)

2 50
VCM = VSY/2
voltage (VBATT) of 15 mV and an output resistance (RBATT) of
0 40 300 GΩ. This sort of contamination is disastrous in electrome-
IB (fA)

ter circuits because guarding techniques cannot suppress it. A

–2 30 simplified model is made with the contamination battery applied
across the A terminal and B terminal of a TIA circuit (see
–4 20
Figure 115). The A terminal and B terminal are both driven to
–6 10 the same voltage, which creates an error current (IBATT) because
RELATIVE HUMIDITY the open circuit battery voltage is dropped across the output
IB
–8 0 resistance as follows:
13405-402

0 25 50 75 100 125 150 175

ELAPSED TIME (Hours) IBATT = VBATT ÷ RBATT
Figure 113. Effective Input Bias Current Transient Response to Humidity Step
All of this battery current flows through the feedback resistance,
It is important to note that all electrometer circuits are subject where it is summed with the signal and other error currents in
to humidity effects. The legacy circuits constructed with TO-99 the circuit. The error current in this example is 50 fA. The battery
packages using air wiring techniques have insulator leakage paths characteristics are subject to the environmental conditions;
such as the epoxy between the pins and the Teflon® standoffs used therefore, the error current drifts with time, temperature, and
to support the air wired components. The input bias currents of humidity.
legacy amplifiers are high enough to mask the humidity effects.

Rev. A | Page 37 of 50
ADA4530-1 Data Sheet
400
CLEANING AND HANDLING
300 The contamination described in the Contamination section can
200
usually be removed by an appropriate cleaning process. Solvents
OUTPUT CURRENT (fA)

like isopropyl alcohol (IPA) are effective at removing the residue

100 from solder fluxes and body oils. Use high purity cleanroom
0
grade solvents to ensure that there is no additional contamina-
tion from the solvent itself.
–100
Insulators that are severely contaminated benefit from mechani-
–200 cal abrasion in addition to the solvent. Ultrasonic cleaners are
–300
highly effective. Scrubbing the area around the high impedance
insulators with an acid brush also works. Flush the insulators
–400 with a final wash of fresh IPA to remove any contaminants

13405-319
–100 –80 –60 –40 –20 0 20 40 60 80 100
APPLIED VOLTAGE (mV) suspended in the solvent.
Figure 114. Current to Voltage Response of RMA Contaminated Insulation The residual moisture must be allowed to completely evaporate
IBATT before the insulator can be used. This evaporation may take
RF
many hours at room temperature; the process can be accelerated
by baking the insulators in an oven at elevated temperature.
ADA4530-1 For detailed cleaning and handling procedures, refer to the
A 8
RBATT
ADA4530-1R-EBZ User Guide.
BATTERY 6
MODEL V SOLDER PASTE SELECTION
BATT

B 1
VOUT Solder paste selection can drastically impact the performance of
the board if not cleaned properly. Solder flux residue on a PCB
13405-312

degrades the low IB performance of the amplifier. An experiment

was performed to evaluate the cleaning procedure for different
Figure 115. TIA Circuit with Contamination Battery
solder paste types. Table 7 shows the result of the experiment.
The recommended cleaning procedure column lists the times
required to restore the effective input bias currents to less than
1 fA. The suggested solder paste of choice is the RMA type.

Table 7. Recommended Cleaning Procedures for Different Solder Paste Material

Solder Paste Type Solder Paste Part Number Recommended Cleaning Procedure1
RMA AIM RMA258-15R 15 min clean time in an ultrasonic cleaner with fresh IPA, followed by 1.5 hours
of bake time at 125°C
Water Soluble SAC305 Shenmao 1.5 hours clean time in an ultrasonic cleaner with fresh IPA, followed by 1.5 hours
of bake time at 125°C
No Clean SAC 305 AMTECH LF4300 3 hours clean time in an ultrasonic cleaner with fresh IPA, followed by 3 hours of
bake time at 125°C
1
Bake time was not optimized and was set equal to the cleaning time.

Rev. A | Page 38 of 50
Data Sheet ADA4530-1

CURRENT NOISE CONSIDERATIONS

The current noise from an amplifier input pin is important The output referred voltage NSD, VNRTO, is sampled by the SR785
when it flows through an impedance and generates a voltage high performance dynamic signal analyzer (DSA) and is equal
noise. If the current noise and impedance are large enough, the to the root-sum-square of the amplifier current noise multiplied by
resulting voltage noise can dominate the other noise sources in RF, the resistor thermal noise, and amplifier voltage noise.
the circuit such as the voltage noise of the resistors and amplifier. VNRTO = √((IN−RF)2 + 4kTRF + VN2)
For an electrometer amplifier such as the ADA4530-1, the
typical circuit impedances are so large that the current noise of where:
the amplifier can be the most important noise source. IN− is the amplifier inverting current noise.
4kTRF is the resistor thermal noise.
To measure current noise, it is necessary to flow the noise VN2 is the amplifier voltage noise.
current through a test impedance large enough that the
resulting noise voltage is larger than the other noise voltages in Calculate the current noise of the amplifier from VNRTO as follows:
the circuit. Practically, this test impedance is usually a resistor. VNRTO 2  4kTRF  VN 2
All resistors have their own thermal noise. The value of thermal IN   (1)
RF
noise is usually presented as an output referred voltage noise
spectral density (NSD), VNRTO. For Equation 1 to be valid, the measured noise must be somewhat
VNRTO = √(4kTR) larger than the resistor thermal noise plus the amplifier voltage
noise. In practice, ensure that the resistor current noise is less
where: than or equal to the amplifier current noise. For example, if the
k is Boltzmann’s constant. amplifier noise is expected to be 2 fA/√Hz, use a value of RF that
T is the temperature in Kelvin. is at least 10 GΩ, according to Table 8.
R is the resistance value.
The amplifier voltage noise is not a concern at most frequencies
The resistor thermal noise can be interpreted as a current NSD because the resistor thermal noise is much larger than the amplifier
by dividing the thermal noise with the resistance value, R, per voltage noise. At very low frequencies, this assumption is not
Ohm’s Law. valid due to the 1/f characteristic of the amplifier voltage noise.
Table 8 shows the thermal noise of a series of resistor values It is important to consider the bandwidth limitations of the
presented as both voltage and current noise. The current noise current noise measurement system shown in Figure 116. The
of a resistor decreases as the resistance increases. This surprising presence of stray capacitance makes it impossible to maintain
result illustrates that it is necessary to use high valued resistors the high impedances required for the measurement. All stray
to measure low levels of current noise. capacitance that couple the amplifier output to the inverting
Table 8. Resistor Thermal Noise input can be lumped into a single capacitor, CF, as shown in
Figure 116.
Resistor Value Voltage Noise Current Noise
1 MΩ 128 nV/√Hz 128 fA/√Hz The current noise must pass through RF to become voltage
100 MΩ 1.28 μV/√Hz 12.8 fA/√Hz noise. However, in practice, the current noise passes through
10 GΩ 12.8 μV/√Hz 1.28 fA/√Hz the parallel combination of RF and CF to become voltage noise.
1 TΩ 128 μV/√Hz 128 aA/√Hz At frequencies higher than the RFCF pole, most of the noise current
flows through the capacitor and current noise calculations at
The measurement setup used to gather the current noise data is
these frequencies are error prone due to the distributed parasitic
shown in Figure 116. The ADA4530-1 is configured as a TIA
nature of CF. A good guideline is to set the measurement band-
with a large value feedback resistor, RF. All amplifier current
width limit equal to the RFCF pole frequency.
noise from the inverting input flows through Resistor RF to
produce a voltage noise at VOUT. The measurement bandwidth limitations for high valued resistors
CF can be surprisingly low. Table 9 shows the −3 dB bandwidth of a
series of resistor values with a practical minimum stray capacitance
RF
value.
ADA4530-1
Table 9. Bandwidth Limitations
VOUT
Resistor Value Capacitor Value −3 dB Bandwidth
SR785
DSA 1 MΩ 100 fF 1.59 MHz
13405-305

100 MΩ 100 fF 15.9 kHz

Figure 116. Current Noise Measurement Setup 10 GΩ 100 fF 159 Hz
1 TΩ 100 fF 1.59 Hz

Rev. A | Page 39 of 50
ADA4530-1 Data Sheet
Reconsider the example amplifier with 2 fA/√Hz of current It is critically important to use high quality resistors during this
noise. The required RF value of 10 GΩ also limits the measurement. Many high valued resistors designed for high
measurement bandwidth to 159 Hz according to Table 9. voltage operation are nonlinear at low voltage levels and are not
It is useful to construct a table that combines the resistor noise suitable for electrometer work. Inferior resistors may also have
and measurement bandwidth guidelines. Table 10 shows the their own 1/f noise that corrupts the measurement results. Table 11
approximate bandwidth limitations for a variety of input lists the resistors used for the characterization of the ADA4530-1.
current noise measurements. Table 11. Test Resistor Device Numbers
Table 10. Measurement Current Noise Density vs. Bandwidth Resistor Value Manufacturer Device Number
Current Noise Density Bandwidth 100 MΩ Vishay RNX050100MDHLB
128 aA/√Hz 1.59 Hz 1 GΩ Ohmite RX-1M1007GE
1.28 fA/√Hz 159 Hz 10 GΩ Ohmite RX-1M1008JE
12.8 fA/√Hz 15.9 kHz 100 GΩ Ohmite RX-1M1009FE
128 fA/√Hz 1.59 MHz 1 TΩ Ohmite RX-1M100AKE

Table 10 demonstrates the error of the often claimed 0.1 fA/√Hz Figure 117 shows the output referred voltage NSD (VNRTO) of
at 10 kHz presented in the specifications of low input bias the transimpedance test circuit for the test resistors listed in
current amplifiers. Measuring this value requires a 1 TΩ resistor Table 11. The calculated thermal noise for each resistor is
with less than 15.9 aF (15.9 × 10−18 F) of stray capacitance, represented with the dashed line. The black dashed line
which is impossible. represents the 1/f voltage noise of the amplifier.
TOTAL OUTPUT VOLTAGE NOISE DENSITY (µV/√Hz)

INPUT SERIES RESISTOR THERMAL NOISE (µV/√Hz)

These kinds of claims are simply shot noise calculations based VSY = 10V
AV = +1
on the specified input bias currents of a few tens of femtoamperes.
1TΩ
Calculate the shot noise of a semiconductor as follows:
100 100
Shot Noise = √(2qIB)
100GΩ
where:
q is the charge on an electron. 10GΩ
IB is the current flowing through a junction. 10 10
Shot noise calculations are appropriate only for some legacy 1GΩ
JFET-based electrometer amplifiers, where only a single
junction is connected to the amplifier input pins. Modern high 1/f
100MΩ
impedance amplifiers have several semiconductor junctions 1
1

13405-306
connected to the amplifier input pins. The most significant of 0.001 0.01 0.1 1 10 100 1k 10k 100k
FREQUENCY (Hz)
these junctions are the ESD diode structures. The input bias
currents are equal to the sum of these diode currents. The diode Figure 117. Transimpedance NSD Referred to Output
currents are designed to cancel each other, but the shot noise VNRTO is dominated by the resistor noise for all of the test
currents are uncorrelated and cannot cancel, which, in turn, resistors up 1 TΩ. This means that the current noise contribu-
makes calculating the shot noise from the input bias current tion from the ADA4530-1 is insignificant relative to the thermal
impossible. noise of these resistors.
Even when appropriate, these shot noise calculations neglect all It is possible to calculate the current noise of the ADA4530-1
capacitive coupling effects so that they are valid only at very low with the 1 TΩ resistor. This result is shown in Figure 118. It is
frequencies. The gate to source capacitance of the input transis- impossible to calculate the amplifier current noise for all of the
tors couples noise currents from sources other than the input other resistors. The most that can be said is that the amplifier
junctions for frequencies above a few tens of hertz. This blowback current noise is much less than the resistor noise. The current
noise effect is present in all amplifiers, and it ensures that the noise densities of each of the test resistors are plotted as dashed
current NSD always increases as frequency increases. lines in Figure 118. The current noise of the ADA4530-1 is
The complex relationship between current noise, feedback below the resistor noise values.
resistance, and bandwidth means that the proper way to
characterize the current noise of an electrometer amplifier is by
measuring the output NSD with a variety of feedback resistors
that cover the entire span of values used in the end applications.
Each feedback resistor establishes a boundary for the minimum
measurable current noise over a range of frequencies.

Rev. A | Page 40 of 50
Data Sheet ADA4530-1
100
VSY = 10V Figure 120 shows the equivalent noise resistance vs. temperature.
AV = +1
From Figure 120, it is simple to determine that the ADA4530-1
CURRENT NOISE DENSITY (fA/√Hz)

100MΩ
contributes less noise than a 1 TΩ resistor for temperatures less
10
1GΩ
than 40°C. If the application requires 85°C operation, the
ADA4530-1 contributes as much noise as a 30 GΩ resistor. This
10GΩ example illustrates the considerable impact that temperature
1
100GΩ plays in determining the noise performance of an application.
10T
1TΩ f = 0.1Hz

0.1

EQUIVALENT NOISE RESISTANCE (Ω)

1T
0.01

13405-307
0.001 0.01 0.1 1 10 100 1k 10k 100k
FREQUENCY (Hz)

Figure 118. Current Noise Spectral Density

100G
The current noise of the ADA4530-1 originates from the
saturation current of the ESD diodes. The diode saturation
current has an exponential dependence on temperature;
therefore, it is expected that the current noise tracks this
10G

13405-309
temperature behavior. The current noise of the ADA4530-1 is 0 10 20 30 40 50 60 70 80 90
characterized over temperature using the transimpedance TEMPERATURE (°C)

measurement circuit with a 1 TΩ resistor. The measurements Figure 120. Equivalent Noise Resistance vs. Temperature
are limited to 85°C because of the maximum operating In summary, the excellent noise performance of the ADA4530-1
temperature of the resistor. Figure 119 shows the current noise makes it ideal for electrometer applications. For impedances
density at a frequency of 0.1 Hz for all of the test temperatures. less than 1 TΩ, the amplifier noise is negligible. Also, unlike
It can be useful to calculate an equivalent noise resistance from other amplifiers, the current noise has been fully characterized
the current noise density data in Figure 119. This conversion and is free of excessive blowback noise.
facilitates comparisons between the current noise generated by
the ADA4530-1 and the thermal noise of the feedback resistor
used in the circuit.
800
VSY = 10V
f = 0.1Hz
700
CURRENT NOISE DENSITY (aA/√Hz)

600

500

400

300

200

100

0
13405-308

0 10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)

Figure 119. Current Noise Density vs. Temperature

Rev. A | Page 41 of 50
ADA4530-1 Data Sheet

LAYOUT GUIDELINES
PHYSICAL IMPLEMENTATION OF GUARDING impedance insulation. A gap of 15 mil between the A trace and
TECHNIQUES the guard ring is sufficient.
In the Guarding section, guarding was introduced as a tech- Another simplified layout demonstrates the implementation of
nique fundamental to high impedance work. The goal of a guard ring in the TIA circuit (see Figure 122). The guard ring
guarding is to completely surround the insulation of high is implemented in the same manner as the buffer circuit. The
impedance node with another conductor that is driven to the primary difference is that the left half of the feedback resistor
guard voltage. This ideal is impossible to achieve in practice; (RF) and feedback capacitor (CF) are connected to the high
however, there are several practical structures that provide good impedance node. The guard ring shape is extended around
performance. these passive components to ensure that the entire high
impedance node is surrounded by guard. The guard ring is
GUARD RING
directly driven from the ADA4530-1 guard buffer (Pin 7).
A guard ring is a structure typically used to implement the
guarding technique on the surface of the PCB. A simplified
layout of the buffer circuit implements the guard ring around
CF
the high impedance (A) trace (see Figure 121). The output of
the voltage sensor is wired directly to the A and B pads in
Figure 121. The guard ring is a filled copper shape that
RF VOUT
completely surrounds the high impedance (A) trace from the
sensor connection to the noninverting input (Pin 1). The guard
ring is driven directly from the ADA4530-1 guard buffer (Pin 2)
V+
through a thermal relief shape connection. It is not necessary to A
connect the other guard buffer output (Pin 7). C+
GUARD
The solder mask was removed from the high impedance trace
ADA4530-1 GND
and the guard trace to ensure that the guard makes electrical
contact with any surface leakage paths. For the same reason,
avoid printing any silkscreen in this section. C–
B
V–

13405-321
Figure 122. TIA Circuit Layout
RF VOUT
The guard voltage in the TIA circuit is nominally equal to the B
RS voltage, which makes it possible to drive the guard ring directly
V+ from the B voltage without using the ADA4530-1 guard buffer.
C+ When implementing the guard ring this way, do not make any
connection to the guard buffer outputs (Pin 2 and Pin 7).
B
ADA4530-1 GND GUARD PLANE
A guard plane is a structure used to implement the guarding
C–
technique through the bulk of the PCB. The structure of the
A guard plane is shown in a cross section of the PCB (see Figure 123).
V– The guard plane is a filled copper shape that is placed directly
GUARD
below the high impedance (A) trace. This plane is connected to
the guard ring on the surface layer with vias.
13405-320

If the circuit board is constructed using high performance PCB

Figure 121. Buffer Circuit Layout laminates such as Rogers 4350B, a hybrid stackup is required for
There is not a large amount of exposed insulation between the mechanical strength. The outside layers are ceramic, whereas the
A trace and the guard ring. It is often counterproductive to core layers are conventional glass epoxy laminate. It is important to
increase this spacing to try to increase the insulation resistance place the guard shield on the boundary of the ceramic and glass
because the exposed insulator tends to accumulate surface epoxy materials to protect the high impedance node from the
charges generated from piezoelectric or triboelectric effects. poor dielectric relaxation characteristics of the glass epoxy
These charges are eventually swept across the insulator toward materials.
the high impedance conductor. The magnitude of this error
current is dependent on the area of the exposed high
Rev. A | Page 42 of 50
Data Sheet ADA4530-1
SOLDER MASK SOLDER MASK Traditional electrical interferers are not the only sources of concern.
GUARD A GUARD
Calculate the displacement current, I, in a capacitor as follows:
ROGERS
4350B V C
I C V (2)
GUARD t t
The second term in this equation is frequently ignored in most
FR-4 circuits, but it can generate some unusual problems in electrome-

13405-322
ter circuits. The problem is that the movement of any charged
Figure 123. Layout Cross Section with Guard Plane
object changes the coupling capacitance between the object and
the electrometer, and this change in capacitance injects small
VIA FENCE currents into the circuit. The ADA4530-1 is so sensitive that it
A via fence is an additional structure that guards the lateral easily detects the movement of a hand or the movement of a
leakage paths in the laminate between the guard ring and the piece of paper. These types of effects are not periodic or
guard plane (see Figure 123). The fence is implemented by predictable, and they can appear as erratic dc shifts on the time
surrounding the entire guard ring with vias that connect the scales of interest.
guard ring to the guard plane (see Figure 121 and Figure 122). Both of these types of interference can be reduced by the
CABLES AND CONNECTORS addition of a shield. A shield is a piece of conductive material
placed between the high impedance input and the interference
Guarding techniques are required for all of high impedance
source. This shield must be electrically connected to a low
wiring; not just on the PCB. Frequently, the high impedance
impedance source (such as signal ground). If the shield physi-
sensor is not directly mounted on the PCB with the electrome-
cally interrupts all of the capacitive coupling paths, all of the
ter amplifier and external cables are used to make the connection.
displacement current from the interference source is shunted to
The typical way to guard a cable connecting to a current output the low impedance source.
sensor is by using a coaxial cable. A coaxial cable consists of an
Notice that the construction of a shield is almost the same as
inner conductor surrounded with insulation, which is, in turn,
the construction of a guard. Because of this similarity, many
surrounded by a braided conductor. Use the inner conductor
guard structures also provide shielding as well. The primary
for the high impedance (A) terminal and the outer braided
difference is that the dc voltage of the shield is not important,
shield conductor for the low impedance (B) terminal. Conven-
whereas the guard must have a voltage equal to that of the high
iently, this arrangement effectively guards the coaxial insulation
impedance input. Shields that are driven by the guard buffer
resistance because the A terminal and B terminal are nominally
have the added benefit of bootstrapping the capacitance between
at the same voltage (when attached to a TIA interface circuit).
the high impedance input and the shield. The disadvantage of
Voltage output sensors are more problematic because the A this approach is that the guard buffer output impedance is 1 kΩ,
terminal and B terminal are not at the same voltage. The typical which makes the shield less effective than a signal ground or a
way to guard the voltage output sensor cable is to use triaxial chassis ground connection. The most effective systems typically
cable. Triaxial cable is constructed with an inner conductor with use the box within a box construction: the outer shield is driven
two separate braided conductors. Each of these braided with ground and the inner shield is driven with guard.
conductors is separated from each other with insulation. Use
There is another capacitive interference effect that typically
the inner conductor for the high impedance (A) terminal and
cannot be shielded. This displacement current is generated from
the inner braided conductor for the guard (VGRD) connection,
a change in capacitance with respect to time (the second term of
and use the outer braided conductor for the low impedance (B)
Equation 2). This change is due to the mechanical movement of
terminal. All the insulation around the inner conductor is
the circuit components. This movement, which can be caused
completely surrounded by the guard conductor, which keeps the
by mechanical impact or vibration, generates electrical interference.
voltage drop across this insulation equal to zero.
This interference typically appears at unexpected frequencies
ELECTROSTATIC INTERFERANCE that are equal to the mechanical resonances of the components.
Very high impedance electrometer circuits are susceptible to This effect must be considered when using traditional air wiring
interference through capacitive coupling. The amount of capaci- techniques for large feedback resistors or relays. It is important
tance required to couple low frequency signals is surprisingly to ensure solid mechanical connections to Teflon standoffs for
small. For example, line frequency (60 Hz) interference is this type of construction.
coupled (with a −3 dB loss) to a 1 TΩ impedance with only 3 fF
of coupling capacitance.

Rev. A | Page 43 of 50
ADA4530-1 Data Sheet

PHOTODIODE INTERFACE
The low input bias current and low input offset voltage makes ture. An error current is created because the amplifier offset
the ADA4530-1 an excellent choice for signal conditioning voltage is applied across this shunt resistance, resulting in an
photodiodes at extremely low illumination levels. Figure 124 RTI error equal to
shows the ADA4530-1 configured in a transimpedance ampli- IVOS_RTI = VOS/RSHUNT
fier interfacing with a photodiode operating in photovoltaic
mode (photodiode is zero biased). A photodiode produces an It is equivalent to think that the shunt resistance increases the
output current proportional to the illumination level. The DC noise gain which multiplies the offset voltage to the output.
amplifier converts the signal current, IPD, into an output voltage The RTO error due to VOS is equal to:
with the following equation: VOS_RTO = VOS × Noise Gain
VOUT = IPD × RF VOS_RTO = VOS × (1 + RF/RSHUNT)
CF
The amplifier input resistance and insulation resistance appear
RF in parallel with the photodiode shunt resistance. These addi-
IPD tional resistances reduce the effective shunt resistance, but they
VOUT are much larger than the photodiode shunt resistance and can
PHOTODIODE
13405-323

usually be ignored.

Figure 124. Transimpedance Amplifier with Photodiode

AC ERROR ANALYSIS
Photodiode TIA circuits typically require external compensation to
Figure 125 replaces the photodiode with an equivalent circuit
give satisfactory dynamic performance. The large feedback
model. IPD is the photo current generated by incident light and
resistor (RF) interacts with the large photodiode capacitance
is proportional to the light level. The shunt capacitance (CSHUNT)
(CSHUNT) to create a low frequency pole in the feedback network.
models the depletion capacitance of the diode. This capacitance
Photodiode shunt capacitance, amplifier input capacitance, and
depends on the area of the photodiode and the voltage bias. The
trace capacitance are lumped into a single element, CSHUNT. The
shunt resistance (RSHUNT) represents the voltage vs. current slope
phase shift due to this pole must be recovered prior to the
of the exponential diode curve near zero bias voltage.
crossover frequency for the feedback loop to be stable. The
CF
usual method to recover this phase shift is to create a zero in the
RF feedback factor with the addition of the feedback capacitor (CF).
PHOTODIODE
The classic way of analyzing this circuit is by examining the
CSHUNT VOUT
IPD
noise gain vs. frequency (see Figure 126). At low frequencies,
RSHUNT
the noise gain is determined by the ratio of the feedback to the
shunt resistance.
13405-324

RF
Figure 125. Transimpedance Amplifier with Photodiode Model NG1  1 
RSHUNT
DC ERROR ANALYSIS The troublesome low frequency pole (which is a zero in the
All of the errors described in the High Impedance Measurements noise gain) occurs at Frequency f1. From this frequency onward,
section related to TIA circuits are applicable to photodiode the noise gain increases. If there is no feedback capacitor in the
interfaces. circuit, the noise gain follows the dotted line until it intersects
The inverting input bias current, IB−, sums directly with the with the amplifier open-loop gain curve. If these curves
photodiode current for a referred to input (RTI) error equal to intersect at the 20 dB/decade slopes shown in Figure 126, the
IB−. This current flows through the feedback resistor, creating a circuit is unstable.
referred to output (RTO) error equal to The addition of CF adds a zero to the feedback factor (which is a
VIB_RTO = IB− × RF pole in the noise gain) at Frequency f2. Beyond Frequency f2, the
noise gain is determined by the ratio of the shunt capacitance to
The amplifier offset voltage, VOS, is a major error source in
the feedback capacitance.
photodiode interface circuits because of the relatively low shunt
resistance of large area photodiodes. Typical values are in the C SHUNT
NG 2  1 
range of 1 GΩ to100 GΩ at 25°C. More importantly, the shunt CF
resistance decreases by half for every 10°C increase in tempera-

Rev. A | Page 44 of 50
Data Sheet ADA4530-1
OPEN-LOOP GAIN
GAIN (dB)

IF CF = 0fF

SIGNAL BANDWIDTH CLOSED-LOOP BANDWIDTH

NG 2

NOISE GAIN
NG1

FREQUENCY (Hz)

13405-325
f1 f2 f3 fUGC

Figure 126. Transimpedance Noise Gain vs. Frequency

For completeness, the noise gain equations are as follows: NOISE ANALYSIS
 2f 1  Photodiode TIA circuits have four noise sources that must be
  
 RF  f1  considered:
NG( f )  1  
 2f
 R   
S 1 The thermal noise of the feedback resistor (RF)
 f2   The saturation current noise of the photodiode
1  The current noise of the amplifier
f1 

RF RSHUNT
CF  CSHUNT  The voltage noise of the amplifier
RF  RSHUNT The noise contributions of these sources are typically referred to
1 output for analysis. The thermal noise of RF appears directly at
f2  the output. This noise is filtered by the feedback capacitance so
RF C F
that its −3 dB bandwidth is the same as the signal bandwidth (f2).
For simplicity, bandwidth limitations are ignored in the noise
The photocurrent of a photodiode, IPD, produces shot noise equal to
gain equations. The noise gain starts to roll-off when it
intersects with the open-loop gain of the amplifier. This pole INPD = √(2qIPD)
frequency (f3) is determined by the unity gain crossover It is a mistake to assume that the noise goes to zero as the diode
frequency (fUGC) of the amplifier and the high frequency noise current goes to zero. Zero net current out of the diode simply
gain, NG2, as follows: means that the saturation current flowing in one direction is at
fUGC thermal equilibrium with the saturation current flowing in the
f3  (3)
 CSHUNT  opposite direction. These currents are uncorrelated and add in a
1  
 CF 
root sum square fashion. This net current noise is equivalent to
 the thermal noise of a physical resistor with a value of RSHUNT.
The addition of CF has an impact on the signal frequency This convenient fact allows the photodiode to be accurately
response. At low frequencies, the transimpedance gain is equal modeled with a simple resistor, RSHUNT. The thermal noise of
to RF. As the frequency increases, the impedance of CF drops RSHUNT is amplified by the ratio of the feedback resistance to the
below RF and starts to reduce this transimpedance gain. This shunt resistance. This noise is also filtered to the signal bandwidth.
signal gain equation is as follows: The current noise of the amplifier flows through the feedback
  resistor to become a noise voltage at the output. It is subject to
  the same bandwidth limitations as the previous noise contributors.
 1 
Signal Gain( f )  RF
 2f  The voltage noise of the amplifier is multiplied by the noise gain
 f 1
 2  of the circuit to the output. This noise source is significant for
two reasons. First, the high frequency noise gain can be high
due to the large ratio between the shunt capacitance and the
feedback capacitance. Second, the voltage noise bandwidth is
much higher than the other contributors. The noise bandwidth
is limited only by bandwidth of the amplifier.
Rev. A | Page 45 of 50
ADA4530-1 Data Sheet
Each of these noise contributors is graphed vs. frequency in improving. The photodiode noise is higher than the
Figure 127. A summary of the noise sources and their RTO amplifier current noise in nearly all practical photodiodes.
contributions is shown in Table 12. The total RTO noise adds  The low frequency noise gain due to RSHUNT. When RF is
the contributions of each noise source in root sum square. larger than RSHUNT, the noise gain multiplies VOS and TCVOS
errors and the signal to error ratio stops improving.
100
RF
The signal bandwidth increases as the feedback capacitance (CF)
decreases. The lower limit for CF is typically limited by one of
RSHUNT
the following:
10
NSD (µV/√Hz)

IN–  Parasitic feedback capacitances limit the minimum value of

CF to 50 fF to 100 fF.
VN
1  Available component values. Physical components can be
found in surface mount packages for values from 0.1 pF to
1 pF in 100 fF increments.
0.1
 Feedback loop stability. CF must be large enough to recover
f1 f2 f3 enough phase shift prior to the loop crossover for stable
operation. This capacitance value can be a significant
13405-404

1 10 100 1k
FREQUENCY consideration for smaller values of RF. Large values
Figure 127. Photodiode TIA RTO Noise Spectral Density (>1 GΩ) tend to be self compensating through the parasitic
feedback capacitance.
Table 12. Photodiode Interface Noise Sources  High frequency noise gain. The high frequency noise gain
Noise Source RTO Noise Noise Bandwidth is set by the ratio of CSHUNT to CF. For very large noise gains,
RF √(4kTRF) π/2 × f2 it is possible for the amplifier voltage noise to be greater
Photodiode (RF/RSHUNT)√(4kTRSHUNT) π/2 × f2 than the feedback resistor noise.
IN− Amplifier RF × IN− π/2 × f2
VN Amplifier VN × noise gain π/2 × f3 DESIGN EXAMPLE
In this section, an example TIA circuit is designed using a
DESIGN RECOMMENDATIONS photometry grade photodiode (Hamamatsu S1226-18BQ). This
The design goal for a large area photodiode TIA circuit is medium area (1.2 mm2) silicon photodiode is responsive in the
usually to maximize SNR and minimize dc errors. Increasing ultraviolet (UV) through visible frequency range. The mini-
the feedback resistor size accomplishes both goals. The signal mum shunt resistance (RSHUNT) is specified at 5 GΩ at 25°C. The
gain increases directly with RF, whereas the noise increases in a shunt capacitance (CSHUNT) is specified at 35 pF. The quartz
square root fashion. High gains also make the output signal window limits the maximum operating temperature to 60°C.
large relative to output voltage errors (such as VOS).
Based on the specified minimum shunt resistance and the
The upper limit for RF is typically determined by one of the recommendations in the Design Recommendations section, a
following: value of 10 GΩ is chosen for RF. This example circuit is powered
 Amplifier output swing. The maximum photocurrent from ±5 V with the input common-mode voltage set at 0 V, which
multiplied by RF must be less than amplifier swing allows a maximum photocurrent of approximately 500 pA.
limitations. An error budget is constructed based on the DC Error Analysis
 Signal bandwidth (or settling time). Signal bandwidth is section (see Table 13). The amplifier offset voltage applies the
dependent on RF × CF. Achieving high signal bandwidths maximum temperature drift limit to the maximum room
with large feedback resistors can require vanishingly small temperature offset limit. The photo diode shunt resistance limit
feedback capacitors to implement. The ultimate limitation is reduced by half for every 10°C.
is due to the parasitic feedback capacitance from the
fringing electric fields in the circuit. Parasitic capacitances Table 13. Photodiode Interface DC Error Budget
in the 50 fF to 100 fF range are possible. To put this in Error Source 25°C 45°C 60°C
perspective, a 100 fF parasitic capacitance limits the signal VOS 40 μV 40 μV + 10 μV 40 μV + 18 μV
bandwidth of a 100 GΩ TIA to 16 Hz. RSHUNT 5 GΩ 1.25 GΩ 442 MΩ
 The thermal noise of the photodiode (RSHUNT). When RF is Noise Gain 3 9 23
significantly larger than RSHUNT, the total noise is domi- VOS Error RTO 120 μV 450 μV 1.3 mV
nated by the photodiode and the SNR stops improving. IB 20 fA 20 fA 20 fA
 The current noise of the amplifier. When the current noise IB Error RTO 200 μV 200 μV 200 μV
of the amplifier is larger than the noise of RF, the SNR stops Total Error RTO 320 μV 650 μV 1.5 mV
Total Error RTI 32 fA 65 fA 150 fA
Rev. A | Page 46 of 50
Data Sheet ADA4530-1
The total RTI error over the entire temperature range is less VSY = 10V
VCM = VSY/2
than 150 fA, which is equal to 300 ppm of the 500 pA full-scale 10 TA = 25°C
range. Note that the extraordinarily low input bias current of

TRANSIMPEDANCE GAIN (GΩ)

the ADA4530-1 is not a significant contributor to the total error
over temperature. The interaction of the offset voltage with the
shunt resistance of the photodiode is the most significant error
source. 1

This circuit was constructed as described with a 10 GΩ feed-

back resistor (Ohmite RX-1M1008JE). The dc error performance
was measured over the 25°C to 60°C temperature range (see
Figure 128). The error increases rapidly with temperature as the CF = 0fF
CF = 300fF
shunt resistance changes the noise gain exponentially. The total 0.1

13405-407
0.1 1 10 100 1k 10k 100k
RTI error ranges from +2 fA to −10 fA, considerably lower than FREQUENCY (Hz)
the worst case error budget, as expected. Figure 129. Transimpedance Gain vs. Frequency
20 2
VSY = 10V The stability improvement can be seen in the time domain as
VCM = VSY/2
0 0 well. The circuits step response to a 10 pA photocurrent is
shown in Figure 130. The uncompensated circuit (red curve)
–20 –2 shows considerable (20%) overshoot. The compensated circuit
RTO ERROR (µV)

RTI ERROR (fA)

(blue curve) is overdamped.

–40 –4
40 4
VSY = 10V
–60 –6 TA = 25°C
20 2
IPD = 10pA

INPUT REFERRED CURRENT (pA)

–80 –8 0 0
OUTPUT VOLTAGE (mV)

–20 –2
–100 –10
–40 –4

–120 –12
–60 –6
13405-401

0 10 20 30 40 50 60 70
TEMPERATURE (°C)
–80 –8
Figure 128. DC Error vs. Temperature
–100 –10
The ac performance of the circuit was also measured. The
–120 CF = 0fF –12
circuit was initially constructed without a physical feedback CF = 300fF
capacitor as a baseline. The transimpedance gain vs. frequency –140 –14

13405-400
0 5 10 15 20 25 30 35 40
is shown in Figure 129. The 30% frequency peaking seen in the TIME (ms)
frequency response (red curve) indicates that the feedback loop Figure 130. 10 pA Step Response
is marginally compensated with parasitic capacitance.
A noise budget is constructed based on the Noise Analysis
A physical capacitor was added to improve the loop compensa- section. The RTO noise budget is separated into noise sources
tion. This capacitor is a 300 fF C0G ceramic in a Size 0805, integrated with a low bandwidth (see Table 14) and those
surface-mount package (AVX UQCFVA0R3BAT2A\500). C0G integrated with a high bandwidth (see Table 15).
ceramic capacitors are good candidates for electrometer circuits
The low frequency noise contributors include the feedback
because they have adequate insulation resistance and dielectric
resistance, the shunt resistance and the amplifier current noise.
absorption performance. These low valued capacitors are designed
Each of these sources has a −3 dB bandwidth equal to the signal
for RF use and are readily available. The 300 fF capacitor elimi-
bandwidth (50 Hz); this is equivalent to a noise bandwidth of
nates the frequency peaking completely (blue curve) but it
79 Hz. The most significant noise source is the photodiode
reduces the −3 dB bandwidth from 390 Hz to 50 Hz.
shunt resistance by a large margin. The second most significant
source is the feedback resistor. The amplifier current noise is so
low that it can be ignored.

Rev. A | Page 47 of 50
ADA4530-1 Data Sheet
Table 14. Low Frequency Noise Budget VSY = 10V

VOLTAGE NOISE SPECTRAL DENSITY (µV/√Hz)

VCM = VSY/2

INTEGRATED VOTLAGE NOISE (µV rms)

Error Source 25°C 45°C 60°C 100 TA = 25°C 1000

VNRF 12.8 μV/√Hz 13.2 μV/√Hz 13.5 μV/√Hz

RSHUNT 5 GΩ 1.25 GΩ 442 MΩ
VNRSHUNT 9 μV/√Hz 4.7 μV/√Hz 2.8 μV/√Hz
RF/RSHUNT 2 8 22
VNRSHUNT_RTO 18 μV/√Hz 37 μV/√Hz 61 μV/√Hz 10 100
IN− 0.07 fA/√Hz 0.15 fA/√Hz 0.24 fA/√Hz
IN−_RTO 700 nV/√Hz 1.5 μV/√Hz 2.4 μV/√Hz
Low Frequency 22 μV/√Hz 39 μV/√Hz 62 μV/√Hz NSD, CF = 0fF
NSD, CF = 300fF
NSD Total RMS, CF = 0fF
Low Frequency 194 μV rms 345 μV rms 549 μV rms RMS, CF = 300fF
1 10

13405-405
RMS Total 0.1 1 10 100 1k 10k 100k
FREQUENCY (Hz)
The sole high frequency noise contributor is the amplifier Figure 131. RTO Noise Spectral Density (25°C)
voltage noise, which is multiplied by the high frequency noise
The dashed curves show the integration of the NSD across the
gain and band limited only by the amplifier gain. The −3 dB
frequency spectrum. These are useful to calculate the rms noise
bandwidth of the amplifier is 17 kHz (refer to Equation 3,
over a variety of bandwidths. For example, the rms noise over
where f3 = fUGC ÷ NG2 = 2 MHz ÷ 118). The equivalent noise
the entire 100 kHz measurement bandwidth is 400 μV rms,
bandwidth is 27 kHz. The high bandwidth is the reason the
which is approximately the same as the calculated total noise of
high frequency noise is significant even though the noise
333 μV rms. If a postfilter is added with a noise bandwidth of
spectral density is much lower than the low frequency noise.
1 kHz, Figure 131 shows that the integrated noise is 200 μV rms
Table 15. High Frequency Noise Budget (a 2× improvement).
Error Source 25°C 45°C 60°C The uncompensated circuit (red curves) shows considerably
VN 14 nV/√Hz 14.5 nV/√Hz 14.8 nV/√Hz worse noise performance. The frequency peaking due to the
High Frequency 118 118 118 marginal loop stability multiplies the noise as well as the signal.
Noise Gain In addition, the high frequency noise gain is larger, which adds
VN_RTO 1.6 μV/√Hz 1.7 μV/√Hz 1.7 μV/√Hz much more noise outside the signal bandwidth. Both of these
High Frequency 271 μV rms 281 μV rms 286 μV rms effects together generate 1.2 mV rms of total noise. Even if the
RMS Total
transient and frequency response of an undercompensated TIA
At low temperatures, the amplifier voltage noise is more signifi- are acceptable, the large noise penalty may not be.
cant than any other noise source. This is important because the Lastly, the NSD was measured for this circuit at 60°C (see
majority of this noise occurs outside the useful bandwidth of Figure 132). As expected, the low frequency noise increased as a
the circuit. For this reason, it is prudent to add a low-pass filter result of the photodiode shunt resistance. The average low
to the output of a photodiode TIA circuit. This filter can be active frequency NSD is 22 μV/√Hz. Removing the contribution of RF
or passive depending on the needs of the system. A simple RC gives an RTO contribution of 17 μV/√Hz, which is equivalent to
filter with a −3 dB cutoff of 500 Hz has an insignificant impact an RTI current noise of 1.7 fA/√Hz. RSHUNT must be approxi-
on the frequency response of the signal path, but it lowers the mately 6.5 GΩ at 60°C to generate this noise.
integrated noise from 271 μV rms to 45 μV rms (a 6× reduction). NSD, CF = 300fF
VSY = 10V
VOLTAGE NOISE SPECTRAL DENSITY (µV/√Hz)

VCM = VSY/2 RMS, CF = 300fF

The NSD was measured for this circuit with (blue curve) and
INTEGRATED VOTLAGE NOISE (µV rms)

100 TA = 60°C 1000

without (red curve) the 300 fF CF capacitor (see Figure 131). At
low frequencies, the NSD is approximately equal to the noise
from the feedback resistor alone (12.8 μV/√Hz). The value of
the low frequency NSD shows that the shunt resistance is much
larger than the specified minimum (which is expected). As 10 100
frequency increases, the resistor noise rolls off at the signal
bandwidth (50 Hz). The NSD then plateaus at the amplifier
voltage noise level until the bandwidth limitations of the
amplifier roll off the NSD toward zero.
1 10
13405-406

0.1 1 10 100 1k 10k 100k

FREQUENCY (Hz)

Figure 132. RTO Noise Spectral Density (60°C)

Rev. A | Page 48 of 50
Data Sheet ADA4530-1

POWER SUPPLY RECOMMENDATIONS

Analog Devices offers a wide range of power management also be used. An LDO like the ADM7170 or ADP7118 is ideal
products to meet the requirements of most high performance to generate the low noise rail.
signal chains. For a dual-supply application, the ADA4530-1 typically needs a
Examples of a single- and dual-supply solution is shown in ±5 V supply, although in some applications, a ±2.5 V to ±8 V
Figure 133. The ADP2370 and ADP5075, cascaded with the supply can be used. LDOs like the ADP7118 or ADM7170 are the
ADP7118 or ADM7170, and the ADP7182 generate clean optimum choices for the positive supply, and the ADP7182 for
positive and negative rails. These rails power the ADA4530-1, the negative supply. In addition, if a negative supply is not already
electrometer amplifier and/or the precision converter in a available, the ADP5075 or the ADP5070 can generate the
typical signal chain. negative supply from a positive supply, as shown in Figure 133.
12V +7.5V
INPUT ADP2370 +8.5V OR +5V Figure 134 shows the combined PSRR of using the ADP7118 to
BUCK OR +6V ADP7118
REGULATOR LDO provide +5 V on +VSY of the ADA4530-1, and the ADP7182 to
provide –5 V on–VSY, from a 9 V battery main supply. Figure 135
–7.5V
ADP5075
–8.5V OR –5V shows the maximum allowable ripple at the input so that the
OR –6V ADP7182
INVERTING combined PSRR of the LDO and the amplifier can still attenuate
REGULATOR LDO
the noise level down to the noise floor.
+6V ADP7118
+5V For example, if the main supply to the ADP7118 and ADA4530-1
3.3V ADP5070 LDO
INPUT BOOST AND has a switching noise of 20 mV p-p at 300 kHz, Figure 135 shows
INVERTING –5V
REGULATOR –6V ADP7182 that it is below the maximum value of 90 mV p-p. Therefore,
LDO
the combined PSRR of the system can still attenuate and bring
15V/12V/6V
the noise level down to the noise floor, in effect, the 300 kHz
INPUT ADM7170/ +12V/+10V/+5V
noise at the input is not seen at the output of the amplifier.
13405-533

ADP7118
LDO
0
+PSRR
Figure 133. Recommended Power Solutions –PSRR

–20
Table 16. Recommended Power Management Devices
Product Description
–40
ADP5075 800 mA, dc-to-dc inverting regulator
PSRR (dB)

ADP2370 High voltage, 1.2 MHz/600 kHz, 800 mA, low

–60
quiescent current buck regulator
ADP5070 1 A/0.6 A, dc-to-dc switching regulator with
–80
independent positive and negative outputs
ADM7170 6.5 V, 500 mA, ultralow noise, high PSRR, CMOS LDO
–100
ADP7118 20 V, 200 mA, low noise, high PSRR, CMOS LDO
ADP7182 −28 V, −200 mA, low noise, linear regulator
–120

13405-534
10k 100k 1M 10M
POWER SUPPLY CONSIDERATIONS FREQUENCY (Hz)

The PSRR of the ADA4530-1 is excellent at dc (approximately Figure 134. Positive and Negative PSRR for the ADP7118 and ADP7182
Powering ADA4530-1, ±VSY = ±5 V, +IN = 0 V
150 dB); however, it decreases as frequency increases. To achieve
1000
the best performance of the ADA4530-1, a low-noise supply is ADP7118
ADP7182
necessary. If switching supplies are used for input rails, a low
dropout regulator (LDO) is essential to attenuate the switching 100

spurs to a level that does not affect the ADA4530-1 output.

Switching power supply noise typically spans a frequency range 10
(mV p-p)

from 300 kHz and up. The switching spurs can effectively be
attenuated using the LDO. Additional filtering around the LDO
1
may be necessary, especially when using a switching regulator to
generate an intermediate rail. Switching regulators also generate
high frequency noise content (>100 MHz), even when running 0.1

in the 100 kHz range, because of the high dv/dt of the switch
node. In this case, ferrite beads can be used, as described in the 0.01
13405-535

0.01 0.1 1 10
AN-1120 Application Note and the AN-1368 Application Note.
FREQUENCY (Hz)
For a single-supply application, the ADA4530-1 typically needs Figure 135. Maximum Allowable Ripple at the Input of the LDOs to Bring
a 5 V, 10 V, or 12 V supply, although a 4.5 V to 16 V supply can Spurs To Noise Floor Level (−120 dB)
Rev. A | Page 49 of 50
ADA4530-1 Data Sheet

OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)

8 5
4.00 (0.1574) 6.20 (0.2441)
3.80 (0.1497) 1 5.80 (0.2284)
4

1.27 (0.0500) 0.50 (0.0196)

BSC 45°
1.75 (0.0688) 0.25 (0.0099)
0.25 (0.0098) 1.35 (0.0532)
8°
0.10 (0.0040) 0°
COPLANARITY 0.51 (0.0201)
0.10 1.27 (0.0500)
0.31 (0.0122) 0.25 (0.0098)
SEATING 0.40 (0.0157)
PLANE 0.17 (0.0067)

COMPLIANT TO JEDEC STANDARDS MS-012-A A

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

012407-A
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 136. 8-Lead Small Outline Package [SOIC_N]

Narrow Body
(R-8)
Dimensions shown in millimeters

ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADA4530-1ARZ −40°C to +125°C 8-Lead Small Outline Package [SOIC_N] R-8
ADA4530-1ARZ-R7 −40°C to +125°C 8-Lead Small Outline Package [SOIC_N] R-8
ADA4530-1ARZ-RL −40°C to +125°C 8-Lead Small Outline Package [SOIC_N] R-8
ADA4530-1R-EBZ-BUF Evaluation Board Buffer Configuration for 8-Lead SOIC
ADA4530-1R-EBZ-TIA Evaluation Board Transimpedance Configuration for 8-Lead SOIC
1
Z = RoHS Compliant Part.

©2015–2016 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D13405-0-3/16(A)

Rev. A | Page 50 of 50