Scribd
Upload
24 views1 page

Digital Techniques Unit Test - Gujarat

This document contains a unit test for a Digital Techniques course. It has two questions worth a total of 20 marks. Question 1 is worth 8 marks and requires students to attempt 4 out of 6 parts involving conversions between binary, octal, decimal; Boolean logic gates; and arithmetic operations. Question 2 is worth 12 marks and requires students to attempt 3 out of 4 parts involving De Morgan's theorem, logic minimization, logic gate realization using NAND gates, and full adder circuit design. The test provides instructions to write answers in order and illustrate with sketches as needed.

Uploaded by

rashmi patil
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
24 views1 page

Digital Techniques Unit Test - Gujarat

This document contains a unit test for a Digital Techniques course. It has two questions worth a total of 20 marks. Question 1 is worth 8 marks and requires students to attempt 4 out of 6 parts involving conversions between binary, octal, decimal; Boolean logic gates; and arithmetic operations. Question 2 is worth 12 marks and requires students to attempt 3 out of 4 parts involving De Morgan's theorem, logic minimization, logic gate realization using NAND gates, and full adder circuit design. The test provides instructions to write answers in order and illustrate with sketches as needed.

Uploaded by

rashmi patil
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

UNIT TEST -I

Government Polytechnic, Pen


Instrumentation and Control Department
Sem: III Subject: Digital Techniques (22320) Date: / /2022
Time: Total Marks: 20
_______________________________________________________________________________________________________
Instructions:
1. All questions are compulsory.
2. Illustrate your answers with neat sketches wherever necessary.
3. Figures to the right indicate full marks.
4. Assume suitable data if necessary.
5. Preferably, write the answers in sequential order.
______________________________________________________________________________________________
Q.1 Attempt any FOUR. (8 marks)
a) Covert (D8F)16into Binary and Octal. (CO a)
b) Perform the BCD Addition.(17)10 + (57)10 (CO a)
c) Draw symbol, truth table and logic symbol of Ex-OR gate. (CO b)
d) List characteristics of logic family. (CO b)
e) Perform (9)10 - (5)10using 2’s complement. (CO a)
f) Write the gray code to given number(1101)2. (CO a)

Q.2 Attempt any THREE. (12 marks)


a) State and Prove De-Morgan’s theorem. (CO b)
b) Minimize the four variable logic function using K map. (CO c)
f(A,B,C,D) = ∑m(0, 1, 2, 3, 5, 7, 8, 9, 11, 14)
c) Realize the basic logic gates using NAND gates. (CO b)
d) Design full adder circuit. (CO c)

UNIT TEST -I
Government Polytechnic, Pen
Instrumentation and Control Department
Sem: III Subject: Digital Techniques (22320) Date: / /2022
Time: Total Marks: 20
_______________________________________________________________________________________________________
Instructions:
6. All questions are compulsory.
7. Illustrate your answers with neat sketches wherever necessary.
8. Figures to the right indicate full marks.
9. Assume suitable data if necessary.
10. Preferably, write the answers in sequential order.
______________________________________________________________________________________________
Q.1 Attempt any FOUR. (8 marks)
a) Covert (D8F)16into Binary and Octal. (CO a)
b) Perform the BCD Addition. (17)10 + (57)10 (CO a)
c) Draw symbol, truth table and logic symbol of Ex-OR gate. (CO b)
d) List characteristics of logic family. (CO b)
e) Perform (9)10 - (5)10using 2’s complement. (CO a)
f) Write the gray code to given number(1101)2. (CO a)

Q.2 Attempt any THREE. (12 marks)


a) State and Prove De-Morgan’s theorem. (CO b)
b) Minimize the four variable logic function using K map. (CO c)
f(A,B,C,D) = ∑m(0, 1, 2, 3, 5, 7, 8, 9, 11, 14)
c) Realize the basic logic gates using NAND gates. (CO b)
d) Design full adder circuit. (CO c)

You might also like