| D [Cero SERVICE MANUALTABLE OF CONTENTS SECTION 1 SPECIFICATIONS [Link] 1-1 SECTION 2 CONTROLS AND THEIR FUNCTIONS ..csscscssssscessssssecccssssssssusvecsesseeceenseses 2-1 ~4 FRONT PANEL cosecescsscssssssssssssscssescsssssssssssessscssesssssssanessassensnssanscsseeesssssnsetsessarseensees 2-1 REAR PANEL ocssessscessscssseesesssesevssscsssssesseseseeseseesesseseccncsesssesessecanneeseneesnecscossnsnonnensnees 2-4 SECTION 3 INSIDE VIEWS o.....ccscsssseessessssssssssssssesesccsssssssanessesescessseneseenessssseninesenanste 3-1 ~2 SECTION 4 BLOCK DIAGRAM .......ccsecessesssssessssssssevececesssvesessesseseeeessessesencecenecessensnennven 4-1 ~2 SECTION 5 OPERATION ...ccccesssssssssesesssssssssssesssssssesesccsssssnsessssssssesecsssssesesessssviesecssseeees 5-1 ~ 15 RE UNIT oiaccccscssssssssessescsssssscssevseesesssnssssssvessessersssssuaversesssesssesnueesscerssnnsneesseesestenvess 5-1 MAIN UNIT cccsssesessssssssesessssssssessssssssesssessessessesseseessstsecsssseseseseccececeenssonsnanssssssenssesvsses 5-2 PLL UNIT cocsccssssssssssssscssssscsssssssssssssssesesssssessessesssssnssssssasssssesssennesesessevsvasnsessecenseesenseees 5-5 DRIVER (LOGIC) UNIT coesecescsssscsecsscseccsscsccsstssscssesesecssscssscssesesessececscenentnnsseseeeesesesaees 5-9 SECTION 6 DISASSEMBLY .....cssssscsssssssssssssssssesessssssssssssssssssssssssssssveceesensensssesetecesnensees 6-1 ~8 SECTION 7 ADJUSTMENTS oveccscccscsecsscsssssssssscssssesseceseccssssescesesscesecccecssrssnnesnnensesnesessenies 7-1 ~3 PLL ADJUSTMENT icccssssscssscssessssssscssssssssccssccessecssscssescssssccesececcesannseunsansssesanssssnsiaves 7-1 RECEIVER ADJUSTMENT oiccsccscssscsssssssssssssessrssssecsssessessevsssseessccssssssnsessccnsssssnssesss 7-2 FM UNIT ADJUSTMENT oocccccccccsssssssesessseccsessssesessecsssssssssssceseesssenssssnecsecensssenesesess 7-3 SECTION 8 CIRCUIT AND VOLTAGE DIAGRAMS o.....cccccccssssssescssssssssessssssssevssnenensenses B-1 ~11 SECTION 9 IC RATINGS .i..cccssssssssssssscsssssseseeesesccssssenesesecsescesssneneeseesssnnvseeeseceessaneeess 9-1 ~7 SECTION 10 PARTS LIST oaicccscsssssssssscsesesssscsesesesessssessersessssssnsnenesssssnnanensisnausevuessesseseseeie 10-1 ~ 20 SECTION 11 SCHEMATIC DIAGRAM ouunccccccccssssssssssssssesecseccessesssssssvevrsstesasssnnsssssseenseese 1-1 SECTION 12 BOARD LAYOUT uu... ccetecenetsscsseteerenensssesenensessneseseensnusnaanesnseatens SEPARATESECTION 1 SPECIFICATIONS GENERAL Number of Semiconductors Frequency Coverage Frequency Control Frequency Readout Frequency Stability Power Supply Requirements Antenna impedance Weight Dimensions RECEIVER Receiving System Receiving Modes IF Frequencies 2nd IF Center Frequency Sensitivity (when preamplifier is ON} Selectivity Spurious Response Rejection Ratio Audio Output Audio Output Impedance * When optional FM unit is instal led. Transistors 90 FETs 19 ICs (Including CPU) 47 Diodes 237 0.1 MHz ~ 30 MHz (Australian version: 2.0 MHz ~ 30.0 MHz) (German version: 0.15 MHz ~ 26.1 MHz) Thirty 1-MHz segments CPU based 10-Hz step digital PLL synthesizer with dual VFO system 6-digit 100-Hz readout Less than 200 Hz after switch ON 1 min. te 60 mins., and less than 30 Hz after 1 hour, Less than 500 Hz in the range of 0°C to +50°C 117 V or 235 V + 10% 50 ~ 60 Hz 30 VA (100V/200V/220V use requires internal modification) 50 ohms unbalanced (Single wire can be used on 0.1 ~ 1.6 MHz} 7.5 kg (16.5 Ibs.) 111 (H) x 286 (W} x 276 (D} mm (4-3/8 x 11-1/4 x 10-7/8 inches} Quadruple conversion superheterodyne with continuous band- width control (F,*: triple conversion superheterodyne} Ay, AgJ (USB, LSB), F, {output FSK audio signal), A, F.* ist 70.4515 MHz 2nd 9.0115 MHz 3rd 455 kHz ath 9.0115 MHz (except F3*) SSB (A,J) AM (A,) 9.0115 MHz CW (A,) RTTY (F,} 9.0106 MHz FM* (F,) 9.0100 MHz SSB, CW, RTTY Less than 0.15 microvolt (0.1 ~ 1.6 MHz: 1 microvolt) for 10 dB S+N/N AM Less than 0.5 microvolt (0.1 ~ 1.6 MHz: 3 microvolts) FM* Less than 0.3 microvolt for 12 dB SINAD (1.6 ~ 30 MHz) SSB, CW, RTTY 2.3 kHz at ~6 dB (adjustable to 500 Hz min) 4.3 kHz at -60 dB CW-N, RTTY-N 500 Hz at -6 dB 1.5 kHz at —60 dB AM 6 kHz at —6 dB (adjustable to 2.7 kHz min} 15 kHz at —50 dB FM* 15 kHz at —6 dB 25 kHz at —60 dB More than 60 dB More than 3 watts 8 ohms Specifications are approximate and are subject to change without notice or obligation.SECTION 2 CONTROLS AND THEIR FUNCTIONS FRONT PANEL @ DIMMER SWITCH @ SCAN START/STOP BUTTON @ S-METER @ AGC TIMING SWITCH @ NB TIMING SWITCH @ NB LEVEL CONTROL: @ NOISE BLANKER SWITCH © MODE SELECT SWITCHE © POWER SWITCH @ FUNCTION KEY @ PHONES JACK @ RECORDER JACK PREAMP/ATT SWITCH: @ AF GAIN CONTROL @ RF GAIN CONTROL @© FILTER SWITCHES @ SQUELCH CONTROL @ TONE CONTROL MODE SELECTIVE SCAN SWITCH @ REMOTE CONTROL SWITCH 1. NB LEVEL CONTROL Controls the threshold level of the noise blank- er. Adjust the controls so that incoming noises will be eliminated. 2. NB (NOISE BLANKER) SWITCH When pulse-type noise such as automobile ignition noise is present, push this switch in. The noise will be reduced to provide comfort- able reception. 3. NB TIMING SWITCH The noise blanker blanking time can be selected (NORMAL and WIDE) by this switch. It will be effective against any types of noise. 4. AGC TIMING SWITCH For changing the time-constant of the AGC (Automatic Gain Control) circuit. By setting this switch to the slow position, the AGC voltage is released more slowly. Set the switch to provide comfortable reception. When the switch is at the OFF position, the AGC function is turned OFF and the S-meter does not move even if a signal is being received. (The AGC does not actuate in the FM mode.) 5. MODE SELECT SWITCHES Any one of five operating modes can be selected by simply pushing the desired switch. Additionally, the AM switch has dual func- tions, as follows. @ FREQUENCY DISPLAY ~ @ VFO SWITCH @ VFO EQUALIZING BUTTON @ FREQUENCY TRANSFER BUTTON @ SPEECH SYNTHESIZER SWITCH @ REMOTE CONTROL ENABLE INDICATOR @ REMOTE CONTROL SENSOR WINDOW @ KEY PAD @ MEMORY WRITE/CLEAR BUTTON @ PBT CONTROL @ NOTCH FILTER CONTROL @ NOTCH FILTER SWITCH @ MEMORY CHANNEL SELECT SWITCH @ VFO/MEMORY SWITCH @ DIAL LOCK SWITCH @ BAND SELECT FUNCTION SWITCH @ TUNING RATE SWITCH @ TUNING CONTROL 1.AM_ For AM operation. [Link] By pushing the FUNCTION key first, then the AM switch, the FM mode is selected. . POWER SWITCH This switch is a push-lock type switch which controls the input AC power to the set. When the switch is pushed in and locked, power is supplied to the set. When the switch is pushed again and released, the power to all circuits is cut. . FUNCTION KEY Increase the function of the AM MODE SELECT and the MEMORY WRITE switches by pushing this key switch first. . PREAMP/ATT (Attenuator) SWITCH Switches RF preamplifier and attenuator in the PF circuit. When the switch is at the OFF position, both preamplifier and attenuator are removed from the circuit, and incoming signals will be fed to the receiver directly. When using a small antenna or receiving a weak signal, set the switch in the “PRE” position; the preamplifier is inserted in the RF circuit and provides higher sensitivity. When nearby signals interfere with reception, or when receiving a very strong signal, set this switch to the “ATT” position. This removes the10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. preamplifier from the circuit and inserts the attenuator into the circuit. This gives about 20 dB attenuation. For normal operation leave this switch at the “OFF” position. FILTER SWITCH Selects one of the second IF (9 MHz) filters to improve the selectivity. PHONES JACK Accepts a standard 1% inch headphone plug for headphones of 4 ~ 16 ohms. Stereo phones can be used without modification. RECORDER JACK Accepts a 3.5 mm mini plug for a tape recorder to record receiving signals. The output is a fixed level regardless of the position of the AF GAIN control. AF GAIN CONTROL Controls the audio output level. Clockwise rotation increases the level. RF GAIN CONTROL Controls the gain of the RF section. Clockwise rotation gives the maximum gain. As the control is rotated counterclockwise, the needle of the METER rises, and only signals stronger than the level indicated by the needle will be heard. SQUELCH CONTROL Sets the squelch threshold level. To turn OFF the squelch function, rotate this control com- pletely counterclockwise. To set the threshold level higher, rotate the control clockwise. TONE CONTROL Controls the receiver audio tone. Adjust the control to provide comfortable reception. DIMMER SWITCH By pushing this switch in, the intensity of the meter illumination and frequency display is reduced. Use this in the dark to prevent glare. SCAN START/STOP BUTTON Starts and stops any of the scan functions. When depressing it again to restart the scan, it will start from the stopped frequency in the programmed scan, or from the highest mem- ory channel in memory scan. MODE SELECTIVE SCAN SWITCH When this switch is pushed, only memory channels stored the operating mode which is displayed on the frequency display just prior to pushing this switch are selected by turning the tuning control or scanning. REMOTE CONTROL SWITCH Switches the optical remote controller circuit (option). When this switch is pushed in and locked, the remote controller circuit will be turned on and the REMOTE CONTROL EN- ABLE INDICATOR will illuminate. TUNING CONTROL Rotating this control clockwise increases the frequency or the memory channel number, while rotating it counterclockwise decreases it. The frequency changes by 10 Hz in any mode. If, at the 10-Hz step tuning rate, the tuning 21. 22. 23. 24. 25. 26. 27. 28. 29 control is turned faster, the 50-Hz step tuning rate is automatically selected. This makes it very convenient to change frequency quickly over a wide range. This control is also used to select the operat- ing band while the BAND SELECT FUNCTION switch is depressed. TUNING RATE SWITCH By pushing in this switch, the operating fre- quency is changed to correspond to 1 kHz increments in any mode. At the same time, the 100 Hz digit on the display is cleared to show “0”. When this switch is pushed again and released, the fre- quency is changed normally. This switch allows you to quickly change over a great frequency range. BAND SELECT FUNCTION SWITCH By pushing in this switch, the operating band is changed by turning the TUNING CONTROL. The operating frequency is changed in 1 MHz steps but the lower digits do not change. VFO/MEMORY SWITCH Switches between VFO operation and MENM- ORY CHANNEL operation. DIAL LOCK SWITCH After the IC-R71 is set to a certain frequency by pushing the DIAL LOCK switch, the VFO is electronically locked at the display frequency, thus inactivating the operation of the tuning knob. To change frequency, the dial lock must first be disengaged by pushing and releasing the DIAL LOCK switch again. MEMORY CHANNEL SELECT SWITCH Selects any one of 32 memory channels in the MEMORY CHANNEL operation. The selected channel number is displayed on the frequency display. By turning the switch clockwise, the channel number is increased, and when coun- terclockwise is decreased. MEMORY WRITE/CLEAR BUTTON By pushing this button, the displayed frequen- cy and selected mode are stored into the memory channel which is selected by the MEMORY CHANNEL SELECT switch. By pushing the FUNCTION KEY first and then this button, the secondary function is selected and the memorized frequency and mode in the displayed memory channel will be cleared. NOTCH FILTER SWITCH Switches the notch filter function ON and OFF. P.B. TUNE (PASS BAND TUNING) CONTROL Allows continuous tuning of the pass-band selectivity by moving the filter up to 800 Hz from the upper or lower side in SSB, CW and RTTY. Not only improves selectivity, but also can improve the audio tone. Normal position is in the center (12 o'clock) position and is 2.3 kHz wide in SSB. NOTCH FILTER CONTROL Shifts the notch filter frequency. Adjust the control so that interference is reduced.30. 31, 32. 33. 34. 35. FM AM CW USB LSB KEY PAD There are ten numerical keys, and the cancell- ing and entering keys for setting an operating frequency. SPEECH SYNTHESIZER SWITCH When the optional speech synthesizer unit is installed, this switch turns on the unit which announces the displayed frequency in English. FREQUENCY TRANSFER BUTTON In the VFO operating mode, the frequency and mode stored in a memory channel (channel number displayed on frequency display), are transferred to the selected VFO. VFO EQUALIZING BUTTON Instantly sets the frequency and mode of a VFO to the same as those of the other VFO. VFO SWITCH Selects either VFO, “A” or “B”, for tuning. Each push of this button selects VFO A and B alternately. FREQUENCY DISPLAY B @ “RTTY' NM OoOodoodo aa Um ee ee De ee Pe SIG SCAN VFO A VFO By | --J 7 , ~, &) I € @ The frequency of the IC-R71 is displayed on a luminescent display tube. Since the 1 MHz and 1 kHz decimal points are displayed, the fre- quency can easily be read. The frequency indicated is the carrier frequency of each mode, USB, LSB, CW, AM and FM, and the mark frequency in RTTY. 36. 37. 38. The FREQUENCY DISPLAY shows not only the operating frequency but also the mode, selected VFO or memory channel, and SCAN mode. @ Shows operating frequency in 6 digits between 10 MHz and 100 Hz. Shows selected VFO: VFO A or VFO B. Shows operating mode: FM, AM, CW, USB, LSB or RTTY. Shows whether the set is in the MEMORY CHANNEL MODE or not, and the selected memory channel number. When the set is in the MEMORY CHANNEL MODE, “M ch” is displayed here. () Shows that the set is tuned to an incom- ing signal frequency within 1 kHz in the FM mode. At this time, “TUNE” is display- ed here, (if optional FM unit is installed). © Shows that the squelch is opened. When the squelch is opened, “SIG” is displayed here. @ Shows that the set is in the SCAN mode. When the set is in the SCAN mode, “SCAN” is displayed here. S-METER Signal strength of an incoming signal is indi- cated on a scale of S1 ~ S9 and S9 to $9+40 dB, and a linear scale divided into five. REMOTE CONTROL ENABLE INDICATOR lIluminates when the REMOTE CONTROL SWITCH is pushed in. REMOTE CONTROL SENSOR WINDOW An infrared sensor is installed under this win- dow. This sensor detects infrared rays emitted from the optical remote controller to control the operating frequency, mode audio volume, speech synthesizer, etc. ® ©®&REAR PANEL @ SCOPE TERMINAL @ LOW BAND ANTENNA TERMINAL (ANT 1) 41. MUTE TERMINAL When you wish to use the set together with a transmitter or transceiver, ground this terminal in the transmit mode, and the set is muted. EXTERNAL SPEAKER JACK When an external speaker is used, connect it to this jack. Use a speaker with an impedance of 8 ohms. When the external speaker is connected, the built-in speaker does not func- tion. FUSE HOLDER This holds a fuse for the AC power circuit. If the fuse is blown, replace it with a new 1A fuse for 100/117V operation, or 0.5A fuse for 200/ 220/235V operation after checking the cause. Open the fuse holder with a Philips-head screwdriver. AC POWER SOCKET For connection of the supplied AC power cable. LOW BAND ANTENNA SWITCH Switches the low band (1600 kHz and below) antenna terminals: ANT 1 (@ LOW BAND ANTENNA TERMINAL) for a high impedance antenna such as a long wire antenna, and ANT 2 (@ 50 ohm ANTENNA CONNECTOR) for a 50 ohm coaxial cable. SCOPE TERMINAL This terminal brings out the 70.4515-MHz IF signal from the mixer in the receiver. Not only observation of the received signal, but also the signals of a selected band width is possible by using a panadaptor or panascope. @ GROUND TERMINAL @ ANTENNA CONNECTOR (ANT 2) @ LOW BAND ANTENNA SWITCH @ RECORDER CONTROL TERMINAL 47. @ FUSE HOLDER @ EXTERNAL SPEAKER JACK @) MUTE @ OPTIONAL CONNECTOR POSITION (PLATE B) @ AC POWER SOCKET RECORDER CONTROL TERMINAL This terminal is grounded when the squelch is opened. This can be used to contro! a tape recorder so that the recorder works only when the squelch is opened and a signal is received. LOW BAND ANTENNA TERMINAL (ANT 1) For connection of a low band antenna to receive 1600 kHz and below. When the operat- ing frequency goes to 1600 kHz and below, the antenna terminal will be changed from the @ ANTENNA connector to this terminal auto- matically (when the @ LOW BAND ANTENNA SWITCH is set at the ANT 1 position). ANTENNA CONNECTOR (ANT 2) This is used to connect the antenna to the set. Its impedance is 50 ohms and connects with a PL-259 connector. GROUND TERMINAL To prevent electrical shock and other prob- lems, be sure to ground the equipment through the GROUND TERMINAL. For best results use as heavy gauge wire or strap as possible and make the connection as short as possible. OPTIONAL INTERFACE UNIT CONNECTOR POSITION (PLATE B) This position is provided to install the connec- tor of the optional interface unit. TERMINAL INTERFACE UNITSECTION 3 INSIDE VIEWS MAIN UNIT Crystal filter (9M15A) SSB ceramic filter (CFJ455K5) Notch filter crystal AM ceramic filter (CFW455IT ; Installation position for FM unit P.B.T. local oscillator circuit pr Filter switch * When optional filter is installed, slide this to the left SSB crystal filter (FL-30) SSB (wide) crystal filter (FL-70) BFO circuit Voltage regulator (79M08) AF gain tone control (AN829) AF power amplifier (uPC1181H) Noise blanker circuit 2nd mixer DBM Display driver (uPD549C) * Don’t tamper with the rotable coil cores, trimmer capacitors, trimmer resistors, etc. RF UNIT 1st LO buffer (2SC2053) Recorder remote control relay Band-pass filter switch (BA618) fof enol) Naa) ; Crystal filter (70M15B) IE Mf vane eee Mens RF preamp (2SK125 x 2) a en EE a aeBOTTOM VIEW Power supply unit DC line fuse (2A) Voltage regulator (¥A7805) Scan speed adjust (R14) RAM unit Lithium back-up battery Custom-made CPU input control IC (RP5G01) VO expander IC Frequency calibrator DC-DC converter Scan stop function switch Scan clears at Brake adjustment screw stopping {o }+ Timer ON PLL UNIT Programmable divider (M54929) Programmable divider (M54929) Reference frequency crystal _ 3 wean eee T (30.72 MHz) e Main-loop VCO circuit Divider (74LS90) : PLL mixer (uPC1073H) Sub-loop VCO circuit Voltage regulator (uA7805)= < oc oO < a “ o ° ond a vt 2 ° & lu ” 1 a | LOdNt ' AO! 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RF Circuits Signals (100 kHz ~ 30 MHz) from the ANT (2) terminal pass through the filter (A), and are divided into 100 kHz ~ 1.6 MHz and 1.6 MHz ~ 30 MHz. Frequencies of 1.6 MHz and below are fed to one of the two low-pass filters. Frequencies of 1.6 MHz and higher pass through the filter (B), and are fed to one of the nine bandpass filters. Filter (A) is a 5-element Chebyshev low-pass filter which attenuates frequencies of 30 MHz and higher by about 40 dB. This serves to improve the image ratio, and to reduce the 1st local oscillator signal (70.4515 ~ 100.4515 MHz) radiation from the antenna terminal. Filter (B) is a high-pass filter which attenuates frequencies of 1.6 MHz and below. This is in order to reduce intermodulation distortion caused by strong broadcast signals, which are in the 1.6 MHz range and below. Note that the above-mentioned filters are selected for an operating filter band according to the band data output from the logic unit. In addition, a high-impedance antenna, such as a wire antenna for 1.6 MHz and below, connected to the ANT (1) terminal, can be switched by $1 (antenna switch). : Signals which have passed through filters are fed to the preamplifier or attenuator. This switching is by the PREAMP/ATT switch on the front panel. When the setting is to the PRE AMP position, the signals are fed to the broad-band amplifier (composed of 03 and Q4) and amplified about 10 dB. When the signals are 1.6 MHz and below, they are by-passed the preamplifier (THROUGH) in order to reduce intermodulation distortion generated at the following stage, mixer, by strong signals. When the setting is to the ATT position, the signals are fed to the T-type attenuator (composed of R22 ~ R24) which attenuates the signals about 20 dB. 5-12. 1st IF Circuits Signals which have passed through the preamplifier or attenuator, or fed directly, and the 1st local oscillator signal (70.4515 ~ 100.4515 MHz) buffer-amplified at O7 are fed to the 1st mixer. The 1st mixer employs a DBM (double-balanced mixer), composed of Q9 and 010, FETs, which feature, compared to the diode type, superior multi-signal characteristics, low conversion loss, etc. The signals converted by the 1st mixer to the 70.4515 MHz IF pass through the FI 1 (+7.5 kHz, —3 dB) MCF (monolithic crystal filter), and are amplified by the Q8 dual-gate FET. Note that AGC is applied at the second gate. The amplified signals pass through J4 and are fed to the main unit. MAIN UNIT 1. 2nd ~ 4th IF Circuits The 70 MHz band ist IF signals input from P1 pass through the T-type attenuator (composed of R1 ~ R3), are mixed by the IC1 double-balanced mixer with the injected 2nd !ocal oscillator signal (61.44 MHz), thereby converting them to the 2nd IF (9.0115 MHz). The signals converted to the 2nd IF pass through the NB gate (composed of D6 ~ D9) and, after amplification by 08, pass through the filter (Fl1 ~ FI3) corresponding to the reception mode and are then amplified by Q9. The amplified IF signals are mixed by Q10 with the 3rd LO (9.4665 MHz+ pass band tuning change) oscillated by Q11 and X1, and are then converted to the 3rd IF (455 kHz + pass band tuning change). Pass band tuning is accomplished by varying the 3rd IF signals by 3rd LO of the degree of multiplicity of the 455 kHz filters (Fl4 and FI5) and the 9 MHz filters (FI1 ~ FI3). Signals to the optional FM unit are taken out as broadband signals without change by connector J10 prior to the 455 kHz filter. SSB, CW, RTTY and AM signals which have passed through the 455 kHz filter are led to the IC2 double-balanced mixer. They are mixed with the 3rd LO (9.4665 MHz + pass band tuning change), the same one for Q10, and then become the 4th IF (9.0115 MHz + pass band tuning change). They are then led to the notch filter (composed of L17, L18, D54, and X2). Because this js a crystal filter, IF band characteristics are not lost and deep attenuation is obtained. A bias voltage provided by the “NOTCH” control (on the front panel) is applied to D54 to change the notch frequency. Note that the variable width is +1.3 kHz. Signals which have passed through the notch filter have, at FI6, the spurious components (which were generated by mixer IC2) removed; then, after amplification at Q21 and Q22, are tuned at L26, and are divided into three parts and led to the detectors. The signals are then led as follows: C102, AM detection circuit; C105, SSB and CW detection circuit; and from L26 secondary side to the AGC detection circuit. 2. AF Circuits SSB, CW and RTTY signals led to IC4 through C105, are mixed with BFO signals, and are detected. AM signals input to D63 through C102, are detected, and are amplified at 026. Note that, during any mode other than the AM mode, Q25 performs switching, and detection by D63 is stopped. During the AM and FM modes, BFO is stopped by 014, D31, D32, D34 and D35, and is not output to IC4. Signals detected by the optional FM unit pass through J9 and are led to Q27. Squelch is applied by Q27 to detection signals, and, by varying the 0 ~ 4V control voltage of the IC6A electronic-attenuator by using the “AF GAIN” control {on the front panel), a volume change of approximately 80 dB can be obtained. Moreover, tone control is also accomplished by using the frequency compensation terminal (pin 2). Note that IC6B is used as a buffer amplifier, and the AF OUT signal is taken for the REC terminal on the front panel. The output of IC6A is amplified at IC7 and is led to the speaker. 3. Other circuits (a) Noise-bianker circuit In order to make it possible for both high sensitivity relative to noise and high input characteristics to coexist, a dual-gate MOS-FET is used in the first stage (Q1) of the noise amplifier, and a dual transistor is used as a differential amplifier (Q2) in the next stage, leading signals to Q3. Because AGC is applied to Q1 ~ Q3, a stable noise-blanking effect is obtained throughout a wide range of noise levels, from low-level noise to strong noises. Especially with regard to pulse noises, by setting the AGC attack time-constant and delay time-constant longer than previously, operation is possible in a wide dynamic range (over 100 dB) without saturation of the noise-amplifier circuit.Noise signals from Q3 are divided in two after rectified at D2 and D3, and one part controls, by Q5, the AGC line of the noise-amplifier circuit. As a result, the output level of the noise-amplifier circuit is maintained at a fixed level, and there is a sufficient time-constant for “woodpecker noise”, etc. Noise signals rectified at D2 and D3 are applied to the Q4 base. Q4 is switched ON only when pulse noise voltage is higher than Vee + Ve voltage, and 8V is then output from the Q6 collector. The blanker level can be adjusted by varing the 04 emitter voltage i.e., Q4 comparate voltage by the “NB LEVEL” control (on the front panel). Q7 is for blanking time control; when the noise-blanker timing switch (on the front panel) is set to “narrow”, the maximum blanking time is approximately 1 msec.; when it is set to “wide”, the time is approximately 5 msec., thus preventing distortion in receiving audio. (b) Filter select circuit D47 ~ D53 and D72 are turned ON, respectively, according to the mode signals input from J12 and J13, and according to the position of the filter switches on the front panel. One of the gates of IC3 is turned ON, by input data from pins 9 ~ 11. That output voltage is applied to the appropriate diodes of D36 ~ D42 to select the desired filter. In the FM mode, C3 pin 1 and pin 4 are turned ON by the filter switches (on the front panel), but, because they are not connected to any diode, and the filter selection does not change. IC3 input/output relationships by mode Input pin Mode Output pin i 10 Normal ! L 14 Wide 3 * Narrow Normal Wide * Narrow Normal Wide * Narrow * If option filter switch ($1) is ON DURING SSB/CW/RTTY FL-70 |/}—_______—J CF W455 IT —- Wide Norma! FL-30 O7reO ! " Wide ' NGrral jormal 1 Narrow y CFJ455K5 f jarrow of I FL-32 / , {Option| | f / Bo a DURING AM ——— [7 + CFW455/T 4 i ; Wide Wide —— Normal | 1 Notnal fo _ Ne { FL-70 + Ot 1 OF J455K5 +— Ow Narrow_, It ' ' | i Fi-32 | {Option} Lo eH eFilter Table No. 6 dB band | 60 dB band IF width width Insertion loss Application SSB Approx. During normal reception ceramic filter 455 kHz 2.8 kHz CFJ455K5 (SSB, CW, RTTY, AM modes) 4.5 kHz or less} 6 GB or less AM ceramic filter During wide reception (SSB, CFW455!T CW, RTTY, AM modes) 455 kHz Approx. 6 kHz / 15 kHz or less | 7 dB or less Standard 2.3 kHz or 4.2 kHz or more less During normal reception 6 dB or less (SSB, CW, RTTY, AM modes) FL-30 SSB filter 9.01315 MHz During wide reception (SSB, 5 kHz or less | 6 dBorless | CW, RTTY modes) and nor- mai reception (AM normal) SSB 2.8 kHz or wide filter 9.0115 MHz more During narrow reception pee rade filter| 405 kHz 2.4 ke °F | 4kHzor less | 6dBorless | (SSB, CW, RTTY, AM mode) gn-g for sharp characteristics Narrow-band filter for CW and RTTY 500 Hz or 1.6 kHz or CW filter 9.0106 MHz more Jess 8 dB or less 250 Hz or 1.1 kHz or more less Super-narrow-band filter for CW narrow filter) 9.0106 MHz CW and RTTY 12 dB or less {c) AGC circuit After signals output from the L26 secondary side are detected at D70, the detected voltage is controlled by 024 and Q19, and AGC voltage is output from the Q19 emitter to the 2nd gates of the IF amplifiers. During no signal, the AGC voltage is offset to the voltage (approx. 4V) set by R107 and R119. When a signal is received, 024 and 019 are switched ON, AGC voltage is decreased, and thus the gain of each amplifier is decreased. The AGC time-constant; the attack time is set by R106 and R206, and the release time is set by R105 and R206. And, for full break-in, Q23 is switched ON by a voltage through D60 during transmission in order to prevent the receiver from being blocked when switching from transmit to receive. (d) S-meter circuit and squelch circuit AGC voltage fed to IC5A pin 2 is inverted and amplified, resulting in wide dynamic range and high linearity of S-meter operation. A part of the S-meter voltage is fed to IC5B pin 6, and this squeich comparator circuit performs an excellent squelch operation even for modes other than FM. Note that 030 and Q31 are the circuit to produce squeich voltage. (e) BFO circuit The BFO frequency is shifted according to the mode by the mode signal supplied through J12. The BFO is oscillated by Q15 with X3 or X4 and buffer amplification at Q16, after which the signals are led to IC4. (f) Other IC8 produces a regulated 8V for supply to each section. D69 and Q32 ~ 034 are provided to produce T8V for use with a transmitter. T8V is used to mute the receiver operation, and is controlled by the signal from the SEND terminal. Q28 stops 09 operation by the mute signal from the PLL. 035 and Q36 are a circuit which, during AM, moves the notch frequency to outside of the pass-band.PLL UNIT This unit is composed of the 1st LO circuit and the 2nd LO circuit of the receiver. The 1st LO oscillates 70.55 ~ 100.45 MHz range with two locked loops and the 2nd LO oscillates a fixed frequency at 61.44 MHz. 1. Reference oscillation circuit The standard reference oscillator output (30.72 MHz) is used for the local oscillatior signal for a loop, for the reference frequency of the main and sub loops, and for the 2nd Local Oscillator. For the reference frequencies for the PLL loops, the main loop reference frequency is 10 kHz, and the sub loop reference frequency is 5 kHz. Because the respective frequency-dividers (IC1 and IC201) are 1/1024, the standard reference oscillation frequency is divided into 1/3 (10.24 MHz) by IC5, and then divided into 1/2 (5.12 MHz) by IC203 is supplied to the sub loop. The main loop uses the output (10.24 MHz) of IC5 as it is, without change. 2. 2nd local-oscillation circuit After the standard reference oscillator output (30.72 MHz) is multiplied by 2 at 014, the 61.44 MHz from which spurious has been sufficiently removed at L3 ~ L65 filters is supplied to the 2nd mixer. Note that the output level is approximately 3 dBm/500. In addition, the muting signal during unlock, etc. is applied to Q13 to shunt the signal. CMAIN LOOP tet LO DATA VCO OUT N-3960~6950 = Sv1i0,1~8MHz) : 70.5515~ 78.451 5MHz OSUB LOOP 2V218~15MH2) | 78.4515~85.451 5MHz o1~Q4 DATA DV3(15~22MH2) :85.4515~92.451 5MHz 1/1024 DATA from LOGIC 30.950~ 30.95999MHz 30 72MHz 1/10+1-11SW C4 30 72MHz 10. 24MHz 230~ 239.99KHz MAIN LOOP Q201 \C204 115~ --- ee ee OL Le. C201 119.99MHz PROGRAN- MABLE DIVIDER CONTROL COUNTER IC202 woe i SWALLOW COUN TER3. Main loop The main loop, which is the output for the 1st LO, is a composite of mixed down and divided method. Note that the VCO output frequency (F,) is obtained from the following formula. Fy = Fio + N x Fref Frequency changes are made by changing Fo and N. The reference frequency (Fref) is 10 kHz, and, VCO is controlled in 10-kHz steps by changing the frequency-division ratio N of the programmable divider. Frequency between this step (less than 10 kHz) is obtained by Fg which controls the VCO. Note that Fro is changed 9.99-kHz range in 10-Hz steps, and in this way the 30-MHz range of the PLL overall can be varied in 10-Hz steps. Reference C1 Q5~07 Q18~921 Q22 frequency LOOP BUFF Ist LO Fel FILTER (1OKHz) C1 IC2 (Pulse swallow method) 016,017 PROGRAM- MABLE DIVIDER N DATA Fro 3960 ~ 6950) Loop internat LO (a) PLL ICs 1C1 (M54929P) is a multi-function IC with built-in phase comparator, programmable divider, reference- frequency divider and swallow-counter controller. In combination with the IC2 (M5466L) swallow counter, pulse swallow frequency division is possible. This method makes a large frequency-division ratio possible, so that it functions as a programmable divider which can be used up to higher frequency. Compared to previous models, it has a small configuration, and 10 Hz steps PLL output can be obtained. (b) Loop filter and muting circuit The phase detected signal from IC1 is fed to the Q6 and Q7 active loop filter. The loop filter is important to the PLL, together with the VCO, and determines lock-up time and C/N (Carrier Noise ratio). These two have a conflicting relationship: if the time-constant of the loop filter is set so that the lock-up time becomes faster, the C/N deteriorates. In order to solve this problem, the PLL in this unit has an FET (Q5) at the loop filter. The result is that, when the frequency suddenly changes more than a certain degree, the time-constant of the loop filter is made smaller and lock-up time becomes faster. Note, however, that usually the time-constant is large and C/N is improved. In addition, 05, which changes the time-constant, is driven by the muting signal. The muting signal converts the lock signals (output from IC1 (pin 8) of the main loop and IC201 (pin 8) of the sub loop) to the appropriate time-constant and voltage at Q8 and O9, and these are supplied to O5. These signals are also led to 013 and Q24, and they switch the output amplifier base, stopping the 1st LO and 2nd LO outputs. When these operations unlock the PLL or cause a large frequency movement, or reception on unwanted frequencies is prevented and, at the same time, lock is applied quickly. (c) VCO circuit Because VCO performance is critical to the PLL, and in order to obtain a high C/N and stabilized oscillation output, the VCOs are divided 4 segments, so that the frequency coverage for any one VCO is suitable. The VCO power supply is, in the same way as the reference oscillation circuit, provided with double stabilization by the 5V zener diode; a coreless coil is used for the oscillation coil, thus giving a high Q and also suppressing external induction. This circuit features a carefully planned pattern (earth point and components layout) and a strong shielding case for an excellent C/N characteristic. 5-6(d} Loop system The VCO output passed through the Q22 buffer amplifier is divided in two. One part is amplified at 023, and, after impedance conversion at 025, is output to the RF unit as the 1st local oscillator signal. Note that the output level is approximately 0 dBm/50Q. The other part passes through the Q26 buffer amplifier and is fed back to the PLL loop. This buffer amplifier employs a grounded base circuit with high isolation so that the signals in the PLL loop don’t leak into the 1st local oscillator signal as spurious. This VCO signal is mixed with the local oscillator signal from the sub-loop at [C3 and is mixed down. This signal passes through the band-pass filter (band width approximately 35 ~ 75 MHz), and, after spurious is removed, is amplified to the necessary level at the Q16 and 017 cascade amplifier and is input to IC2, forming the locked loop. The D10 and D11 limiter is used at the C2 input in order to prevent over driving. (e) Local oscillator circuit The local oscillator is provided to mix down the VCO signal and obtain the 10-Hz step tuning. Because the sub loop output (230.00 ~ 239.99 kHz) is too low as the LO frequency, it is mixed with the reference oscillator signal (30.72 MHz) at IC4. Spurious is removed from the mixed signal (30.950 ~ 30.960 MHz) at the monolithic filter (FI1), after which the signal is amplified at Q15 and then fed to IC3, the main loop mixer. iC4 FIT(MC.F} Q15 REF. osc Q10 4. Sub loop This loop is the divider type locked loop, and is used to produce 10-Hz steps LO signals. The VCO locks the range of 4.995 MHz (from 115 ~ 119.995 MHz) in 5-kHz steps. This signal is divided into 1/500 at 1C204 and IC203, to obtain a signal to change the range of 9.99 kHz (from 230 ~ 239.99 kHz) in 10-Hz steps, and is supplied to the mixer in the main loop. A part of the VCO signal is fed to 1C202, the swallow counter. This output is fed to the PLL IC, IC204, and then the loop filter, to lock the VCO. This uses the pulse swallow method by the combination of IC204 and IC202 (the same as the main loop). And, by changing the frequency-division ratio of the programmable counter, the frequency is changed. Note that the 5.12-MHz input from IC203 is divided into 1/1024 as the reference frequency (5 kHz) by the divider inside IC204. 116~ IC204 119.99MHz Q202 i ' 1 LOOP ; FILTER 4 1C203:1/2 PROGRAM- MABLE SWALLOW / © Main loop | f I 1 ; COUNTER DIVIDER 230~239,99KHz t t 15. PLL data The data for setting the frequency-division ratio (“N") of the programmable divider and the VCO switching signal are fed from the logic unit; the former is supplied by the dynamic method and the latter by the static method. Because IC1 can also vary the frequency-division ratio of the reference-frequency divider, that data (fixed at 1/1024) is also supplied at the same time. (a) How N data are obtained The set employs two locked loops, thus two types of N data are necessary, and, even if the PLL output frequencies are the same, the display frequency differs according to the operating mode. Note that LSB and FM are the same; for RTTY and CW, the display frequency shifts —600 Hz; for AM it shifts — 1.5 kHz; and for USB it shifts +3 kHz. For LSB and FM, the N data can be obtained by the following formula. Example: 14.075 MHz Main loop The 10 kHz and upper digits of the displayed frequency are used as F1. The formula is as follows: N = F1 x 100 + 3950 For the example frequency, N therefore becomes as follows: N = 14.07 x 100 + 3950 = 5357 Sub loop The 1 kHz and lower digits of the displayed frequency are used as F2. The formula is as follows: N = F2 x 100 + 23000 For the example frequency, N therefore becomes as follows: N = 5.00 x 100 + 23000 = 23500 Note that, in this case, the 10-Hz digit is not displayed. Calculation made by adding, to the display frequency, +600 Hz for RTTY and CW, +1.5 kHz for AM, or —3 kHz for USB. By providing the N data obtained as described above, the programmable divider frequency-division ratio becomes 1/N.LOGIC UNIT This handles processing for frequency control, BPF switching and mode setting, and producing data to the PLL unit, and data to the display unit, etc. It is composed of an 8-bit N-MOS CPU, a 4-bit x 1k-word C-MOS RAM, a multi-function custom IC, an I/O expander IC, etc. 1. CPU The CPU terminals operate to allot functions. In addition, the tuning and remote controls use the interrupt terminal! for priority handling. Ail peripheral devices including ROM and RAM, are allotted their addresses. The figures below show the allocation of CPU ports and the memory map. (See Fig. 1 and Fig. 2.} 2. CPU input control circuit This circuit is composed of a multi-function custom IC and the input matrix circuit. (For additional information concerning the input matrix, refer to the section concerning the matrix unit.) (a) Multi-function custom IC This is a C-MOS type 40-pin DIL package multi-function custom IC. The clock signals is obtained by an L and C externally connected to pins 18 and 19, and cause an oscillation of approximately 100 kHz. Pin 32, ATS, is used as a strobe signal for the tuning step of the input matrix. When the tuning control is rotated at a speed higher than a certain speed, ATS becomes H level. This switching point can be set by C6 and R7, which are connected to the pin 21 TC terminal. Pin 38 and pin 37, M1 and M2, function to determine the input pulse speed multiple of the tuning control. For this unit, 200 pulses per rotation is obtained at a speed multiple of 4 times 50 pulses. Note that the pin 2, pin 3, pin 33 and pin 34 RIT/XIT functions are not used on this unit. Fig. 1: CPU port allocation Fig. 2: CPU memory map 0000 9 ry Pp CPU INTERNAL ROM 4 . ADDRESS BUS 16 Up 15 — vce & +5V OF FF Bbit x 4096W - 2 0OuUT pe 14[Oo 14 ; Sloe? we 13182 is) 7F FF | REMOTE CONTROL 6 _- \o86 PE 12 ot 12 5 ~>5}p85 pe 11 oO 11 8FFO J 4 —~ 2/084 PE 1022-—»— 10 1 DATA BUS 58 2 3 > 4pa3 Peg o> 9 20 —+e 74082 peste.» 8 3 ’ +> +{pB1 pe 7 po 7 ADDRESS 4 | Input Ng . oe ono pe6ls—_»— 6 BUS 5 | Matrix REMOTE SRO —~'int2 PE 5{22 = 5 6 main oan —>— tants pe afSS _ g : 7 WSS AF nro pe 32 3 | 8 +5V) - > “Uwiit pe 2{5t »— 2 : 8FF9 as PE 1 fom 1 | 16] 49 / ; | WRITE STROBE <—--—-] WR PEO-———»>— 0 - QF FO | Display Data Out(#PD549e x 2) READ STROBE a pa 7 [48 18 47 _ . ueiPe? a — BFF9 | BPF (High) 1 4 4 ePcé PBS las A | BPF (Mid) vFoe- <« a Pc5 Pade B | BPF (Low) res Pear C | MODE (High) MEMORY READ -—+-— Sa PC3 PB2 a —>— CONT (PLL RESET D | MODE (Low) DIAL UP DOWN —= PC? P81 p> FUNC. LED E F 24 41 ALL. REMOTE DAV -—<— Sal Pct Pao BFFF | [Link] PERIPHERAL RESET =<——{PC0 Pa ?}—— -- —28lgeK pagp® oy 48 CFFF | PLL Data Out (M54929 x 2) —— 51 Pas 28} [37 _ F800 gelne Paar EXTERNAL RAM SYSTEM RESET 30 PETE PAs Iss 4bit x 1024W (# PD444C) xd — > x4 paar —— —- FBFF CLOCK < 31 34 . - pate — FF86 alt? 33 CPU INTERNAL RAM aoe 88 pao -— GND vss ° Sbit x 128W FFFF Fig. 3: Custom IC port allocation Wan 1 40 . +5 —-— vee sck>—-—— CLOCK 2 39 yMIC UP? DOWN INPUT RIT XIT oB1 = RUD SUOT - UP DOWN ! < 3 8 . DATA OUTPUT pg2 « aRee MIP MULTIPLIER SELECT MAIN DIAL | INTi —« - cK m2e = (MAIN DIAL INPUT) DATA OUTPUT”. pop —— S4up s1 PS 6 35 +MAIN DIAL SENSOR INPUT WRITE STROBE ——{WR s2--—~< 4a READ STROBE-> 480 sat 8 33 +RITOXIT SENSOR INPUT £0 ->—4DA $4 1 >». pp rs? » ars auro TS; 1 2-~ Yo yoRt. + ADORESS Bus J WM 30 3-0 yi INPUT 12 29 2 -—-HeA y 2 13 a cB ¥3 28. 14 27 14 —» —ec ¥ 4 4 MATRIX : PLL-CFFE «15x 4 ys o Y DATA OUTPUT PERIPHERAL | 16 25 ADDRESS BPF ETC.-BFXX = ——1K 3 yee > UT PUT | 4 ° ut LoiseLay-oFeD = — 4x4 v7 |S cuocej > Sleume vl22 2 ose oe ky yee ono = 2 ano Toft ATS THRESHOLD SET 5-93. I/O expander circuit This circuit provides the BPF, PLL-VCO and MODE data outputs. The relationship is shown in the table. Data output wo vu m“ PLL VCO Frequency 0.1 ~ 0.5 MHz 0.5 ~ 1.6 MHz 1.6 ~ 2 MHz 2 ~ 3 MHz 3 ~ 4 MHz 4~6MHz 6 ~ 8 MHz 8~ 11 MHz 11 ~ 15 MHz 16 ~ 22 MHz 22 ~ 30 MHz oon oarh Wn — = 2 = = 4. Display timing 8-digit data and load signals (8 CTL pulses) are fed, to the ICs (IC1 and IC2) for display drive of the display unit from J13 of the LOGIC unit. Note that the data of T; (IC1) and of Tp ~ T2 and T; ~ T; (IC2) are not used. These data for display are sent only for operations related to the display, such as when the frequency is changed, the memory channel is switched, etc. 5. N data Because the PLL has a 2-loop configuration, two types of N data, high (HA ~ HD) and low (LA ~ LD), are sent from logic unit J,, to the PLL unit. IC17 and IC18 are gate switches for data lines HA ~ HD and LA ~ LD. The data lines are commonly used for PLL, BPF, display, etc.; therefore, the switches are switched. When the data are sent to the PLL to prevent noises being mixed in the VCO. Display data timing Only 1 RESET pulse when power 200% | switched ON RESET So $3 So $3N data output timing a) HR LSB MSB HA High § | DATA HD (DBO~3) LA Low 4 DATA LD \ (oB4~7) Note: CPS pulse intervals are actual measured values (clock 4 MHz). High and low N data High N-DATA Low N-DATA Xx10M, x1M, x100K, x 10K x1K, x100Hz, x 10Hz Disp. freq. N-DATA Disp. freq. N-DATA 0.10MHz 3360 OHz 23000 0.11MHz 3961 10Hz 23001 0.12MHz 3962 20Hz 23002 0.13MHz 3963 50Hz 23005 0.14MHz 3964 100Hz 23010 0.15MHz 3965 1kHz 23100 1MHz 4060 2kHz 23200 10MHz 4950 3kHz 23300 20MHz 5950 4kHz 23400 30MHz 6950 5kHz 23500 9.99kHz 23999 *For FM mode; N data (with display frequency as standard)6. Other circuits (a) Scan circuit This circuit is composed of Q4, IC7b and R14, and is used to control the programmed scan, mode-selected scan, memory scan, etc. Note that R14 is the trimmer for adjustment of the scan speed. (b) Matrix unit This unit functions for handling signal relay between units and input matrices related to the front panel, and generating —10V DC supplied to the MAIN unit. The matrices used by this unit and their operations are as follows. Matrix table {C2 RP5G01 007 Yo Y 1 Y 2 Y 4 Y 5 Y 6 Y7 Y 9 TEN MEMORY Y -|---4 tsar aaa MODE |REMOTE| SCAN ilo it o4 SELECT| RP | CLOCK S NIN i i | 1 \ PITCH ; 2 j CLEAR \ AGUAS \ | ! 1 0B 1 9 oO a a wo YOCcOWOerHy FOYVC TBO VFO VFO NS \ IN dB 4 MEMORY XO 0B 5 08 6 DB 7 @ YO -» DBO ~ DB3 (TEN KEY) Sets frequencies by key entering of ten-key unit. @ YO -» DB4 (SCAN START/STOP) Used for start and stop of scan by SCAN switch.@® Y1— DB4 (VFO A/B) Matrix for VFO A/B switching; CPU pin 20 becomes high level at VFO B condition. @ Y1— DB5 (MEMORY READ) Matrix for VFO/M (memory) switching; CPU pin 22 becomes high level at memory read condition. ® Y2 — DB4 (VFO A = B) Matrix for VFO A = B VFO equalization; operation is as in table below for various FUNC (function) switch combinations. A=B FUNC +A=B When VFO A used VFO A— VFO B | VFOB-» VFOA When VFO B used VFO B— VFOA | VFOA~> VFO B © Y2 — DB6 (MW1/DISP -» MEMO) @ Y2 — DB7 (MW2/MEMO -— DISP) The above © and @® are matrices for memory operation by WRITE/CLEAR switch and M — VFO switch; operation is as shown in the table below. Note that a combination of FUNC switch and WRITE switch or M — VFO switch will erase unnecessary memory channel data, so that it becomes a blank channel. VFO/M SW. Operation Description WRITE VFO (A or B) data are entered into displayed memory channel. VFO A or VFO B M-— VFO Displayed memory channel data are entered into VFO in operation WRITE Displayed data are entered into memory channel in operation MEMORY-CH M- VFO Displayed data are entered into VFO immediately prior to switching to memory channel. Y4 — DBO (LSB) Matrix for LSB; I/O expander IC pin 19 becomes high level. @ Y4— DB1 (USB) Matrix for USB; I/O expander IC pin 20 becomes high level. Y4 — DB2 (AM) Matrix for AM; /O expander IC pin 31 becomes high level; becomes FM mode and I/O expander IC pin 22 becomes high level by combination with FUNC switch. @ Y4 — DB3 (CW) Matrix for CW mode; I/O expander IC pin 21 becomes high level; becomes CW narrow and I/O expander IC pin 32 becomes high level by combination with FUNC switch. @ Y4 —» DB4 (RTTY) Matrix for RTTY mode; I/O expander IC pin 33 becomes high level; becomes RTTY narrow and I/O expander IC pin 34 becomes high level by combination with FUNC switch. @ Y5 — DBO ~ DB4 (MEMORY CH.) Y5 data supplied by custom IC of logic unit are distributed by O08 ~ 012 of matrix unit to DBO ~ DB4 and a memory channel is selected. Memory channel Memory channel 10 11 12 13 14 15 16 t 32@ Y6 — DBO (MODE-SELECT SCAN) Matrix for MODE-S switch; memory-selected scan is available when a memory channel is selected and memory scan. @® Y6 — DB1 (PITCH CLEAR) Matrix for frequency steps clear input; currently used frequency steps and all below are cleared to “0” when TS switch is switched ON. @ Y7 — DBO (REMOTE RP) Matrix for remote-control read pulse. Y7 — DB1 (REMOTE WP) Matrix for remote-control write pulse. Y7 — DB2 (SQL) One pulse enters, only when squelch is ON, to identify squelch condition; used for control of each scan. @ Y7 — DB4 ~ DB7 (DIAL PITCH 1 ~ 4) Matrix for selection of frequency steps for distribution of Y7 data to DB4 ~ DB7 according to the TS switch setting; BAND switch has priority. Main dial 10-Hz steps (2 kHz/rotation) Becomes 50-Hz steps if turned quickly. 1-kHz steps (200 kHz/rotation) Display of 100 Hz and less cleared. Steps and BAND switching 10 Hz 50 Hz 1 kHz BAND @ Y9 — DBO Matrix for scan clock; clock input during scan @ Y9 — DB5, DB7 (10 sec. SET/TIMER SCAN) Used as matrix for 10-second timer when scan stop, and for timer ON/OFF switching. Note that scan stop switching (restart 10 sec. after scan stop) can be set by $1. (c) Display unit This unit is composed of the display tube and its driver, and the DC-DC converter. The fluorescent display tube (DS1) is driven by IC1 and IC2; the display shows the frequency, mode, memory channel, VFO A/B, scan, etc. by dynamic illumination. Note that IC1 and IC2 are ICs which include the functions of data latch, clock oscillation circuit, timing counter, segment decoder, etc. IC2 drives the memory channel display, and IC1 drives the other displays. C2 and C6 determine the timing of the clock oscillation circuit. The SIG signal, the TUNE signal and the DS1 and DSO signals for dimmer are fed from the matrix unit; other signals are from the logic unit; of these, the SCAN signal and RES signal are passed to the matrix unit. The {C3 voltage 3 regulator produces the +5V for IC1 and IC2; the DC-DC converter (composed of T1, Q1 and Q2) produces the —5V for !C1 and IC2 and the —35V for the display tube; the AC 3.5V for the display tube filaments is also taken out here. After Q3 ~ O5 are switched ON, —35V is switched at Q4, the display data latch signal (CTL) is sent from the logic unit, and the display tube is turned off for approximately 2 seconds until reset is completed. (d) REG unit After noise has been removed by the line by-pass capacitors (C1 and C2), AC voltage input from J1 passes through fuse F1, through the power switch of the front panel, and is input to step-down transformer T1.The AC voltage stepped-down by T1 is rectified with single-phase full-wave rectification by the D1 bridge-type rectifier. After the rectified output is smoothed at C7, it becomes direct current, passes through F2, and is led to the regulator circuit. The regulator circuit of this unit is the closed-circuit type. Output voltage is constantly monitored and, if there is a fluctuation, there is immediate feedback to the control circuit and the fluctuation is eliminated. If there is a drop of output voltage, when the Q3 base voltage (voltage divided by R4 ~ R6) drops, base current and collector current are also reduced at the same time. As a result, the voltage across R3 (connected to the emitter) drops, and the emitter and collector voltages also drop at the same time. As a result, Q2 base voltage drops and current is increased, and collector current is also increased. Consequently, Q1 base current is increased, collector current is also increased, and output voltage rises. When output voltage rises, operation becomes the opposite. Note that R2 functions to reduce the Q1 load. The regulated DC output is led to J2 and P2, passes through L1, through the front panel power switch, and is supplied to the unit. (e) Remote-control reception circuitry (ten key unit) This circuitry is composed of the high-gain amplification circuit, the detection circuit and the output waveform rectification circuit (on a 1-chip IC), and the receptor diode, level converter, etc. The IC1 output is negative polarity (high level during the no-signal condition), and is open collector output. Note that the output waveform is as shown below. Transmission output waveform 38-kHz carrier 1C1 output waveform +10VSECTION 6 DISASSEMBLY TOP COVER 20201 ) bottom cover. (6 set screws @ {Use a hexagonal wrench to remove the four knob Remove the top cover. (12 set scraws @) screws @.) 2. Remove the 3. Remove the frant panel control knobs, etc. is ox ¢ oD 5 Oe ao ~ 52 oo on o ef 5 oe $a oa Ew Cc 256 “= . 30 ee a 2: ce Sou Oo. Gs Ese S25 eve f 6-1FRONT PANEL PARTS SWITCH SUT111A6 SWITCH SUT110C2 SWITCH(1) BOARD B-862A 42620 SWITCH SUT111A7 ATT. PRE SWITCH SWL-43-16PS BUTTON K-16A 42299 BUTTON K-16(SILVER) 42299 POWER SWITCH SDS-3P AGC SWITCH SRU1023NC8 NB LEVEL CONTROL K12140055-1KB SWITCH SPJ222CB2 y es LS BUTTON K-6 42039 Xa "SD bod PHONES JACK LJ035-1-2 J > en st POWER SWITCH BUTTON K-16 42298 REC JACK HSJ0779-01A4 ATT. PRE BUTTON K-17 42300 (2 KNOB N-56B 42037 - FRONT DIECASTING 20154 KNOB N-65 42301 RIT CONTROL KNOB N-66 42 KNOB N-58A 42102 TUNING CONTROL KNOB N-6TEN KEY UNIT =~ FRONT DIECASTING 20154 —— KNOB N-65 42301 — RIT CONTROL KNOB N-66 42302 == KNOB N-58A 42102 —= TUNING CONTROL KNOB N-68 42392 DISPLAY BRACKET 42632 DISPLAY BOARD B-860A 42619 DISPLAY TUBE FIP9BM7 MATRIX BOARD B-867A 42625 SWITCH(3) BOARD B-864A 42622 SWITCH SUT110C2 SWITCH SUT111A7 BUTTON K-16A 42299 BUTTON K-16(SILVER) 42299 RF, AF CONTROL K16B10005-10KB-20KC SQUELCH, TONE CONTROL K16C20011-10KBX3 ENCODER LA24007 PBT BOARD B-865A 42623 MEMORY CH SWITCH SBU102C PBT, NOTCH CONTROL K12B60AOL-1 0KBX2 NOTCH SWITCH SPJ222CB2 WRITE CLEAR SWITCH SPJ222T43 BUTTON K-6 42039 SUB CHASSIS 30381CONNECTOR CONNECTIONS MAIN UNIT SET SCREW & SET SCREW = SET SCREW = 1 (A) 3x6 A) 3x6 7 (A) 3x6 M3Xx5 = 2 (A) (A) | COUNTERSUNK HEAD te. REAR PANEL 30382 [um : o OQ I { tT __ TO REAR PANEL | LEAD CLAMP LEAD CLAMP | J2, J5 | 69TC4772 59TCA772 | r=! = = = ! SET SCREW TO PLL UNIT (C) 3X6 TP a. 7 on rast SET SCREW SHIELDED CASE (C) 3x6 A JIT | (a) 41699 a, CHASSIS(L) J13 = = 20199 = 2 ( REG HEAT SINK Ls 42161 ? MAIN BOARD 18 B-858A Ks SET SCREW r 8 (C) 3X6 SET SCREW . f= J (C) 3x6 2 CHASSIS(C) SET SCREW 20198 (C) 3X6 _ TO WIRING HARNESS _ TO MATRIX UNIT J10, J13 TO MATRIX UNIT M3X5 M3X5 COUNTERSUNK COUNTERSUNK HEAD + HEAD + LL DISPLAY BOARD J ea — SUB CHASSIS B-B60A 9 | 30381 bo] FRONT DIECASTING 20154