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DES Decryption Process and Implementation

The decryption process of DES is essentially the same as the encryption process but uses the keys in reverse order. Feistel structure makes encryption and decryption similar processes by applying the keys in the opposite direction. The goal of the thesis was to demonstrate developing FPGA and ASIC implementations of an application initially described in hardware description language. It exercised the design flow with a variety of tools and constraints for an application requiring tens of thousands of logic gates.

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32 views3 pages

DES Decryption Process and Implementation

The decryption process of DES is essentially the same as the encryption process but uses the keys in reverse order. Feistel structure makes encryption and decryption similar processes by applying the keys in the opposite direction. The goal of the thesis was to demonstrate developing FPGA and ASIC implementations of an application initially described in hardware description language. It exercised the design flow with a variety of tools and constraints for an application requiring tens of thousands of logic gates.

Uploaded by

Abhi
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

The decryption algorithm of a block cipher should be identical to the encryption algorithm, step by

step but, in a reverse order. But in case of DES cipher, the encryption algorithm is so well designed,
that the decryption algorithm is identical to the encryption algorithm step by step in the same order,
only with the sub keys applied in the reverse order. Feistel structure makes encryption and
decryption similar processes.

The decryption process with DES is essentially the same as the encryption process and is as follows:
Use the ciphertext as the input to the DES algorithm but use the keysKi in reverse order. That is, use
K16 on the first iteration, K15 on the second until K1which is used on the 16th and last iteration

The goal of this thesis was to demonstrate the design flow for developing both FPGA and ASIC
implementations of an application initially described in a hardware description language. Exercising
the design flow with a variety of tools and constraints for an application requiring tens of thousands
of logic gates to implement is not a simple task. Documenting this effort can serve as a tutorial to
others. Many people wish to communicate privately. To prevent unauthorized persons from
extracting information from the communication channel or injecting misinformation into the
communication channel, messages need to be disguised by encryption. At the transmitter, the
plaintext is encrypted to produce the ciphertext. The ciphertext is transmitted over an insecure
channel to the receiver. The receiver then decrypts the ciphertext to obtain the original plaintext.
DES, which stands for Data Encryption Standard [17], is a block encryption algorithm adopted by the
National Bureau of Standards. With this algorithm, a 64-bit plaintext and a 64-bit key are provided as
input. By applying a sequence of initial permutation, switch, shift on the key and plaintext, the 64-bit
ciphertext is generated at the output after 16 clock cycles. The VHDL code to implement the DES
algorithm in this thesis was downloaded from the website [4]. The original code could not be
compiled with our toolset so the code was 1 CHAPTER 1. INTRODUCTION 2 modified and some parts
were rewritten to make the code synthesizable. It should be noted that the resulting VHDL code can
only be synthesized with the 1993 standard when using Synopsys synthesis tools. A test bench for
simulation is critically important for the final success of the whole work. The testbench code for DES
was found and downloaded from the web to verify each step of the implementation. This test bench
provides a sequence of keys and plaintext to the DES design, along with a sequence of expected
ciphertext. After each 16 clock cycles, the generated ciphertext from the output of the design is
compared with the expected ciphertext. If they are the same, the simulation succeeds and a success
message is reported. Otherwise, the simulation fails and an error message is reported. In that case, it
is necessary to go back to check the previous steps for errors. With the test bench, the pre-synthesis
simulation is then made using ModelSim. This is an RTL level simulation which verifies the logic
functionality of the code without gatelevel information involved. After the successful pre-synthesis
simulation, Mentor Graphics’s Leonardo Spectrum is used to synthesize the DES design with some
compile constraints applied to generate the EDIF (Electronic Design Interchange Format) file, which is
a FPGAindependent netlist file. The Xilinx Place & Route (P&R) tools take the EDIF file and implement
it in the targeted Virtex V1000ebg560 device. With the gate-delay and wiredelay information
obtained from the files generated during the P&R process, the post-layout simulation is made using
ModelSim again. Synopsys’s FPGA COMPILER II (FC2) is used as another synthesis tool to compile the
DES design to Vertex V1000ebg560 device. The two versions of implementation from Leonardo
Spectrum and FC2 are compared in layout, speed, and size, etc. The DES design is also synthesized to
a testable Standard-Cell-Based ASIC with TSMC18 process. Synopsys’s Design Compiler is used as the
tool to explore the design space to compile the DES design to different versions that are respectively
optimized to area, speed and CHAPTER 1. INTRODUCTION 3 power. Cadence’s tools are used to place
and route the designs to get the physical layout. Finally, the post-layout simulation is made again to
verify the implementation. The goal of this thesis was to demonstrate the design flow for developing
both FPGA and ASIC implementations of an application initially described in a hardware description
language. Exercising the design flow with a variety of tools and constraints for an application
requiring tens of thousands of logic gates to implement is not a simple task. Documenting this effort
can serve as a tutorial to others. Many people wish to communicate privately. To prevent
unauthorized persons from extracting information from the communication channel or injecting
misinformation into the communication channel, messages need to be disguised by encryption. At
the transmitter, the plaintext is encrypted to produce the ciphertext. The ciphertext is transmitted
over an insecure channel to the receiver. The receiver then decrypts the ciphertext to obtain the
original plaintext. DES, which stands for Data Encryption Standard [17], is a block encryption
algorithm adopted by the National Bureau of Standards. With this algorithm, a 64-bit plaintext and a
64-bit key are provided as input. By applying a sequence of initial permutation, switch, shift on the
key and plaintext, the 64-bit ciphertext is generated at the output after 16 clock cycles. The VHDL
code to implement the DES algorithm in this thesis was downloaded from the website [4]. The
original code could not be compiled with our toolset so the code was 1 CHAPTER 1. INTRODUCTION
2 modified and some parts were rewritten to make the code synthesizable. It should be noted that
the resulting VHDL code can only be synthesized with the 1993 standard when using Synopsys
synthesis tools. A test bench for simulation is critically important for the final success of the whole
work. The testbench code for DES was found and downloaded from the web to verify each step of
the implementation. This test bench provides a sequence of keys and plaintext to the DES design,
along with a sequence of expected ciphertext. After each 16 clock cycles, the generated ciphertext
from the output of the design is compared with the expected ciphertext. If they are the same, the
simulation succeeds and a success message is reported. Otherwise, the simulation fails and an error
message is reported. In that case, it is necessary to go back to check the previous steps for errors.
With the test bench, the pre-synthesis simulation is then made using ModelSim. This is an RTL level
simulation which verifies the logic functionality of the code without gatelevel information involved.
After the successful pre-synthesis simulation, Mentor Graphics’s Leonardo Spectrum is used to
synthesize the DES design with some compile constraints applied to generate the EDIF (Electronic
Design Interchange Format) file, which is a FPGAindependent netlist file. The Xilinx Place & Route
(P&R) tools take the EDIF file and implement it in the targeted Virtex V1000ebg560 device. With the
gate-delay and wiredelay information obtained from the files generated during the P&R process, the
post-layout simulation is made using ModelSim again. Synopsys’s FPGA COMPILER II (FC2) is used as
another synthesis tool to compile the DES design to Vertex V1000ebg560 device. The two versions of
implementation from Leonardo Spectrum and FC2 are compared in layout, speed, and size, etc. The
DES design is also synthesized to a testable Standard-Cell-Based ASIC with TSMC18 process.
Synopsys’s Design Compiler is used as the tool to explore the design space to compile the DES design
to different versions that are respectively optimized to area, speed and CHAPTER 1. INTRODUCTION 3
power. Cadence’s tools are used to place and route the designs to get the physical layout. Finally, the
post-layout simulation is made again to verify the implementation.

Common questions

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The challenges in synthesizing the DES algorithm from VHDL code include compatibility with the synthesis toolset and ensuring code is synthesizable under the 1993 standard. The original VHDL code had to be modified and some parts were rewritten to make it compatible with Synopsys synthesis tools . Moreover, creating a test bench was essential to verify each step of the implementation by providing sequences of keys and plaintext and comparing the resultant ciphertext to expected values .

Simulation in FPGA and ASIC development verifies functionality and correctness prior to manufacturing by detecting and resolving errors early. During pre-synthesis, simulation (e.g., using ModelSim) checks logic functionality at the RTL level, without gate-level detail, ensuring that the design performs the intended logical operations . Post-layout simulation, conducted after place and route steps, incorporates physical constraints like gate and wire delays, thus verifying the design's performance and behavior under real-world conditions . These stages ensure that all functional and physical aspects of the design meet specified requirements.

Several synthesis tools and processes were applied, including Mentor Graphics's Leonardo Spectrum and Synopsys's FPGA COMPILER II (FC2) for FPGA implementation, generating an FPGA-independent EDIF file which is implemented on the Virtex V1000ebg560 device using Xilinx P&R tools . For ASIC, Synopsys’s Design Compiler was used to explore and optimize the design space for area, speed, and power before using Cadence tools for placement and routing . Differences noted include variations in layout, speed, and size among the versions from different tools .

The document acknowledges limitations such as compatibility issues with synthesis toolsets, requiring modification of VHDL code to meet the standards applicable at the time, specifically the 1993 standard when using Synopsys tools . These limitations could affect the project's outcomes by introducing additional steps and potential errors in the design process, possibly impacting the synthesis efficiency and final performance. Ensuring correct synthesis is essential for reliable FPGA and ASIC implementations, as it directly influences how well the hardware meets functional and performance requirements.

DES, or Data Encryption Standard, uses the Feistel structure, which ensures that both encryption and decryption processes are essentially identical, with the primary difference being the order in which subkeys are applied. In DES, encryption and decryption involve using the ciphertext as input and applying the subkeys in reverse order compared to encryption (K16 to K1 instead of K1 to K16). This reversibility is integral to the Feistel structure, enabling the same set of operations to be used for both processes, ensuring security and efficiency.

Documenting the design flow for FPGA and ASIC implementations serves as a tutorial, providing valuable insights and guidance to others. It presents a step-by-step approach, highlights challenges encountered, and discusses solutions applied, which can aid learners and professionals in replicating procedures or addressing similar problems in their projects. It also fosters knowledge sharing and enhances understanding of complex processes, contributing to education and development within the field .

The comparison between Leonardo Spectrum and FC2 implementations of DES underscores the importance of optimization in digital design by evaluating performance metrics such as layout, speed, and size. This comparison highlights how different synthesis tools and approaches can yield variations in the physical implementation's efficiency and effectiveness. The ability to optimize designs for specific criteria like speed and area is crucial in resource-constrained environments, illustrating why tool selection and synthesis strategy are vital components of the design process .

Synthesizing DES into a Standard-Cell-Based ASIC using the TSMC18 process allows for thorough design space exploration to optimize for various attributes, such as area, speed, and power. Design space exploration involves evaluating different configurations to balance trade-offs among these attributes. For instance, designs optimized for speed might require more area due to increased logic utilization, while designs focused on minimizing power may sacrifice some performance. Tools like Synopsys’s Design Compiler enable exploring these trade-offs, ensuring the final implementation meets specific requirements under given constraints .

The initial permutation and key shift operations are crucial in DES as they serve to obscure the relationship between the plaintext and the ciphertext. The initial permutation provides a simple but effective transformation of the input data, effectively scrambling it from the outset. Meanwhile, key shift operations introduce non-linearity and diffusion into the encryption process by progressively shifting subkeys used in each round. Together, these operations increase the complexity of the cipher, enhancing security by making it more resistant to cryptanalysis .

The test bench code is critical in the DES implementation process as it verifies each step by simulating the logic functionality without involving gate-level details. Its success is measured by comparing the generated ciphertext to expected results after each 16 clock cycles. If the outputs match, a success message is reported; otherwise, an error message is given, prompting further debugging . This ensures that the design behaves correctly and any discrepancies can be addressed early in the development cycle.

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