OPA396

SBOSA65 – JULY 2021

OPA396 Precision, Low IQ, Low Input Bias Current Op Amp

1 Features 3 Description
• Low IQ: 23.5 µA The OPA396 features a combination of high
• Gain bandwidth product: 1 MHz bandwidth (1 MHz) along with very low quiescent
• Low input bias current: 10 fA (typical) current (23.5 µA) in a high-precision amplifier. These
• Low offset voltage: ±100 µV (maximum) features combined with rail-to-rail input and output
• Low drift: ±1.2 µV/°C make this device an exceptional choice in high-gain,
• Low supply voltage operation: 1.7 V to 5.5 V low-power applications. Ultra-low input bias current of
• Input common mode range ±100 mV beyond rail 10 fA, 100 µV of offset (maximum), and 1.2 µV/°C of
• Fast slew rate: 1 V/µs drift over temperature help maintain high precision in
• High load capacitance drive ratiometric and amperometric sensor front ends that
• High output current drive: 60 mA have demanding low-power requirements.
• Rail-to-rail output
The OPA396 uses Texas Instrument's proprietary
• EMI/RFI filtered inputs
e‑trim™ operational amplifier technology, enabling a
• Small packages: SC70 and WCSP (Preview)
unique combination of ultra-low offset and low input
2 Applications offset drift without the need for any input switching or
auto-zero techniques. The CMOS-based technology
• Portable electronics
platform also features a modern, robust output stage
• Flow transmitter
design that is tolerant of high output capacitance,
• Blood glucose monitor
alleviating stability problems that are common in
• Process analytics (pH, gas, force, humidity)
typical low-power amplifiers.
• Temperature transmitter
• Pressure transmitter Device Information
• Medical sensor patches PART NUMBER PACKAGE(1) BODY SIZE (NOM)
• Building automation OPA396 SC-70 (5) 2.00 mm x 1.25 mm
• Wearable fitness and activity monitor
• Gas detector (1) For all available packages, see the package option
addendum at the end of the data sheet.
• Analog security camera

OPA396

+ ADS7042
Sensors CE
Bridges
Transducers RE
Electrochemical Cells
Photodiodes WE

OPA396

+ ADS7042

High-Input-Impedance, Low-Offset Buffer

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 8 Application and Implementation.................................. 17
2 Applications..................................................................... 1 8.1 Application Information............................................. 17
3 Description.......................................................................1 8.2 Typical Applications.................................................. 17
4 Revision History.............................................................. 2 9 Power Supply Recommendations................................21
5 Pin Configuration and Functions...................................3 10 Layout...........................................................................21
6 Specifications.................................................................. 4 10.1 Layout Guidelines................................................... 21
6.1 Absolute Maximum Ratings ....................................... 4 10.2 Layout Example...................................................... 21
6.2 ESD Ratings .............................................................. 4 11 Device and Documentation Support..........................22
6.3 Recommended Operating Conditions ........................4 11.1 Device Support........................................................22
6.4 Thermal Information ...................................................4 11.2 Documentation Support.......................................... 22
6.5 Electrical Characteristics ............................................5 11.3 Receiving Notification of Documentation Updates.. 22
6.6 Typical Characteristics................................................ 7 11.4 Support Resources................................................. 22
7 Detailed Description......................................................14 11.5 Trademarks............................................................. 22
7.1 Overview................................................................... 14 11.6 Electrostatic Discharge Caution.............................. 22
7.2 Functional Block Diagram......................................... 14 11.7 Glossary.................................................................. 23
7.3 Feature Description...................................................15 12 Mechanical, Packaging, and Orderable
7.4 Device Functional Modes..........................................16 Information.................................................................... 23

4 Revision History
DATE REVISION NOTES
July 2021 * Initial Release

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5 Pin Configuration and Functions

+IN 1 5 V+
+
V± 2
±

±IN 3 4 OUT

Not to scale

Figure 5-1. DCK Package, 5-Pin SC70, Top View

Table 5-1. Pin Functions

PIN
I/O DESCRIPTION
NAME NO.
–IN 3 I Inverting input
+IN 1 I Noninverting input
OUT 4 O Output
V– 2 — Negative (lowest) power supply
V+ 5 — Positive (highest) power supply

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Single-supply 6
VS Supply voltage, VS = (V+) – (V–) V
Dual-supply ±3
Common-mode (V–) – 0.5 (V+) + 0.5
Input voltage, all pins V
Differential (V+) – (V–) + 0.5
Input current, all pins ±10 mA
Output short circuit(2) Continuous Continuous
TA Operating temperature –55 150 °C
Tstg Storage temperature –65 150 °C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Short-circuit to ground, one amplifier per package.

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Single-supply 1.7 5.5
VS Supply voltage, VS = (V+) – (V–) V
Dual-supply ±0.85 ±2.75
Input voltage Differential –0.5 +0.5
TA Specified temperature –40 125 °C

6.4 Thermal Information

OPA396
THERMAL METRIC(1) DCK (SC70) UNIT
5 PINS
RθJA Junction-to-ambient thermal resistance 214 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 115 °C/W
RθJB Junction-to-board thermal resistance 58 °C/W
ΨJT Junction-to-top characterization parameter 29 °C/W
ΨJB Junction-to-board characterization parameter 58 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.5 Electrical Characteristics

at VS = 1.7 V to 5.5 V, TA = 25°C, and VCM = VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VS = 5.0 V ±10 ±100
VCM = (V+) – 0.3 V, VS = 5.0 V ±60 ±750
VOS Input offset voltage µV
±15 ±100
VCM = (V–) – 0.1 V
TA = –40°C to +125°C(1) ±600

Input offset voltage TA = 0°C to 85°C(1) ±1 ±5

dVOS/dT µV/°C
drift TA = –40°C to +125°C(1) ±1.2 ±6
Power supply
PSRR VCM = (V–) – 0.1 V 40 µV/V
rejection ratio
INPUT BIAS CURRENT
TA = 25°C(1) ±0.01 10
IB Input bias current pA
TA = –40°C to +125°C(1) ±3.78
TA = 25°C(1) ±0.01 10
IOS Input offset current pA
TA = –40°C to +125°C(1) ±1.00
NOISE
0.91 µVRMS
Input voltage noise f = 0.1 Hz to 10 Hz, VCM = V
6.0 µVPP
f = 10 Hz 130
Input voltage noise
en f = 1 kHz 60 nV/√Hz
density
f = 10 kHz 55
Input current noise
in f = 1 kHz 30 fA/√Hz
density
INPUT VOLTAGE
Common-mode (V–) – (V+) +
VCM TA = –40°C to +125°C(1) V
voltage 0.1 V 0.1 V
(V–) – 0.1 V ≤ VCM ≤ (V+) – 1.5 V 89 100

Common-mode (V–) – 0.1 V ≤ VCM ≤ 100 121

CMRR dB
rejection ratio (V+) – 1.5 V, VS = 5.5 V TA = –40°C to +125°C(1) 90 100
(V+) – 0.6 V ≤ VCM ≤ (V+) + 0.1 V 69
INPUT IMPEDANCE
Differential input
Zid 0.1 || 1 GΩ || pF
impedance
Common-mode
Zic 1 || 1 TΩ || pF
input impedance

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6.5 Electrical Characteristics (continued)

at VS = 1.7 V to 5.5 V, TA = 25°C, and VCM = VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPEN-LOOP GAIN
(V–) + 0.1 V < VO < (V+) – 0.1 V,
VCM = (V–) –100 mV, 100 121
RL = 10 kΩ
VS = 5.5 V
(V–) + 0.45 V < VO < (V+) – 0.45 V,
VCM = (V–) –100 mV, 100 121
Open-loop voltage RL = 2 kΩ
AOL dB
gain (V–) + 0.1 V < VO < (V+) – 0.1 V,
VCM = (V+) – 1.5 V, 90 113
RL = 10 kΩ
VS = 1.7 V
(V–) + 0.45 V < VO < (V+) – 0.45 V,
VCM = (V+) – 1.5 V, 90 107
RL = 2 kΩ
FREQUENCY RESPONSE
IOUT = 0 µA, RL = 10 kΩ 450 kHz
Unity-gain
UGB G=1 IOUT = 0 µA, RL = 50 kΩ 0.85
bandwidth MHz
IOUT = 100 µA, RL = 10 kΩ 0.75
Gain-bandwidth
GBW 1 MHz
product
SR Slew rate G = –1, 4-V step 1 V/µs
tS Settling time To 0.1%, VS = 5.5, G = 1, 1-V step 8 µs
Overload recovery
tOR VIN x G = VS 15 µs
time
OUTPUT
No load 3

Voltage output RL = 10 kΩ 10
VO mV
swing from rail RL = 2 kΩ 40
TA = –40°C to +125°C, both rails, RL = 10 kΩ(1) 10
ISC Short-circuit current VS = 5.5 V 60 mA
Open-loop output
ZO f = 1 MHz, IOUT = 100 µA 4 kΩ
impedance
POWER SUPPLY

Quiescent current 23.5 30

IQ VCM = (V+) – 1.5 V µA
per amplifier TA = –40°C to +125°C(1) 32

(1) Specification established from device population bench system measurements across multiple lots.

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6.6 Typical Characteristics

at TA = 25°C, VS = 5.0 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)

40 20

35 18
16
30
14

Amplifiers (%)
Amplifiers (%)

25 12
20 10

15 8
6
10
4
5 2
0 0
-50 -40 -30 -20 -10 0 10 20 30 40 50 -4 -3 -2 -1 0 1 2 3 4
Input Offset Voltage (PV) opa3
Offset Voltage Drift (PV/qC) C037

45 units
Figure 6-1. Offset Voltage Distribution Figure 6-2. Offset Voltage Drift Distribution (–40°C to +125°C)
300 100

75
200
50
Offset Voltage (PV)

Offset Voltage (PV)

100
25

0 0

-25
-100
-50
-200
-75

-300 -100
-50 -25 0 25 50 75 100 125 0 1 2 3 4 5
Temperature (qC) C042
Common-mode Voltage (V) C043

5 units 5 units
Figure 6-3. Offset Voltage vs Temperature Figure 6-4. Offset Voltage vs Common-Mode Voltage
1500 200

150
1000
100
Offset Voltage (PV)

Offset Voltage (PV)

500
50

0 0

-50
-500
-100
-1000
-150

-1500 -200
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Common-mode Voltage (V) C044 Supply Voltage (V) C041
30 units VS = 5.5 V 5 units VS = 5.5 V
Figure 6-5. Offset Voltage vs Common-Mode Voltage Figure 6-6. Offset Voltage vs Supply Voltage

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6.6 Typical Characteristics (continued)

at TA = 25°C, VS = 5.0 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)

140 240 30
Gain G= 1
120 Phase 200 G= 1
20 G = 10
100 160

80 120
10

Gain (dB)
Gain (dB)

Phase (q)
60 80

40 40
0
20 0

0 -40 -10
-20 -80

-40 -120 -20

10m 100m 1 10 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz) C003
C001

RL = no load
Figure 6-7. Open-Loop Gain and Phase vs Frequency Figure 6-8. Closed-Loop Gain and Phase vs Frequency

50 100
IB- IB-
40 IB+ 75 IB+
IOS IOS
30
50
Input Bias Current (fA)
Input Bias Current (fA)

20
25
10
0 0

-10 -25
-20
-50
-30
-75
-40
-50 -100
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2
Common-mode Voltage (V) Common-mode Voltage (V) C052
C051

VS = 1.7 V Common-mode voltage referenced to VS / 2 VS = 3.3 V Common-mode voltage referenced to VS / 2

Figure 6-9. Input Bias Current vs Common-Mode Voltage Figure 6-10. Input Bias Current vs Common-Mode Voltage

100 2500
IB- IB-
75 IB+ IB+
IOS 2000 IOS
50
Input Bias Current (fA)
Input Bias Current (fA)

1500
25

0 1000

-25
500
-50
0
-75

-100 -500
-3 -2 -1 0 1 2 3 -3 -2 -1 0 1 2 3
Common-mode Voltage (V) Common-mode Voltage (V) C018
C019

VS = 5.5 V Common-mode voltage referenced to VS / 2 VS = 5.5 V Common-mode voltage referenced to VS / 2

Figure 6-11. Input Bias Current vs Common-Mode Voltage Figure 6-12. Input Bias Current vs Common-Mode Voltage

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6.6 Typical Characteristics (continued)

at TA = 25°C, VS = 5.0 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)

36 60

32 54

28 48
42
24
Amplifiers (%)

Ampilfiers (%)
36
20
30
16
24
12
18
8 12
4 6
0 0
-100 -75 -50 -25 0 25 50 75 100 -100 -75 -50 -25 0 25 50 75 100
Negative Input Bias Current (fA) C020
Positive Input Bias Current (fA) C021

Figure 6-13. Negative Input Bias Current Distribution Figure 6-14. Positive Input Bias Current Distribution
6
10 IB 40qC
IB 5.4 25qC
IOS 85qC
4.8
125qC
Input Bias Current (pA)

4.2
Output Voltage (V)

1
3.6
3
0.1
2.4
1.8

0.01 1.2
0.6
0
-50 -25 0 25 50 75 100 125 0 10 20 30 40 50 60 70 80 90 100
Temperature (qC) C022 Output Current (mA) C045

Figure 6-15. Input Bias Current vs Temperature Figure 6-16. Output Voltage Swing vs Output Current
(Maximum Supply)
3 120
40qC PSRR
2.7 25qC PSRR
Power Supply Rejection Ratio (dB)

85qC 100
2.4
125qC
2.1
Output Voltage (V)

80
1.8
1.5 60
1.2
40
0.9
0.6
20
0.3
0 0
0 10 20 30 40 50 60 70 80 90 100 1 10 100 1k 10k 100k 1M
Output Current (mA) C046
Frequency (Hz) C031

Figure 6-17. Output Voltage Swing vs Output Current Figure 6-18. PSRR vs Frequency
(Maximum Supply)

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6.6 Typical Characteristics (continued)

at TA = 25°C, VS = 5.0 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)

20 40
17.5
Common-Mode Rejection Ratio (PV/V)

Power Supply Rejection Ratio (PV/V)

15 30
12.5
10 20
7.5
5 10
2.5
0 0
-2.5
-5 -10
-7.5
-10 -20
-12.5
-15 -30
-17.5
-20
-40
-50 -25 0 25 50 75 100 125
-50 -25 0 25 50 75 100 125
Temperature (qC) C004 Temperature (qC) C032
5 units
5 units
Figure 6-19. CMRR vs Temperature
Figure 6-20. PSRR vs Temperature
10000
VOUT Voltage Noise (nV/—Hz)
Voltage (1 PV/div)

1000

100

10
Time (1 s/div) 100m 1 10 100 1k 10k 100k
C028 Frequency (Hz) C036

Figure 6-21. 0.1-Hz to 10-Hz Noise Figure 6-22. Input Voltage Noise Spectral Density vs Frequency
5 1 -40
Total Harmonic Distortion + Noise (dB)

G = –1, 10-kΩ Load

Total Harmonic Distortion + Noise (dB)

Total Harmonic Distortion + Noise (%)

Total Harmonic Distortion + Noise (%)

G = –1, 100-kΩ Load

1 G = +1, 10-kΩ Load -40
G = +1, 100-kΩ Load

0.1 -60
0.1 -60

0.01 -80 0.01 G = –1, RL = 10 kΩ -80

G = –1, RL = 100 kΩ
G = +1, RL = 10 kΩ
G = +1, RL = 100 kΩ
0.001 -100 0.002
200 2k 10m 100m 1
Frequency (Hz) Output Amplitude (VRMS) C034
C035

VOUT = 1 VRMS f = 1 kHz Filter BW = 80 kHz

Figure 6-23. THD+N Ratio vs Frequency Figure 6-24. THD+N vs Output Amplitude

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6.6 Typical Characteristics (continued)

at TA = 25°C, VS = 5.0 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)

30 34

32
24
Quiescent Current (PA)

Quiescent Current (PA)

30

18
28

26
12

24
6
22

0 20
0 1 2 3 4 5 6 -50 -25 0 25 50 75 100 125 150
Supply Voltage (V) C024
Temperature (qC) C025

5 units 5 units
Figure 6-25. Quiescent Current vs Supply Voltage Figure 6-26. Quiescent Current vs Temperature
10 1000

7.5

100
Output Impedance (k:)

5
Open Loop Gain (PV/V)

2.5

0 10

-2.5

-5 1

-7.5

-10 0.1
-50 -25 0 25 50 75 100 125 1 10 100 1k 10k 100k 1M 10M
Temperature (qC) Frequency (Hz) C047
C002

5 units
Figure 6-27. Open-Loop Gain vs Temperature Figure 6-28. Open-Loop Output Impedance vs Frequency

60 80
RISO = 0 : RISO = 0 :
55 RISO = 25 : RISO = 25 :
RISO = 50 : RISO = 50 :
50 60
Overshoot ( )

Overshoot ( )

45

40 40

35

30 20

25

20 0
10 100 1000 10 100 1000
Output Capacitance (pF) C016
Output Capacitance (pF) C017

G = +1 G = –1
Figure 6-29. Small-Signal Overshoot vs Capacitive Load Figure 6-30. Small-Signal Overshoot vs Capacitive Load
(10-mV Step) (10-mV Step)

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6.6 Typical Characteristics (continued)

at TA = 25°C, VS = 5.0 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)

VIN
VOUT

Voltage (500 mV/div)

Voltage (1 V/div)

VIN
VOUT

Time (100 Ps/div) Time (5 Ps/div)

C029 C048

Figure 6-31. No Phase Reversal Figure 6-32. Positive Overload Recovery

VIN VIN
VOUT VOUT
Voltage (500 mV/div)

Voltage (5 mV/div)

Time (5 Ps/div) Time (10 Ps/div)

C027 C015

G = +1
Figure 6-33. Negative Overload Recovery Figure 6-34. Small-Signal Step Response (10-mV Step)

VIN VIN
VOUT VOUT
Voltage (500 mV/div)
Voltage (5 mV/div)

Time (10 Ps/div) Time (10 Ps/div)

C049 C013

G = –1 G = +1
Figure 6-35. Small-Signal Step Response (10-mV Step) Figure 6-36. Large-Signal Step Response (4-V Step)

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6.6 Typical Characteristics (continued)

at TA = 25°C, VS = 5.0 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)

VIN Falling
VOUT Rising
Voltage (500 mV/div)

Output (1 mV/div)
Time (5 Ps/div) Time (2 Ps/div)
C014 C033

G = –1
Figure 6-37. Large-Signal Step Response (4-V Step) Figure 6-38. Settling Time (1-V Positive Step)
90 7
Sourcing Vs=r2.75 V
85 Sinking 6 Vs=r0.85 V

80
Output Voltage (VPP)
5
Output Current (mA)

75
4
70
3
65
2
60

55 1

50 0
-40 -20 0 20 40 60 80 100 120 140 1 10 100 1k 10k 100k 1M
Temperature (qC) C026
Frequency (Hz) C008

Figure 6-39. Short-Circuit Current vs Temperature Figure 6-40. Maximum Output Voltage vs Frequency
140

120

100
EMIRR IN+ (dB)

80

60

40

20

0
10M 100M 1000M
Frequency (Hz) C007

PRF = –10 dBm

Figure 6-41. EMIRR vs Frequency

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7 Detailed Description
7.1 Overview
The OPA396 is a low-offset, low-power e-trim operational amplifier (op amp) that uses a proprietary offset trim
technique. This op amp offers ultra-low input offset voltage, drift and input bias current while achieving an
excellent bandwidth-to-quiescient-current ratio. The OPA396 operates from 1.7 V to 5.5 V, is unity-gain stable,
and is designed for a wide range of general-purpose and precision applications.
The output features an advanced output stage that tolerates high capacitive loading for solid and stable
performance. The OPA396 strengths make this device an excellent amplifier for high-impedance sensors, where
input bias current, offset voltage, and power consumption are critical.
7.2 Functional Block Diagram

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7.3 Feature Description

7.3.1 Low Input Bias Current
The OPA396 achieves very low input bias current as a results of CMOS inputs and advanced ESD protection
circuitry. Input bias current (IB) is primarily a function of the input protection scheme in CMOS input amplifiers. If
careful consideration is not taken with the ESD cells, a CMOS input device can exhibit large input bias currents,
especially over temperature. The OPA396 achieves excellent input bias current ratings of ±30 pA maximum at
125°C.
7.3.2 Input Differential Voltage
The OPA396 does not have any diodes connected between the input nodes, allowing for input voltages
anywhere between the supply voltage. The input structure can be seen in Figure 7-1. Although the device
can tolerate any differential input voltage that does not exceed the supply voltage, do not operate continuously at
differential input voltages greater than 0.5 V.
V+

1k
+IN ±
CORE
1k
±IN +

V±

Figure 7-1. Equivalent Input Circuit

7.3.3 Capacitive Load Drive

The OPA396 features advanced output drive circuitry that can maintain stability even with capacitive loads as
high as 1 nF. Many low-quiescent-current amplifiers exhibit poor stability when connected to a capacitive load as
a result of the low levels of current used to bias the output stage. The OPA396 is designed with an output stage
that adapts to high capacitive loads without sacrificing additional current consumption. This feature gives a highly
stable device across all temperature and supply conditions, enabling robust system performance.
7.3.4 EMI Rejection
The OPA396 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI
interference from sources such as wireless communications and densely-populated boards with a mix of analog
signal chain and digital components. EMI immunity can be improved with circuit design techniques; the OPA396
benefits from these design improvements. Texas Instruments has developed the ability to accurately measure
and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to
6 GHz. Figure 7-2 shows the results of this testing on the OPA396. Table 7-1 lists the EMIRR +IN values for the
OPA396 at particular frequencies commonly encountered in real-world applications. Applications listed in Table
7-1 may be centered on or operated near the particular frequency shown. Detailed information can also be found
in the EMI Rejection Ratio of Operational Amplifiers application report, available for download from [Link].
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many op amps is a change in the offset voltage as a result of
RF signal rectification. An op amp that is more efficient at rejecting this change in offset as a result of EMI has
a higher EMIRR and is quantified by a decibel value. Measuring EMIRR can be performed in many ways, but
this section provides the EMIRR +IN, which specifically describes the EMIRR performance when the RF signal is
applied to the noninverting input pin of the op amp. In general, only the noninverting input is tested for EMIRR for
the following three reasons:

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1. Op amp input pins are known to be the most sensitive to EMI, and typically rectify RF signals better than the
supply or output pins.
2. The noninverting and inverting op amp inputs have symmetrical physical layouts and exhibit nearly matching
EMIRR performance.
3. EMIRR is more simple to measure on noninverting pins than on other pins because the noninverting
input terminal can be isolated on a PCB. This isolation allows the RF signal to be applied directly to the
noninverting input terminal with no complex interactions from other components or connecting PCB traces.
High-frequency signals conducted or radiated to any pin of the operational amplifier may result in adverse effects
because the amplifier does not have sufficient loop gain to correct for signals with spectral content outside the
bandwidth. Conducted or radiated EMI on inputs, power supply, or output may result in unexpected dc offsets,
transient voltages, or other unknown behavior. Make sure to properly shield and isolate sensitive analog nodes
from noisy radio signals, digital clocks, and interfaces.
The EMIRR +IN of the OPA396 is plotted versus frequency as shown in Figure 7-2. The OPA396 unity-gain
bandwidth is 1 MHz. EMIRR performance less than this frequency denotes interfering signals that fall within the
op amp bandwidth.
140

120

100
EMIRR IN+ (dB)

80

60

40

20

0
10M 100M 1000M
Frequency (Hz) C007

Figure 7-2. EMIRR Testing

Table 7-1. OPA396 EMIRR IN+ for Frequencies of Interest

FREQUENCY APPLICATION AND ALLOCATION EMIRR IN+
400 MHz Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF) applications 39.1 dB
Global system for mobile communications (GSM) applications, radio communication, navigation, GPS
900 MHz 46.5 dB
(to 1.6 GHz), GSM, aeronautical mobile, UHF applications
1.8 GHz GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz) 61.3 dB
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
2.4 GHz 69.8 dB
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
3.6 GHz Radiolocation, aero communication and navigation, satellite, mobile, S-band 82.5 dB
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
5 GHz 83.6 dB
operation, C-band (4 GHz to 8 GHz)

7.4 Device Functional Modes

The OPA396 has a single functional mode and is operational when the power-supply voltage is greater than
1.7 V (±0.85 V). The maximum specified power-supply voltage for the OPA396 is 5.5 V (±2.75 V).

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Application Information

The OPA396 is a unity-gain stable, precision operational amplifier free from unexpected output and phase
reversal. The OPA396 is optimized for full rail-to-rail input, allowing for low-voltage, single-supply operation or
split-supply use. These miniature, high-precision, low-noise amplifiers offer high-impedance inputs that have a
common-mode range 100 mV beyond the supplies and can tolerate the full supply voltage across the input. The
OPA396 precision amplifier is designed for sensor amplification, low-power analog signal chain applications in
low or high gains, as well as a low-power discrete MOSFET or bipolar driver.
8.2 Typical Applications

8.2.1 Three-Terminal CO Gas Sensor

Figure 8-1 shows a simple micropower potentiostat circuit for use with three-terminal unbiased CO sensors.
This same design is applicable to many other type of three-terminal gas sensors or electrochemical cells.
The basic sensor has three electrodes: the sense or working electrode (WE), counter electrode (CE) and
reference electrode (RE). A current flows between CE and WE proportional to the detected concentration. The
RE monitors the potential of the internal reference point. For an unbiased sensor, the WE and RE must be
maintained at the same potential by adjusting the bias on CE. Through the potentiostat circuit formed by U1, the
servo feedback action maintains the RE pin at a potential set by VREF. R1 maintains stability as a result of the
large capacitance of the sensor. C1 and R2 form the potentiostat integrator and set the feedback time constant.
U2 forms a transimpedance amplifier (TIA) to convert the resulting sensor current into a proportional voltage.
The transimpedance gain, and resulting sensitivity, is set by RF according to Equation 1:

VTIA = (–I * RF) + VREF (1)

RLoad is a load resistor with a value that is normally specified by the sensor manufacturer (typically, 10 Ω). The
potential at WE is set by the applied VREF.
R1

CE
RLOAD R2
RE

VREF + U1
WE
OPA396

RF

RLOAD

VOUT
VREF +
U2
OPA396

Figure 8-1. Three-Terminal CO Gas Sensor

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[Link] Design Requirements

For this example, an electrical model of a CO sensor is used to simulate the sensor performance, as shown in
Figure 8-2. The simulation is designed to model a CO sensor with a sensitivity of 69 nA/ppm. The supply voltage
and maximum analog-to-digital converter (ADC) input voltage is 2.5 V, and the maximum concentration is 300
ppm.

CO Sensor
Model VCE
10 kŸ
CE

260 mF Ÿ

Ÿ 2.5 V
10 kŸ
RE
±
Ÿ VREF
+ OPA396

130 mF Ÿ

ISENS 110 kŸ VTIA

0 µA to 20 µA

Ÿ 2.5 V
WE
±
VREF
+ OPA396

Figure 8-2. CO Sensor Simulation Schematic

[Link] Detailed Design Procedure

First, determine the VREF voltage. This voltage is a compromise between maximum headroom and resolution, as
well as allowance for the minimum swing on the CE terminal because the CE terminal generally goes negative
in relation to the RE potential as the concentration (sensor current) increases. Bench measurements found the
difference between CE and RE to be 180 mV at 300 ppm for this particular sensor. To allow for negative CE
swing, footroom, and voltage drop across the 10-kΩ resistor, 300 mV is chosen for VREF.

VZERO = VREF = 300 mV (2)

where
• VREF is the reference voltage (300 mV).
• VZERO is the concentration voltage (300 mV).
Next, calculate the maximum sensor current at highest expected concentration:

ISENSMAX = IPERPPM * ppmMAX = 69 nA * 300 ppm = 20.7 µA (3)

where
• ISENSMAX is the maximum expected sensor current.
• IPERPPM is the manufacturer specified sensor current in amperes per ppm.
• ppmMAX is the maximum required ppm reading.

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Then, find the available output swing range greater than the reference voltage available for the measurement:

VSWING = VOUTMAX – VZERO = 2.5 V – 0.3 V = 2.2 V (4)

where
• VSWING is the expected change in output voltage.
• VOUTMAX is the maximum amplifier output swing.
Finally, calculate the transimpedance resistor (RF) value using the maximum swing and the maximum sensor
current:

RF = VSWING / ISENSMAX = 2.2 V / 20.7 µA = 106.28 kΩ (use 110 kΩ for a common value) (5)

[Link] Application Curve

VTIA
VCE
2.5 V ISENS
Voltage (1 V/div)

Current (10 P$/div)

0.3 V

20 PA

Time (10 ms/div)

C012

Figure 8-3. Sensor Transient Response to Simulated 300-ppm CO Exposure

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8.2.2 4-mA to 20-mA Loop Design

Factory automation systems commonly use the 4-mA to 20-mA (4-20 mA) communication protocol to enable
process automation. In typical 2-wire, 4-mA to 20-mA loop applications, power to the remote transmitter is
limited to less than 4 mA total consumption. As a result of the power limitations, low power consumption is
essential. The OPA396 solves many design challenges in 4-mA to 20-mA loop applications, where low power,
high accuracy, and high bandwidth are required.
4.096 V

102.4 kŸ
5V IOUT+
11.3 kŸ 14.3 kŸ
DAC + Ÿ
12 nF OPA396

1.98 kŸ Ÿ

IOUT±

Figure 8-4. 4-20 mA Loop Interface Schematic

[Link] Design Requirements

Table 8-1. Design Parameters

PARAMETER VALUE
Total current consumption < 100 μA
DAC control voltage 0 V to 4.096 V
Output current 4 mA to 20 mA

[Link] Application Curve

8 48
7 VDAC 44
IOUT
6 40
5 36
Current ( 1 mA/div)
Voltage ( 1 V/div)

4 32
3 28
2 24
1 20
0 16
-1 12
-2 8
-3 4
-4 0
Time (1 ms/div)
C050

Figure 8-5. 4-mA to 20-mA Loop Response

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9 Power Supply Recommendations

The OPA396 device is specified for operation from 1.7 V to 5.5 V (±0.85 V to ±2.75 V).

10 Layout
10.1 Layout Guidelines
Paying attention to good layout practice is always recommended. Keep traces short, and when possible, use
a printed-circuit board (PCB) ground plane with surface-mount components placed as close as possible to
the device pins. Place a 0.1-µF capacitor closely across the supply pins. These guidelines must be applied
throughout the analog circuit to improve performance and provide benefits, such as reducing the electromagnetic
interference (EMI) susceptibility.
10.2 Layout Example
VS
Minimize
RF CBYPASS parasitic
inductance by
placing bypass
-IN V+ capacitor close
to V+.
V-

+IN VOUT
Keep high OUT
impedance
input signal VIN Route trace
away from under package
noisy traces. for output to
feedback
resistor
connection.
Figure 10-1. OPA396 Layout Example

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11 Device and Documentation Support

11.1 Device Support
11.1.1 Development Support
[Link] TINA-TI™ Simulation Software (Free Download)
TINA-TI™ software is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE
engine. TINA-TI software is a free, fully-functional version of the TINA™ software, preloaded with a library of
macromodels in addition to a range of both passive and active models. TINA-TI simulation software provides
all the conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design
capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI software offers extensive post-
processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability
to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.

Note
These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed.
Download the free TINA-TI software from the TINA-TI website.

11.2 Documentation Support

11.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Highly-Accurate, Loop-Powered, 4mA to 20mA Field Transmitter With HART Modem
reference design
• Texas Instruments, Micropower Electrochemical Gas Sensor Amplifier reference design
• Texas Instruments, Compensate Transimpedance Amplifiers Intuitively application report
• Texas Instruments, Designing With pH Electrodes application report
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on [Link]. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
e‑trim™, TINA-TI™, and TI E2E™ are trademarks of Texas Instruments.
TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

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11.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

[Link] 31-Jul-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

OPA396DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 1JJ

OPA396DCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 1JJ

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

[Link] 31-Jul-2021

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

[Link] 1-Aug-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA396DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
OPA396DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

[Link] 1-Aug-2021

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA396DCKR SC70 DCK 5 3000 190.0 190.0 30.0
OPA396DCKT SC70 DCK 5 250 190.0 190.0 30.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DCK0005A SCALE 5.600
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

C
2.4
1.8 0.1 C
1.4
B A 1.1 MAX
PIN 1 1.1
INDEX AREA

1 5

2X 0.65 NOTE 4

2.15
1.3 (0.15) 1.3
2 1.85

(0.1)

4
0.33 3
5X
0.23
0.1
0.1 C A B (0.9) TYP
0.0

0.15
GAGE PLANE 0.22
TYP
0.08

8 0.46
TYP TYP
0 0.26
SEATING PLANE

4214834/C 03/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.

[Link]
 EXAMPLE BOARD LAYOUT
DCK0005A SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

PKG
5X (0.95)

1
5
5X (0.4)

SYMM
(1.3)
2
2X (0.65)

3 4

(R0.05) TYP (2.2)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:18X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214834/C 03/2023

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
DCK0005A SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

PKG
5X (0.95)
1
5
5X (0.4)

SYMM
(1.3)
2
2X(0.65)

3 4

(R0.05) TYP
(2.2)

SOLDER PASTE EXAMPLE

BASED ON 0.125 THICK STENCIL
SCALE:18X

4214834/C 03/2023

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.

[Link]
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