Microelectronics Journal 111 (2021) 105033

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A novel ultra-low-power CNTFET and 45 nm CMOS based ternary SRAM

Abhay S. Vidhyadharan a , Sanjay Vidhyadharan b, ∗
a
Department of ECE, SRMIST, Kattankulathur, Chennai, Tamil Nadu, 603203, India
b Department of EEE, BITS Pilani Hyderabad Campus, Telangana, 500078, India

A R T I C L E I N F O A B S T R A C T

Keywords: This paper presents a CNTFET based ultra-low-power ternary SRAM design which consumes merely 66 nW of
Ternary logic power, achieving 84–98% reduction in power consumption as compared to the other CNTFET ternary SRAM
Ternary SRAM
designs reported in the literature. The 6-Transistor (6T) Standard Ternary Inverter (STI) cell or the 3T-STI
CNTFET
cell form the basic building block of the conventional SRAM cells. These conventional STI designs have an
45 nm CMOS
undesirable direct path between VDD and ground during certain ternary input signals, resulting in higher power
consumption. In this paper, a highly power-efficient 4T-STI based Ternary SRAM design is presented, which
prevents a direct path between the power supply VDD and ground in all the possible ternary logic states.
While CNTFET is preferred by many researchers around the world for low-power VLSI applications, CMOS
technology is still widely used in the industry because of the availability of advanced CMOS manufacturing
units. Therefore, the proposed ultra-low-power ternary SRAM design has been implemented with both 32 nm
CNTFET and 45 nm CMOS devices. The performance of both the CNTFET and CMOS based ultra-low-power
ternary SRAM circuits have been benchmarked with corresponding conventional SRAM circuits. The overall
decrease in Power Delay Product (PDP) is 86–97% in the proposed ultra-low-power ternary 32 nm CNTFET
SRAM circuit and 87–99% in the proposed 45 nm CMOS SRAM with respect to corresponding conventional
ternary SRAM circuits.

1. Introduction The basics of CNTFET operation is presented in section 2 and the

device characteristics are compared with that of the MOSFETs in this
MOSFET based binary logic circuits form the basic building blocks section. The Standard Ternary Inverter (STI) is the fundamental build-
of most of the traditional VLSI Circuits. However, recent studies ing blocks of the Ternary SRAM cell. The limitations of the conven-
[2,3,7,16,22,25,28,29,31,34,38,39,41,43,47,48] have demonstrated tional STI designs are discussed in section 3. An improved ultra-low-
that multi-valued logic (MVL), and in particular ternary circuits in addi- power ternary SRAM design which consumes significantly lesser power
tion to reducing the component count of the various logical and arith- than the conventional ternary SRAMs is presented in section 4. The per-
metical circuits, also significantly reduces the propagation delays asso- formance parameters of the proposed SRAM implemented with 32 nm
ciated with these circuits. A microprocessor and computer built entirely CNTFET and 45 nm MOSFETs are compared with the performance
on ternary circuits have been manufactured and the efficacy of multi- parameters of the conventional ternary SRAMs in section 5.
valued logic has been demonstrated [45,46]. Researchers are preferring
advanced technology devices like Carbon Nanotube FETs (CNTFETs) 2. Carbon Nanotube field-effect transistors (CNTFETs)
over conventional CMOS devices for implementation of ternary circuits
as they can be easily configured as High and Low Threshold (HVT 2.1. Structure and device characteristics of CNTFETs
and LVT) switches enabling compact and faster ternary circuit design
[2,7,8,12,16,17,20,22,25,28,29,31,32,35,38,39,41,43,44,47,48]. CNTFETs can be classified into two based on the current injection
Moreover, CNTFETs have higher ION ∶ CGG and ION ∶ IOFF ratios than methods. CNTFETs with metallic ohmic contacts rely on tunneling of
corresponding CMOS devices making it a more power-efficient choice majority carriers (holes in p-CNTFETs and electrons in n-CNTFETs)
for ultra-low-power VLSI circuits.

∗ Corresponding author.
E-mail address: sanjay_vidhyadharan@rediff[Link] (S. Vidhyadharan).

[Link]
Received 7 January 2021; Received in revised form 18 February 2021; Accepted 14 March 2021
Available online 20 March 2021
0026-2692/© 2021 Elsevier Ltd. All rights reserved.
A.S. Vidhyadharan and S. Vidhyadharan Microelectronics Journal 111 (2021) 105033

Fig. 2. Characteristics of LVT, Normal VT and HVT CNTFET devices fabricated

Fig. 1. The CNTFET structure with multiple Carbon Nano-tubes [9]. with appropriate CNT effective diameters.

from the potential barriers at the drain and source junctions for cur-
rent conduction. The electric field on application of gate voltage, mod-
ulates the junction barrier-width which results in variation in the cur-
rent injected into the channel region, making the transconductance of
the CNTFET a function of gate voltage [19,37]. The second type of the
CNTFETs is made of coaxial (13,0) zigzag carbon nano-tubes (CNTs)
and takes advantage of the n-doped CNT as the source and drain con-
tacts. Highly doped potassium drain and source regions are used as
contacts and it has been demonstrated and experimentally verified that
these type of CNTFETs behave like MOSFETs [11,19]. In these CNTFETs
the potential barrier is formed at the middle of the channel and the gate
voltage modulates the barrier height producing the required source to
drain current variation.
The structure of CNTFETs [9] using multiple Carbon Nano Tubes
(CNTs) in the channel region is shown in Fig. 1. The CNTs under Fig. 3. ID -VGS characteristics of the Normal VT devices nCNTFET vs. nMOSFET
the drain and source regions are heavily doped with potassium impu- for ChannelLength = 45 nm for both the devices, ChannelWidth = 120 nm for
rity making them n + regions/contacts and the portion of the CNTs MOSFET and single tube for CNTFET.
under the gate-stack are intrinsic, similar to the MOSFET structures.
The threshold voltage VT of the CNTFET is a function of the bandgap
of the Carbon Nano Tube, which again is set by the orientation of the
2.2. Performance benchmarking of CNTFETs with MOSFETs
CNT graphene sheet (indicated as the chiral vector of the CNT). The
chiral vector for CNTFET is represented by the two integers (n1 , n2 ).
The industry-implemented 45 nm CMOS technology files released by
The effective diameter of the CNT DCNT can be expressed as [4,5]:
Europractice for academic research purposes [6], are readily available
√ in EDA tool (cadence®). The device characteristics of the CNTFETs
a n21 + n1 n2 + n22 (with channel length chosen as 45 nm) have been compared with 45 nm
DCNT = (1)
𝜋 MOSFETs. The standard verilog-A compact CNTFET SPICE Model [4,5]
has been used for co-simulation of CNTFET device and circuit character-
where a = 2.49 Å is the lattice constant. The CNTFET is switched istics with standard 45 nm MOSFET devices and circuits in cadence®.
ON/OFF on application of appropriate gate voltage. The threshold volt- The ITRS regulation stipulates power supply of 1 V DC for 45 nm CMOS
age VT of the CNTFETT is an inversely proportional to the diameter and devices [10] and hence the CNTFET and MOSFET device characteristics
can be expressed as [4,5]: was compared for the entire range of 0–1 V VDS & VGS .
The transfer characteristics of n & p-channel NVT devices, for the
EG aV smallest possible device size i.e. 45 nm effective channel length for both
VT ≃ =√ 𝜋 (2)
2q 3qDCNT CNTFET & MOSFET, 120 nm channel width for MOSFET and CNTFET
with a single tube are shown in Figs. 3 and 4, respectively. Although the
Here q is the unit electron charge and V𝜋 = 3.033 eV is the carbon 𝜋 -𝜋 CNTFETs have slightly lower ION than corresponding MOSFETs, they
bond-energy. It can be seen from eqn. (2) that the threshold voltage have 19 times higher ION ∶ CGG and 8–10 times higher ION ∶ IOFF ratios
of the CNTFET is an inverse function of the CNT effective diameter. than MOSFETs. This makes the CNTFETs a better candidate for imple-
More details about the derivation of equations (1) and (2) are available mentation of low-power ternary logic VLSI circuits.
in Refs. [4,5]. The threshold voltage of the CNTFET can be set to the The summary of the device characteristics benchmarking results are
required voltage by choosing the appropriate chiral vector. The multi- placed in Tables 1 and 2. The CNTFETs have a higher ION ∶ CGG ratio
VT configuration of theCNTFETs makes it an ideal device for ternary than analogous MOSFETs and hence CNTFET based circuits will have
logic circuits. Chiral vector (13,0). (10,0) and (19,0) yields Normal VT much lesser propagation delays than the corresponding MOSFET cir-
(NVT), High VT (LVT) and Low VT (LVT) CNTFET devices, as shown in cuits. Furthermore. the CNTFET circuits will have lesser static power
Fig. 2. dissipation due to lower IOFF and significantly lesser dynamic power

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A.S. Vidhyadharan and S. Vidhyadharan Microelectronics Journal 111 (2021) 105033

Fig. 5. Schematic of the conventional ternary SRAM.

CNTFET based ternary logic gates have been proposed which optimizes
the transistor count of basic ternary building blocks. A novel SRAM
cell design have been proposed in Ref. [26] which enables significant
power reduction as compared to the conventional SRAM circuits at low
Fig. 4. IS -VSG characteristics of the Normal VT devices pCNTFET [Link] operating voltages.
for ChannelLength = 45 nm for the both devices, ChannelWidth = 120 nm for
MOSFET and single tube for CNTFET.
3. Detailed analysis of limitations of the conventional SRAM
designs
Table 1
Device characteristics of the Normal VT nCNTFET vs.
3.1. STI based conventional ternary SRAM
nMOSFET devices with 45 nm effective channel length for
both nCNTFET & nMOSFET, 120 nm channel width for In ternary logic the power supply voltage VDD represents ternary
nMOSFET and nCNTFET with a single tube. Best Figures of logic state ‘2′ and ground represents ternary logic state ‘0’. The inter-
Merit are marked in bold. mediate ternary logic state ‘1’ is repented by VDD ∕2. The truth table
Parameter n-MOSFET n-CNTFET of the Standard Ternary Inverter (STI) and the schematic of the con-
ventional ternary SRAM implemented by cross-coupling two STI cells is
Power Supply VDD (V) 1 1
Ion (𝜇 A) 48 29 shown in Fig. 5. There are two types of conventional STI designs one
Ioff (pA) 5.1 0.29 which utilities 6 transistors and has moderate power requirement and
Average CGG (fF) 0.03 0.001 the second design which requires only 3 transistors for implementation,
Ion ∶ Ioff 9.4 × 106 100 × 106 but has significantly higher power consumption. The limitations of both
Ion ∶ CGG (sec−1 ) 1.6 × 1012 29 × 1012
Improvement in Ion ∶ Ioff X 10.6
designs are explained in the following subsections.
Improvement in Ion ∶ CGG X 18
3.2. Limitations of the conventional 6T-STI

The schematic and the performance plot of the conventional 6T-STI

due to lower gate capacitance CGG .
[23] implemented with 32 nm CNTFET with VDD = 0.9 V is shown
in Fig. 6. When the input is ternary logic 0 (0 V), HVT p-CNTFET P1
2.3. Review of previous CNTFET based works
is switched ON and HVT n-CNTFET N1 is switched OFF, resulting in
the output node Vout getting charged to ternary logic 2 state (0.9 V),
Since the CNTFET can easily be fabricated as Normal, High and
through P1 . CNTFET N2 also remains OFF in this state. The total static
Low threshold switches, it has become a very efficient technology for
leakage current in this state is 0.045 nA.
ternary circuit designs. In Refs. [23,24] basic ternary logic cells like Similarly, when the input is ternary logic 2, HVT n-CNTFET N1 is
three-valued NAND, AND & AND gates implemented with CNTFETs
switched ON and HVT p-CNTFETT P1 is switched OFF, resulting in out-
were presented. Since then, many research groups have proposed effi-
put node Vout getting discharged to ternary logic 0 state, through N1 .
cient CNTFET based ternary designs that perform multiple logical and
CNTFET P2 also remains OFF in this state. The total static leakage cur-
arithmetic operations requiring lesser number of computation steps and
rent in this state is 0.0002 nA.
consuming negligible power as compared to the conventional ternary
However, when the input is ternary logic 1 (0.45 V), both HVT CNT-
circuits [1,14,16,18,27,30,33,40,43]. In Ref. [13], negative capacitance FETs N1 & P1 are switched OFF and both LVT CNTFETs N2 & P2 are
switched ON simultaneously. A constant static current of 552 nA flows
through P2 –P3 –N3 –N2 . The output node Vout is charged to ternary logic
Table 2 1 because of the diode-connected CNTFETs P3 & N3 forming a poten-
Device characteristics of the Normal VT pCNTFET vs. tial divider network. A relatively higher static current of 552 nA flows
pMOSFET devices 45 nm effective channel length for both
through P2 –P3 –N3 –N2 in this state, which increases the overall power
pCNTFET & pMOSFET, 120 nm channel width for pMOSFET
consumption of the circuit.
and CNTFET with a single tube Best Figures of Merit are
marked in bold.
The higher power consumption in the 6T STI cell is because of the direct
path between VDD and ground through P2 –P3 –N3 –N2 , when the input is
Parameter p-MOSFET p-CNTFET
ternary logic 1.
Power Supply VDD (V) 1 1
Ioff (pA) 2.47 0.29
Ion (𝜇A) 34 29 3.3. Limitations of the conventional 3T-STI
Average CGG (fF) 0.023 0.001
Ion ∶ Ioff 13.8 × 106 100 × 106 The schematic and the performance plot of the conventional 3T-STI
Ion ∶ CGG (sec−1 ) 1.48 × 1012 29 × 1012
Improvement in Ion ∶ Ioff X 7.2
[49] implemented with 32 nm CNTFETs with VDD = 0.9 V is shown
Improvement in Ion ∶ CGG X 19.6 in Fig. 7. CNTFETs N2 is an ‘always ON’ transistor connecting power
supply VDD ∕2 to output node Vout .

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A.S. Vidhyadharan and S. Vidhyadharan Microelectronics Journal 111 (2021) 105033

Fig. 7. (a) Schematic and (b) transient switching plot of the conventional 3T-
STI.

Fig. 6. (a) Schematic and (b) performance plot of the conventional 6T-STI.

When the input is ternary logic 0, HVT p-CNTFET P1 is switched ON

and HVT n-CNTFET N1 is switched OFF, resulting in output node Vout
getting charged to ternary logic 2 state, through P1 . n-CNTFET N2 also
remains ON in this state and a static current of 389 nA is observed from
VDD to VDD ∕2 through P1 –N2 .
When the input is ternary logic 2, HVT n-CNTFET N1 is switched ON
and HVT p-CNTFET P1 and is switched OFF, resulting in output node
Vout getting discharged to ternary logic 0 state, through N1 . CNTFET N2
also remains ON in this state resulting in a high static current of 11 𝜇 A
from VDD ∕2 to ground through N2 –N1 . Furthermore since N2 remains
ON the output voltage observed is around 80 mV instead of pure ground
potential. This 80 mV voltage can be reduced further by increasing the
number of CNT tubes of N1 with respect to N2 , but it would result in a
further increase in the static current.
When the input is ternary logic 1, both HVT CNTFETs N1 & P1 are
turned OFF, and the output node is charged to logic 1 (0.45 V) through
N2 . The static current, in this case, is 4.1 nA.
The higher power consumption in the 3T-STI cell is because of the
direct path between VDD ∕2 and ground through N2 –N1 , when the input
is ternary logic 2 and the direct path between VDD & VDD ∕2 through P1 –
N2 , when the input is ternary logic 0.

4. Proposed improved ultra-low-power ternary SRAM design

The schematic of the proposed CNTFET ternary SRAM design is

shown in Fig. 8. The design is based on a new power-efficient 4T-STI Fig. 8. Schematic of the proposed ultra-low-power ternary SRAM design.
[Link] of performance of the proposed ternary SRAM design
with other conventional designs are shown in Fig. 9.

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A.S. Vidhyadharan and S. Vidhyadharan Microelectronics Journal 111 (2021) 105033

Fig. 9. Comparison of performance of the proposed 4T-STI ternary SRAM design with other conventional designs.

Case 1. Consider a case when a ternary logic ‘0′ is to be written into N1 . CNTFET N2 and P2 remains OFF in this state. In the feedback path
the SRAM cell. The ground potential at node Q switches ON HVT p- N3 is switched OFF and P3 is switched ON. The total static current in
CNTFET P1 and HVT n-CNTFET N1 is switched OFF, resulting in output this condition is 17.2 pA (Fig. 9). When the Write signal is removed,
node Q getting charged to ternary logic 2 state (VDD ), through P1 . CNT- the back to back connected STI (N1 –P1 and N3 –P3 ) form a latch and
FET N2 and P2 also remains ON in this state but that doesn’t result the ternary data is preserved. There is no direct path between VDD and
in any additional static current. In the feedback path N3 is switched ground in this state.
ON and P3 is switched OFF. The total static current in this condition
Case 3. Consider a case when a ternary logic ‘1’ is to be written into
is 44 pA (Fig. 9). When the Write signal is removed, the back to back
the SRAM cell. The VDD ∕2 potential at node Q switches OFF both HVT
connected STI (N1 –P1 and N3 –P3 ) form a latch and the ternary data is
n-CNTFET N1 and HVT p-CNTFET P1 . While the LVT p-CNTFET P2 &
preserved. There is no direct path between VDD and ground in this state.
SVT N2 is switched ON, resulting in output node Q getting discharged to
Case 2. Consider a case when a ternary logic ‘2’ is to be written into ternary logic 0 state (ground potential), through N1 . CNTFET N2 and P2
the SRAM cell. The VDD potential at node Q switches ON HVT n-CNTFET remain OFF in this state. A 0.45 V voltage is dropped across the diode
N1 and HVT p-CNTFET P1 is switched OFF, resulting in output node Q connected CNTFETs N2 which has a chirality (13,0), thus charging the
getting discharged to ternary logic 0 state (ground potential), through output node to logic 1 (0.45 V). The static current, in this case, is 87 pA

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A.S. Vidhyadharan and S. Vidhyadharan Microelectronics Journal 111 (2021) 105033

Table 3
Improvement in Power Delay Product of the proposed 4T-STI 32 nm CNTFET SRAM w.r.t conventional 32 nm
6T-STI & 3T-STI CNTFET SRAMs. Results based on self-simulation of the benchmarked designs under the same
test conditions.
Circuit parameters Units Conventional CNTFET Designs Proposed CNTFETT Design
6T-STI SRAM [23] 3T-STI SRAM [49] 4T-STI SRAM
Technology Node nm 32 32 32
Power supply VDD V 0.9 0.9 0.9
Transistor Counta 16 10 12
Average delay 𝜏 p ps 0.425 0.25 0.375
Average power Pavg 𝜇W 0.42 3.1 0.066
PDP × 10−18 J 0.18 0.775 0.025

PDP [Link] Proposed Design × 7.2 × 31 ×1

a
Including 4 transistors of Write enable pass switch of Bit and Bit lines.

Fig. 10. Layout of the SRAM designs implemented with 45 nm MOSFETs.

Table 4
Improvement in Power Delay Product of the proposed 4T-STI 45 nm CMOS & CNTFET SRAM w.r.t conventional 45 nm 6T-STI &
3T-STI CMOS SRAMs.
Circuit parameters Units Conventional CMOS Designs Proposed Designs
6T-STI SRAM [23] 3T-STI SRAM [49] 4T-STI CMOS SRAM 4T-STI CNTFET SRAM
Technology Node nm 45 45 45 45
Power supply VDD V 1 1 1 1
Transistor Counta 16 10 12 12
Average delay 𝜏 p ps 2.95 2.15 2.9 0.4
Average power Pavg 𝜇W 1.41 20.7 0.189 0.12
PDP × 10−18 J 4.2 44.5 0.55 0.048

PDP [Link] Proposed CMOS Design × 7.64 × 80.9 ×1 × 0.087

a
Including 4 transistors of Write enable pass switches of Bit and Bit lines.

(Fig. 9). When the Write signal is removed, the back to back connected While CNTFET is the most preferred device for ternary logic circuit
STI (N2 –P2 and N4 –P4 ) form a latch and the ternary data is preserved. implementation, 45 nm CMOS technology also provides NVT, HVT and
There is no direct path between VDD and ground even in this state. LVT devices like the CNTFET technology. The new design methodology
presented in this work makes use of the LVT and HVT devices and can
Direct path between VDD and ground is avoided in all the possible ternary
be implemented with both CMOS and CNFET technologies. The design
states in the proposed design and hence significant reduction in total power
has been implemented in 45 nm CMOS to estimate the area. Further-
consumption is achieved.
more, the circuit implemented in CMOS would enable easy integration
of the ternary designs with existing CMOS binary designs.
5. Performance benchmarking of proposed SRAM implemented The proposed SRAM design and the conventional 6T-STI SRAM and
with CNTFET and 45 nm CMOS devices with conventional ternary 3T-STI SRAM designs were also implemented with 45 nm CNTFETs and
SRAMs 45 nm CMOS devices with VDD = 1 V, which is the specified voltage
for 45 nm technology node by ITRS [10]. The layout of the SRAM
The proposed SRAM design, the conventional 6T-STI SRAM and the designs including the Write pass-switches, implemented with 45 nm
3T-STI SRAM designs were implemented with 32 nm CNTFETs with CMOS devices are shown in Fig. 10. The comparison of the performance
VDD = 0.9 V. The comparison of the performance parameters is sum- parameters is summarized in Table 4. The 3T-STI CMOS SRAM design
marized in Table 3. The 3T-STI SRAM design has the lowest average has the lowest average delay of 2.15 ps among the three CMOS designs
delay of 0.25 ps but has a large power requirement of 3.1 𝜇 W. The 6T- but has large power requirement of 20.7 𝜇 W. The 6T-STI CMOS SRAM
STI SRAM has an average delay of 0.425 ps and consumes 0.42 𝜇W of has an average delay of 2.95 ps and consumes 1.41 𝜇 W of power. The
power. The proposed 4T-STI SRAM design has an extremely low power proposed 4T-STI CMOS and CNTFET SRAM design have an extremely
requirement of 0.066 𝜇 W and has a delay of 0.375 ps. Overall the PDP low power requirement of 0.189 & 0.12 𝜇 W and has delays of 2.9 &
of the proposed design is mere 0.03–0.14 times the PDP of conventional 0.4 ps, respectively. Overall the PDP of the proposed CMOS design is
designs.

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A.S. Vidhyadharan and S. Vidhyadharan Microelectronics Journal 111 (2021) 105033

Table 5
Improvement in Power Delay Product of the proposed 4T-STI w.r.t other SRAM designs reported in literature.
Circuit parameters Shylashree-2019 Karmakar-2019 Kumar-2019 Patel-2019 Proposed Design
[42] [15] [21] [36] 4T-STI SRAM
Technology Node (nm) 45 32 32 32 32
Power supply VDD (V) 1 0.5 1 0.9 0.9
Transistor Count∗ 18 6 10 12 10
Average delay 𝜏 p (ps) 11 3.3 0.36 36 0.375
Average power Pavg (𝜇 W) 3.14 2.6 3.82 19.8 0.066
PDP × 10−18 (J) 34.54 8.58 1.38 12.7 0.025
PDP [Link] Proposed Design × 1382 × 343 × 55.2 × 508 ×1

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