Microelectronic Circuits
EEE F244
BITS Pilani Anu Gupta
Pilani Campus
AICD
BITS Pilani Anu Gupta
Pilani Campus
BITS Pilani
Pilani Campus
Single Stage Amplifiers
Device gain
Max gain/ frequency of
MOSFET device as amplifier
Intrinsic gain
[𝑔𝑚 𝑟𝑜 ]
Transit frequency
1 𝑔𝑚
𝑓𝑇 =
2𝜋 𝐶𝑔𝑠
Anu Gupta BITS Pilani, Pilani Campus
Small signal parameters
Id, gm, [gm/ Id]
1 𝑊 2
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇
2 𝐿
𝑊
𝑔𝑚 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇
𝐿
Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
How to maximise gain in an amplifier at
given power constraint???
• We need to maximise gm for required
power dissipation or Ibias
• How to choose gm ???
𝑔𝑚
• Define a new figure of merit → shd.
𝐼𝐷
be large
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Method1 --To increase intrinsic
gain by design, choose L large
Keep L large
Keep Id small
Example---
Keeping (w/L) constant
L’= 4L, W’= 4W, I’ = I→ Vgs --same
Intrinsic gain= 4 times increase
Intrinsic gain’ ≈ [4] original intrinsic gain by properly
choosing L values
Cgs increases , so Transit freq. reduces
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Effect of technology scaling on
intrinsic gain (C E SCALING)
• MOS scaled down by constant electric
field scaling strategy
(α > 1: usually α =1.33) All dimensions
scale down by a factor α:
• All voltages scale down by a factor α
Effect of increasing L on CSA gain
• Keeping I constt.-----
➢L1, L2 scaled up by α, (ro1, ro2) increase
➢W1, W2 also increase to keep ratio
constant, so gm remains same
➢Hence CSA gain increases by ≈ α
Effect of increasing only L
• Keeping I constt-----
➢L scaled up by α, ro increases
➢L scaled up, W also increases to keep
ratio constant, so gm remains same
➢Hence, intrinsic gain increases by α
➢Vgs increases, so Swing reduces
Effect of technology scaling on intrinsic gain (C E SCALING)
• Keeping W/L constt----- Vdd decreases by ,say, α
➢ L scaled down by α, W also decreases to keep
ratio constant,
➢ Cox, increases by α-----Id decreases by α---gm
remains constt.
➢ λ increases by α, Id decreases by α---ro constt.
➢ Hence intrinsic gain does not change
What do we really want??
What we really want from MOS transistor
– Large gm without investing much current (less
power consumption)
– Large gm without having large Cgs (wide fT)
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Method 2 to maximise gain in an
amplifier at given power constraint
• We need to maximise gm for required
power dissipation or Ibias
• How to choose gm ???
𝑔𝑚
• Define a new figure of merit → shd.
𝐼𝐷
be large
Anu Gupta BITS Pilani, Pilani Campus
gm/ Id—
Trans-conductance generation efficiency
1) It is strongly related to the performances (gain/ transit
frequency )of analog circuits
2) It gives an indication of the device operating region.
3) It provides a tool for calculating required transistors
dimensions
The gm/ID ratio is a measure of the efficiency to translate
current (hence power) into trans-conductance; i.e., the
greater the gm / ID value, the greater the trans-conductance
we obtain at a constant current value.
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Figure of merit [gm/ Id]
1 𝑊 2
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇
2 𝐿
𝑊
𝑔𝑚 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇
𝐿
𝑔𝑚 2
=
𝐼𝐷 𝑉𝐺𝑆 − 𝑉𝑇
• Choose bias current using power consumption constraint
• If Choose small Vov. , then (W/L) increases for given
current , Si area increases, Cgs increases
• Hence, fT decreases???
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Information from gm/Id plot
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Intrinsic gain in terms of
gm * ro
𝑔𝑚
𝐴𝑉 = − 𝑉𝐴
𝐼𝐷
1 𝑔𝑚
𝑓𝑇 =
2𝜋 𝐶𝑔𝑠
For amplifier,
UGB
1 𝑔𝑚
𝑓𝑈𝐺𝐵 =
2𝜋 𝐶𝐿
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Anu Gupta
BITS Pilani
Pilani Campus
Common Source/ Emitter Amplifier
• CSA
• CEA
CSA amplifier
with drain-to gate feedback bias
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Bits, pilani
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CSA amplifier
with potential divider bias
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CSA with current mirror bias
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Small signal analysis
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Pmos CSA
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Common Source
Bias point
Given--Kn’= 80uA/v2, Vt=1v, Vdd= 5v
Suppose, we want Id= 100uA, Vds= 2.5v,
This gives ----
Rd= 25k
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Design of common source amplifier
for gain specification
• To set gain
• Av= 30 = - gm [ RD || ro ]
• ro=1/ λId = 1M ohm; λ= .01V-1
• gm= 1.2 mA / V = 2 Id / Vov
• Hence, Vov= 0.166V [designers choice depends on
VDD, Small value for small supply ]
gm= 1.2 mA / V = Kn’ (w/L) Vov
• W/L= 90.3, Vgs= 1.166V
Practical design
• Sketch VTC
• Choose bias current, choose a w/L
• Find corresponding Vgs, Vds, re calculate Rd,
w/L
• Draw the schematic in eda tool
• Set voltages by applying sources
• Do .dc analysis
• Check all dc current and voltages
• Apply ac , check ac output. Do .ac analysis
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i/o phase relation ship
Lagging Phase Difference
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Voltage amplifier model of
CSA
Ro
+ + +
vi Ri vo
Avvi
- -
-
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CSA/ CGA/ CDA
CEA/ CBA/ CCA
Low Frequency Operation
CSA/ CGA/ CDA
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Direct/ capacitivly coupled
CGA
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Diff. ---- Low frequency / high
frequency performance
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MOSFET capacitances
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Gain calculation
Small signal model
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CDA--Av variation
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Rin, Rout, o/p voltage swing
GAIN and SWING
Compatibility
What if gain is high but not sufficient voltage swing ?
• Output will be distorted as MOSFET slips in LINEAR/
CUTOFF region
• Hence, output voltage swing calculation is important
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Output voltage swing under dynamic
state
• Constraint---MOS must
remain in saturation
• Vo max→≈Vdd
• Vomin→ Vgs-Vt
• Output DC level→[Vdd-IdRd]
Vdd= 3V
Reduced upper swing
Dc level
Reduced lower swing
Vgs-Vt = 0.2
For symm. signal—dc level shd. be in the middle for max swing
Rin, Rout
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CGA-- Rin
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CGA-- Rin
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Source Follower-- Rout
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Resistive load amplifier
Output Voltage swing
Vomax---- Vdd
Vomin---- Vov1
For Vdd=3v, Vgsp = Vgsn =0.9v, Vt=0.7v
Vomax---- 3V
Vomin---- 0.2 V
} 2.8 V
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CSA/ CGA/ CDA
Max. Gain---- maximize load, R→ ∞
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Non ideal current source
(active ) load
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Active load amplifier
Output Voltage swing
Vomax---- Vdd - Vov2
Vomin---- Vov1
For Vdd=3v, Vgsp = Vgsn =0.9v, Vt=0.7v
Vomax---- 0.2v
Vomin---- 2.8v
} 2.6v
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Gain comparison
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Benefit of active load
Benefit:
• Less silicon
• High impedance leads to high gain
• DC at output is dynamic (adjust on its own)
Drawback:
• Voltage swing reduces
• Transistor count increase
• Power dissipation increases (reference arm added)
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Active load amplifier
Different Active loads
• Diode connected load
• NMOS/ PMOS lin. enhancement load (triode load) χ
• NMOS/ PMOS sat. enhancement load
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Preferred Active load
• Current mirror load
• Reason---High impedance ro
• Hence, high gain
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Impedance (in ac conditions)
calculation
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•NMOS/ PMOS sat. enhancement load
Diode connected load
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Active load amplifiers
Active load amp,
Gain calculations
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Active load amplifier
pmos
Small value
Gain depends on device dim
for same I.
Also on µp if load is pmos
Gain improvement technique for
diode connected load—inc. I1
I1/4
But Vgs of M1 will increase
to carry 4I current. Swing reduces Double gain
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Adv.- diode connected load
amp.
Here, gain depends only on device dim. ---so, linear
amplification, less distortion
For lin. Amp. ----Gain shd. be independent of bias
voltages and current
Reason---
|Av|= gm Rd changes as gm changes with the input
signal swing (though close to Q point)
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Triode load
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Active load CGA
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Active load Source follower
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Source Follower-
DC Level shifter, impedance
matching
Source follower as DC Level
shifter
How much shift?
Vout dc= Vindc-Vgs
Vgs can be adjusted for a
given Ibias by adjusting w/L
Used in push pull amplifier for
shifting
dc bias
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Ex1- DC level shifter
Pmos requires high Vg, Swing requirement
nmos requires low Vg
Vgs for both transistors Level shifter circuit
are not optimized here.
vin
vin
vin
Ex2- level shifter
Charac. Of source follower
• Rin--high
• Rout--low
• Av ≈1
• It reduces Vswing of previous stage
• Non linearity due to gmb
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Vmin at x node of successor
constraint
↓
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Amplifier Gain enhancement
Trade offs
Maximum gain possible
(intrinsic gain)
• Av= - gm ro
• Make Rd infinite
• But this will make VRd=Vdd, MOS
goes to cutoff
• How?---Rd replaced by current
source
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Gain in active region
Av increases with W/L, VRD, or by dec ID
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Design Parameter affecting
gain
Av increases with W/L, VRD, or by dec ID
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Trade offs
W/L increased keeping ID and VRD constant
---greater device capacitance at output , time constant
increases, speed of response is affected
---less overdrive voltage reqd. ( as Id constt.) so vomin
reduces
output swing range increases, bias point will shift
----gain increases
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Bias point for increased (w/L)--- ID and V RD constant
(w/L) 2 large
(w/L) 1 small
vgs 2 vgs 1
small large
(w/L) 2 > (w/L) 1
Id =
Vdd/Rd
ID and VRD constant
Q1, Q2 vgs1
(w/L)2 large vgs2
Vov2 less
Less lower
swing
(w/L)1 small
Vov1 more
More lower swing
Vdd
vov2 vov1
VdS
less more
VRD increased keeping Id and
W/L constant
Gain increases
Vdd - VRd inc., or Vout max reduces,
→output swing range decreases,
→MOS shifts towards triode region,
→Voltage swing is limited
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Bias point for increased VRD -----
-ID and w/L constant
vgs 1,2
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(VRD)2 > (VRD)1
Id=
Vdd/Rd Id and W/L constant
(VRD)2 large
Q2
vgs
Q1
Less lower swing
(VRD)1small
More lower swing
vds2 vds1 Vdd
less more VdS
ID dec. keeping VRD and W/L
const.
ID reduces---to keep VRd constant Rd
must increase,
→So, Rout shd. be increased
→time constant increases,
→So, speed of response is affected
→ Vgs must dec.
Gain increases
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Bias point for decreased (ID)---
(w/L) and VRD constant
vgs 2 vgs 1
small large
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VRD and W/L constt. (Id)2 < (Id)1
Id=
Vdd/Rd
Q1
vgs1
(Id) 2 small
vgs2
Vov2 less
Q2
Less swing
((Id)1 large
Vov1 more
More swing
Vdd
vov2 vov1
VdS
less more
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Voltage gain = Gm* Rout
Gm, Rout
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CSA , Av = Gm Rout
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CSA with source degeneration
Remove capacitor
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Gm----Small signal model
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gm
• For Rs=0, Gm = gm
• For Rs ≠ 0, Gm < gm
Gm from small signal model without
ro and gmb intuitive analysis
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Gm--- Circuit trans-
conductance
Voltage Gain
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Gm decreases --csa/ csa-Rs
Without Rs With Rs
Gm=
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Trans-conductance variation-
comparison
Gm=
Without Rs With Rs
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Gm decreases. why ?
Because
Input going
to
amplifier
reduces
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Rout----Small signal model
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Rout’
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Voltage gain
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Why Rout increases due to Rs?
A high impedance at a node means if voltage at that
node is changed slightly, current through that node
does no change much.
Here we achieve this at Vout node through negative
feedback action in vgs.---
If Vout ↑---Id ↑ (effect comes through ro)
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Voltage gain (from ac model)
If ro >> Rs, Rd
• Vout ↑---Id ↑ --- vs ↑--- Vgs ↓--- Id ↓
• (effect comes through (1+λ Vds)
• At the same time, due to Vout ↑ , a voltage vs
vs appears at source
• Vs causes reduction in Vgs, due to which Id
falls more due to square dependence on
Vgs
• Hence Id changes little in comparison to
change in vout
• So Rout increases
Benefit/ drawback
Advantage—
• Non linearity decreases as Id varies less w.r.t vin
variations, Q point is more stable
• Output impedance increases
Drawback--
• Vgs < vin, gain reduces
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Comparison—CSA/ CSA-Rs
With Rs
Without Rs With Rs
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Nonlinearity reduction- Q
point stable
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Amplifiers with increased voltage/
current gain
Cascode amplifier (high gain)
Cascode Amplifier---
• Modified CSA with cascode load
• CSA-CGA Cascade
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Cascode amplifier--
Modified CSA
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CASCODE amp with cascode
load
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Cacode amp---
CSA-CGA Cascade
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Anu Gupta
Resistive load
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Output Voltage swing, Rin,
Rout
Bits, pilani
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Cascode amp with current
bias
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BICMOS Cascode amplifier
BJT + MOSFET
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Cascode amp with current
bias--- capacitor???
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Multi Stage amplifiers– increased
voltage/ current gain, beyond gmro
2 Stage amplifier-- -- active
load (ro)
• CSA, CSA--- Rin- high, Rout –high, Av– high, in phase
• CGA, CGA--- Rin- low, Rout –high, Av– high, out of phase
• CSA, CGA---Rin- high, Rout –high, Av– low, out of phase
• CGA, CSA---Rin- low, Rout –high, Av– high, out of phase
• CGA, SF--- Rin- low, Rout –low, Av– low, in phase
• CSA, SF---Rin- high, Rout –low, Av– low, out of phase
• SF, CSA-- Rin- high, Rout –high, Av– low, out of phase
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End