STF6N65K3 STMicroelectronics
STF6N65K3 STMicroelectronics
Features
Order codes VDSS RDS(on) max. ID Ptot
STF6N65K3 TAB
30 W
STFI6N65K3 650 V < 1.3 Ω 5.4 A
STU6N65K3 110 W 3
3
2 1 2
1 2
3 1
■ 100% avalanche tested
TO-220FP I²PAKFP IPAK
■ Extremely high dv/dt capability
■ Gate charge minimized
■ Very low intrinsic capacitance
■ Improved diode reverse recovery
characteristics
Figure 1. Internal schematic diagram
■ Zener-protected
D(2,TAB)
Applications
■ Switching applications
Description G(1)
STF6N65K3 TO-220FP
STFI6N65K3 6N65K3 I²PAKFP Tube
STU6N65K3 IPAK
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) .......................... 6
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1 Electrical ratings
2 Electrical characteristics
Drain-source
V(BR)DSS ID = 1 mA, VGS = 0 650 V
breakdown voltage
Zero gate voltage VDS = 650 V 0.8 µA
IDSS
drain current (VGS = 0) VDS = 650 V, TC=125 °C 50 µA
Gate-body leakage
IGSS VGS = ± 20 V ±9 µA
current (VDS = 0)
VGS(th) Gate threshold voltage VDS = VGS, ID = 50 µA 3 3.75 4.5 V
Static drain-source
RDS(on VGS = 10 V, ID = 2.7 A 1.1 1.3 Ω
on-resistance
Table 5. Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit
Input capacitance
Ciss 880 pF
Output capacitance
Coss VDS = 50 V, f = 1 MHz, VGS = 0 - 65 - pF
Reverse transfer
Crss 12 pF
capacitance
Eq. capacitance time
Co(tr)(1) - 43 - pF
related
VGS = 0, VDS = 0 to 520 V
Eq. capacitance
Co(er)(2) - 27 - pF
energy related
Intrinsic gate
RG f = 1 MHz open drain - 3.5 - Ω
resistance
Qg Total gate charge VDD = 500 V, ID = 5.4 A, 33 nC
Qgs Gate-source charge VGS = 10 V - 4 - nC
Qgd Gate-drain charge (see Figure 18) 21 nC
1. Coss eq. time related is defined as a constant equivalent capacitance giving the same charging time as Coss
when VDS increases from 0 to 80% VDSS
2. Coss eq. energy related is defined as a constant equivalent capacitance giving the same stored energy as
Coss when VDS increases from 0 to 80% VDSS
The built-in back-to-back Zener diodes have specifically been designed to enhance not only
the device’s ESD capability, but also to make them safely absorb possible voltage transients
that may occasionally be applied from gate to source. In this respect the Zener voltage is
appropriate to achieve an efficient and cost-effective intervention to protect the device’s
integrity. These integrated Zener diodes thus avoid the usage of external components
1ms
10ms
0.01
0.001
0.1 1 10 100 VDS(V)
Figure 4. Safe operating area for IPAK Figure 5. Thermal impedance for IPAK
AM12961v1
ID
(A) Tj=150°C
Tc=25°C
Single pulse
10µs
10
is
a
n)
R e
100µs
ax ar
(o
DS
m is
by in th
ite tion
Lim era
1
d
1ms
Op
10ms
0.1
0.1 1 10 100 VDS(V)
10
8
8
6V 6
6
4
4
2
2
0 0
0 10 20 VDS(V) 0 2 4 6 8 VGS(V)
Figure 10. Capacitance variations Figure 11. Output capacitance stored energy
AM12966v1 AM12967v1
C Eoss
(pF) (µJ)
5
1000 Ciss
4
100 3
Coss 2
10
Crss
1
1 0
0.1 1 10 100 VDS(V) 0 100 200 300 400 500 VDS(V)
Figure 12. Normalized gate threshold voltage Figure 13. Normalized on-resistance vs
vs temperature temperature
AM12968v1 AM12969v1
VGS(th) RDS(on)
(norm) (norm)
ID=50µA VGS=10V
1.10 VDS=VGS ID=2.7A
2.5
1.00 2.0
1.5
0.90
1.0
0.80
0.5
0.70 0
-75 -25 25 75 125 TJ(°C) -75 -25 25 75 125 TJ(°C)
Figure 14. Normalized BVDSS vs temperature Figure 15. Source-drain diode forward
characteristics
AM12970v1 AM12971v1
BVDSS VSD
(norm)
(V)
ID=1mA TJ=-50°C
1.0
1.10
TJ=25°C
0.8
1.05
TJ=150°C
0.6
1.00
0.4
0.95
0.2
0.90 0
-75 -25 25 75 125 TJ(°C) 0 1 2 3 4 5 6 ISD(A)
80
60
40
20
0
0 20 40 60 80 100 120 TJ(°C)
3 Test circuits
Figure 17. Switching times test circuit for Figure 18. Gate charge test circuit
resistive load
VDD
12V 47kΩ
1kΩ
100nF
RL 2200 3.3
μF μF
VDD IG=CONST
VD Vi=20V=VGMAX 100Ω D.U.T.
VGS 2200
RG D.U.T. μF 2.7kΩ VG
PW
47kΩ
PW 1kΩ
AM01468v1 AM01469v1
Figure 19. Test circuit for inductive load Figure 20. Unclamped inductive load test
switching and diode recovery times circuit
L
A A A
D
FAST L=100μH VD
G D.U.T. DIODE 2200 3.3
μF μF VDD
S B 3.3 1000
B B μF μF
25 Ω VDD ID
D
RG S
Vi D.U.T.
Pw
AM01470v1 AM01471v1
Figure 21. Unclamped inductive waveform Figure 22. Switching time waveform
90% 90%
IDM
10%
ID 10% VDS
0
A 4.4 4.6
B 2.5 2.7
D 2.5 2.75
E 0.45 0.7
F 0.75 1
F1 1.15 1.70
F2 1.15 1.70
G 4.95 5.2
G1 2.4 2.7
H 10 10.4
L2 16
L3 28.6 30.6
L4 9.8 10.6
L5 2.9 3.6
L6 15.9 16.4
L7 9 9.3
Dia 3 3.2
7012510_Rev_K_B
A 4.40 4.60
B 2.50 2.70
D 2.50 2.75
D1 0.65 0.85
E 0.45 0.70
F 0.75 1.00
F1 1.20
G 4.95 - 5.20
H 10.00 10.40
L1 21.00 23.00
L2 13.20 14.10
L3 10.55 10.85
L4 2.70 3.20
L5 0.85 1.25
L6 7.30 7.50
REV!
A 2.20 2.40
A1 0.90 1.10
b 0.64 0.90
b2 0.95
b4 5.20 5.40
0.3
B5
c 0.45 0.60
c2 0.48 0.60
D 6.00 6.20
E 6.40 6.60
e 2.28
e1 4.40 4.60
H 16.10
L 9.00 9.40
L1 0.80 1.20
L2 0.80 1.00
V1 10 o
0068771_J
5 Revision history
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