ARM Processor – Instruction Set
Lecture on ARM7 Instruction set
By
Harish V. Mekali
Assistant Professor, Dept. of ECE
BMSCE, Bangalore - 19
Register Organization - CPSR
05-01-2017 ARM Processors - Instruction Set 2
Condition Mnemonics
Fig : Condition mnemonics that can be added to basic instructions
05-01-2017 ARM Processors - Instruction Set 3
Instruction Set & Processor State
05-01-2017 ARM Processors - Instruction Set 4
Instruction set
Classification of instructions
1. Data Processing Instruction
- Data movement , Arithmetic, Logical, Comparison, Multiply
2. Branch instructions
3. Load – store instructions
- Single register, Multiple register, Stack operations, Swap
4. Software interrupt instructions
5. Program Status Register instructions
05-01-2017 ARM Processors - Instruction Set 5
Data Processing Instructions
- Most of the data processing instructions can process one operand using
barrel shifter
Data movement instructions
- “S” suffix with MOVE operations can update the C, Z, N flags in CPSR
- “N” can be register or immediate data
- Example : MOV instruction without and with barrel shifter operations
05-01-2017 ARM Processors - Instruction Set 6
Barrel Shifter Operations
05-01-2017 ARM Processors - Instruction Set 7
Arithmetic Instructions
- “N” is the result of shift operation
- Example :
05-01-2017 ARM Processors - Instruction Set 8
Logical Instructions
- Updates CPSR only if suffix “S” is added and logical instructions
can also use barrel shifter in the same way as MOVE and
arithmetic
- Example :
05-01-2017 ARM Processors - Instruction Set 9
Comparison Instructions
- Updates CPSR only without affecting the register content and this
can be used in conditional execution
- TST is logical AND and TEQ is a logical XOR operation
- Example :
05-01-2017 ARM Processors - Instruction Set 10
Multiply Instructions
- Example :
05-01-2017 ARM Processors - Instruction Set 11
Branch Instructions
- Address label is stored with instruction as a PC relative offset and it must
be approximately 32 MB
- BX and BLX are primarily used for branch to and from Thumb code . “T”
bit in CPSR is updated by least significant bit of branch register
05-01-2017 ARM Processors - Instruction Set 12
Branch Instructions
- Example :
05-01-2017 ARM Processors - Instruction Set 13
Load and Store Instructions
05-01-2017 ARM Processors - Instruction Set 14
Load and Store Instructions
05-01-2017 ARM Processors - Instruction Set 15
Load and Store Instructions
05-01-2017 ARM Processors - Instruction Set 16
Load and Store Instructions
05-01-2017 ARM Processors - Instruction Set 17
Swap Instructions
- Its an atomic operation – It reads and writes
location in the same bus operation
preventing any other instruction from
reading and writing to the location until it
completes
05-01-2017 ARM Processors - Instruction Set 18
Program Status Register Instructions
- CPSR_<fields> refer to Control (C) , Extension (x) , Status (s) , Flags (f)
05-01-2017 ARM Processors - Instruction Set 19
Coprocessor Instructions
- “cp” field in the syntax refer to coprocessor number p0 to p15.
- “opcode” field refer to operation to take place on coprocessor
-
05-01-2017 ARM Processors - Instruction Set 20
Thank you
05-01-2017 ARM Processors - Instruction Set 21
Harish V. Mekali
Assistant Professor, Dept. of ECE, BMSCE
[Link]@[Link] / harishmekali@[Link]
+91-9538765141
[Link]
05-01-2017 ARM Processors - Instruction Set 22
I acknowledge and appreciate ARM University Program(AUP)
and ARM Embedded Systems pvt. Ltd. for their continuous
support.
05-01-2017 ARM Processors - Instruction Set 23
References
Video lectures :
1. Mr. Chrish Shore, ARM Training Manager, UK
The ARM University Program, ARM Architecture Fundamentals
( [Link] )
2. Dr. Santanu Chaudhury, Dept. of Electrical Engineering, IIT Delhi
Lecture - 5 ARM : ( [Link] )
Website :
3. [Link]
Textbooks:
1. ARM system developers guide, Andrew N Sloss, Dominic Symes and Chris
Wright, Elsevier, Morgan Kaufman publishers, 2008.
2. ARM System-on-Chip Architecture, Steve Furber, Second Edition,
Pearson, 2015
05-01-2017 ARM Processors - Instruction Set 24