CAN-PCIe/402-FD

PCI Express® Board with up to 4 CAN-FD Interfaces

Single Lane PCIe Board with Intel® FPGA CAN Data Management
for up to 4x CAN FD The FPGA supports bus mastering (first-
• 1x,2x or 4x CAN FD interfaces according party DMA) to transfer data to the host
to ISO 11898-2, up to 8 Mbit/s memory. This results in a reduction of overall
• Bus mastering and local data latency on servicing I/O transactions in
management by FPGA (esdACC) particular at higher data rates and a reduced
• PCIe® interface according to PCI Express host CPU load.
Specification R1.0a Due to the usage of MSI (Message Signaled
Interrupts) the CAN-PCIe/402-FD can be
• Selectable CAN termination on board
operated for example in Hypervisor
• Supports MSI (Message Signaled
environments.
Interrupts) CAN-PCIe/402-2-FD
(C.2045.64) The CAN-PCIe/402-FD provides high
resolution hardware timestamps.
Wide Range of Operating System
Support and Advanced CAN Diagnostic
Wide Choice of Hardware Designs Software Support
• Software drivers for Windows® and
The CAN-PCIe/402-FD is a PC board Windows and Linux (NTCAN-API)
Linux® included free of charge
designed for the PCIe bus that features one The CAN layer 2 drivers for Windows and
• Optional CAN layer 2 software drivers for (CAN-PCIe/402-1-FD) or two (CAN- Linux are included in the scope of delivery.
real-time operating systems PCIe/402-2-FD) electrically isolated CAN FD
• CANopen®, J1939 and ARINC 825 interfaces according to ISO 11898-2 via Real-time OS (NTCAN-API)
protocol libraries DSUB9 connectors. CAN layer 2 drivers for QNX® RTX® and
• ISO 16845:2004 certified esd Advanced Equipped with up to two CAN FD interfaces RTX64® can be ordered separately.
CAN Core (esdACC) technology the board is available as low-profile versions
(CAN-PCIe/402-1-LP-FD and -LP2-FD). Higher Layer Protocols
Variety of Product Designs Four CAN FD interfaces can be connected (Classical CAN application only)
• 4x CAN FD via 1x DSUB37 via one 37-pin DSUB connector in the Higher Layer Protocols are available for
• Low profile version for 1x or 2x CAN FD version CAN-PCIe/402-B4-FD/1Slot. many operating systems (see order info):
• CANopen Master- and Slave-Stack
CAN FD • J1939
The CAN FD interfaces are designed • ARINC825
according to ISO 11898‑1:2015. They are
driven by the ISO 16845:2004 certified Customization on Request
esdACC (esd advanced CAN Core) Customized options are available for
implemented in the Intel FPGA. customized series production in reasonable
All CAN FD versions are fully backward quantities. Please contact our sales team for
compatible with CAN and can also be detailed information.
used in Classical CAN applications.

Technical Specifications:
PCI Express Interface: Order Information:
PCIe port PCI Express Spec. R1.0a, Link width 1x Hardware Order No.
CAN: CAN-PCIe/402-1-FD 1x CAN FD (CAN1 only), via DSUB9 C.2045.62
Interface 1x, 2x or 4x CAN FD interfaces according to ISO 11898-2, CAN-PCIe/402-2-FD 2x CAN FD (CAN1, CAN2) via DSUB9 C.2045.64
bit rates from 10 kbit/s up to 8 Mbit/s (with the same CAN CAN-PCIe/402-B4-FD/1Slot 4x CAN FD via DSUB37 connector C.2045.68
transceiver), with or without electrical isolation CAN-PCIe/402-1-LP-FD Low-profile format, 1x CAN FD (CAN1) C.2045.92
CAN-PCIe/402-1-LP2-FD Low-profile format, 1x CAN FD (CAN2) C.2045.94
CAN controller esdACC in EP4CGX Intel FPGA,
acc. to ISO 11898-1:2015 Accessories
General: CAN-PCI/4XX- 4-FD-1C4 Adapter cable DSUB37 to 4x DSUB9 C.2041.18
Power supply 3.3 V: 2x CAN IMAX = 280 mA, Software Support 1
4x CAN IMAX = 290 mA
CAN layer 2 drivers for Windows/Linux are included in delivery free of charge.
12 V: 2x CAN IMAX = 180 mA,
Additional CAN layer 2 object licences including CD-ROM:
4x CAN IMAX = 230 mA
CAN-DRV-LCD QNX Object Licence for QNX6, QNX7 C.1101.32
Ambient temp. 0 °C ... +75 °C
CAN-DRV-LCD RTX Object Licence for RTX64 C.1101.35
Rel. humidity Max. 90 % (non-condensing)
Higher CAN layer protocols including CD-ROM for Classical CAN Application:
Connector PCIe: PCIe card edge connector
CANopen-LCD Windows/Linux, RTX or QNX [Link]
CAN: All except C.2045.68:
J1939 stack for Windows, Linux [Link]
1x 9-pin DSUB per CAN channel, pin contacts
ARINC 825-LCD Windows/Linux, RTX or QNX [Link]
C.2045.68 only: 1x 37-pin DSUB (4 CAN channels),
1 For detailed information about driver availability for your operating system please contact our sales team.
pin contacts
Weight CAN-PCIe/402-2-FD: 60 g

esd electronics gmbh Phone: +49 (0) 511 3 72 98-0

Vahrenwalder Str. 207 Fax: +49 (0) 511 3 72 98-68
30165 Hannover / Germany E-mail: info@[Link]
CAN-PCIe/402-FD
Driven by esdACC-FD (Advanced CAN Core)

Basic Product Features:

• CAN ISO 11898-1:2015 protocol compatibility
• Tested and certified acc. to ISO CAN Conformance Tests
“ISO 16845:2004 Road vehicles - Controller area network (CAN)
- Conformance test plan”
• 11-bit and 29-bit CAN IDs
• Supported bit rates: From 10 kbit/s up to 8 Mbit/s
• Receive buffer (64 CAN messages)
• Complete access to CAN error counters
• Programmable error warning limit
• Error code capture register
• Error interrupt for each CAN bus error
• Arbitration lost interrupt with detailed bit position
• Listen only mode (no acknowledge, no active error flags)
• Automatic bit rate detection (hardware supported bit rate
detection)
• Self-reception mode (reception of ‘own’ messages)
• Busload measurement

Superior esdACC Features 1: Superior esdACC Features (continued) 1:

• Operating system independently programmable via esd's • Hardware timer to provide accurate software timeouts beyond
NTCAN-API operating system accuracy
• 32-bit register interface optimized for CAN needs • Bus mastering in RX direction takes the load off host CPU (needs
• Easy to program bus master capable local bus to host interface)
• Transmission and reception of CAN frames with a minimum of • Optional different sources for timestamps (e.g. IRIG-B)
register accesses
• Using FPGA technology provides the option to tailor any feature
• RX and TX timestamping (64-bit wide, bit accurate, resolution to any customer's needs, including optional integration with
may vary with input clock, in any case ≤ 62.5 ns, usually 12.5 ns) customer's FPGA content
• Timestamping complies with the CiA 603 specification
• On hardware with IRIG-B interfaces IRIG-B time is used for • The esdACC IP core has been verified on Xilinx® Spartan® and
timestamping Intel® Cyclone® FPGAs.
1
Availability of the Superior esdACC Features depends on the operating
• TX FIFO (16 CAN frames deep) system. Please contact our sales team for further information.
• Providing the means to generate 100% busload even with
non-real-time operating systems
• Providing the means for real back-to-back transmission
• Timestamped Tx FIFO (16 CAN frames deep)
• High priority
• 64-bit timestamp
• Bit time accuracy for CAN transmission
For further information on the esdACC IP Core please contact our
• Frame accurate abortion of transmissions with minimum delay
sales team.
• e.g. for driver timeouts
• ISO11898-1:2015 conform
• Aborted frames in FIFO won't be blocked by low priority TX

©2022 esd electronics gmbh, Hannover All data are subject to change without prior notice. CiA® and CANopen® are registered EU trademarks of CAN in Automation e.V..
File: CAN-PCIe402-FD_Datasheet_en_15.docx Rev.: 1.5 • Date: 2022-04.06 All trademarks are reserved by their respective owners.
esd electronics gmbh Phone: +49 (0) 511 3 72 98-0
Vahrenwalder Str. 207 Fax: +49 (0) 511 3 72 98-68
30165 Hannover / Germany E-mail: info@[Link]