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VHDL Flip-Flop and Sequential Logic Design

1. The document describes an activity on VHDL block diagramming of flip-flops and sequential logic circuits. It involves simulating flip-flop operations and designing counters using different types of flip-flops. 2. Students will learn to simulate sequential circuits using VHDL, design counters using flip-flops, and verify their results. 3. The activity aims to program flip-flop characteristics and sequential logic circuits using Quartus II software. Students will generate vector waveforms for sample circuits.

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Dylan Cosep
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0% found this document useful (0 votes)
46 views9 pages

VHDL Flip-Flop and Sequential Logic Design

1. The document describes an activity on VHDL block diagramming of flip-flops and sequential logic circuits. It involves simulating flip-flop operations and designing counters using different types of flip-flops. 2. Students will learn to simulate sequential circuits using VHDL, design counters using flip-flops, and verify their results. 3. The activity aims to program flip-flop characteristics and sequential logic circuits using Quartus II software. Students will generate vector waveforms for sample circuits.

Uploaded by

Dylan Cosep
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

COMPUTER ENGINEERING DEPARTMENT

ACTIVITY 2: VHDL Block Diagram - Flip-flop Familiarization and Sequential Circuit Design

2.1 Program Outcomes (POs) Addressed by the Activity


a. ability to design and conduct fieldworks, as well as to analyse and interpret data
b. ability to function on multidisciplinary teams
c. ability to identify, formulate, and solve engineering problems
d. ability to use techniques, skills, and modern engineering tools necessary for engineering practice

2.2 Activity’s Intended Learning Outcomes (AILOs)


At the end of this activity, the student shall be able to:
a. simulate flip-flops operation using VHDL block diagram
b. design circuit block diagram of different sequential circuits such as counters
c. implement sequential circuit design using different types of flip flop
d. verify experimental results versus theoretical results

2.3 Objectives of the Activity


The objective of this activity is to:
a. program flip-flop characteristics and design of clocked sequential circuits using the Quartus II software.
b. generate a vector waveform from the given sample sequential logic circuit

2.4 Principle of the Activity

Flip-flop - is a circuit that has two stable states and can be used to store state information.

Sequential Logic Circuit - is a type of logic circuit whose output depends not only on the present value of
its input signals but on the sequence of past inputs, the input history.

Binary Counter - A counter is a digital sequential logic device that will go through a
certain predefined states (for example counting up or down) based on the application of the
input pulses.

VHDL - Very High Speed Integrated Circuit Description Language.

Quartus II - is software that provides a complete, multiplatform design environment that easily adapts to
your specific design needs.

2.5 Materials/Equipment

1 PC unit
1 Keyboard and Mouse

2.6 Procedure/s

A. Apply the necessary inputs of the given circuits/problem statement and record your result.

2.7 Activity Report

2.7.1 Data and Results

ACTIVITY 2: VHDL BLOCK DIAGRAM - FLIP FLOP AND SEQUENTIAL LOGIC CIRCUITS
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1. Circuit:
use clock overwrite: sw2=4us, sw3=2us, key0=1us, sw0=2us, sw1=8us.
Use grid size = 1us and end time = 16us
SW2

SW0 J
SET
Q LEDR0
KEY0
SW1 K CLR Q LEDR1

SW3
FIGURE 4-2. JKFF
Block Diagram:

ACTIVITY 2: VHDL BLOCK DIAGRAM - FLIP FLOP AND SEQUENTIAL LOGIC CIRCUITS
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Waveform:

Truth Table

0 0 Pulse 0 0 0 0
0 1 Pulse 1 1 0 1
1 0 Pulse 2 0 0 0
1 1 Pulse 3 1 0 0
0 0 Pulse 4 0 0 0
0 1 Pulse 5 1 1 1
1 0 Pulse 6 0 1 0
1 1 Pulse 7 1 1 0
0 0 Pulse 8 0 1 0
0 1 Pulse 9 1 0 1
1 0 Pulse 10 0 0 0
1 1 Pulse 11 1 0 0
0 0 Pulse 12 0 0 0
0 1 Pulse 13 1 1 1
1 0 Pulse 14 0 1 0
1 1 Pulse 15 1 1 0

ACTIVITY 2: VHDL BLOCK DIAGRAM - FLIP FLOP AND SEQUENTIAL LOGIC CIRCUITS
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2. Circuit:
use clock overwrite: set=1us, clear=1us, clk=2us
use forcing high to J & K.
Use grid size = 1us and end time = 32us
SET

1 J
SET
Q Q0

CLK

K CLR Q

CLEAR

J
SET
Q Q1

K CLR Q

J
SET
Q Q2

K CLR Q

J
SET
Q Q3

K CLR Q

FIGURE 4-4. BINARY COUNTER

ACTIVITY 2: VHDL BLOCK DIAGRAM - FLIP FLOP AND SEQUENTIAL LOGIC CIRCUITS
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Block Diagram:

Waveform:

Truth Table

ACTIVITY 2: VHDL BLOCK DIAGRAM - FLIP FLOP AND SEQUENTIAL LOGIC CIRCUITS
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1 1 Pulse 0 1 1 1 1 1 1
1 1 Pulse 1 1 1 0 1 1 1
1 1 Pulse 2 1 1 1 0 1 1
1 1 Pulse 3 1 1 0 0 1 1
1 1 Pulse 4 1 1 1 1 0 1
1 1 Pulse 5 1 1 0 1 0 1
1 1 Pulse 6 1 1 1 0 0 1
1 1 Pulse 7 1 1 0 0 0 1
1 1 Pulse 8 1 1 1 1 1 0
1 1 Pulse 9 1 1 0 1 1 0
1 1 Pulse 10 1 1 1 0 1 0
1 1 Pulse 11 1 1 0 0 1 0
1 1 Pulse 12 1 1 1 1 0 0
1 1 Pulse 13 1 1 0 1 0 0
1 1 Pulse 14 1 1 1 0 0 0
1 1 Pulse 15 1 1 0 0 0 0

3. Problem Statement:
Design a 3 bit Down-Counter Sequential Circuit using T Flip-flops.
use clock overwrite: clk=1us, set=1 and clear = 1
Use grid size = 1us and end time = 8us
Truth Table, Kmap and state equation

0 0 0 1 1 1 1 1 1
0 0 1 0 0 0 0 0 1
0 1 0 0 0 1 0 1 1
0 1 1 0 1 0 0 0 1
1 0 0 0 1 1 1 1 1
1 0 1 1 0 0 0 0 1
1 1 0 1 0 1 0 1 1
1 1 1 1 1 0 0 0 1

ACTIVITY 2: VHDL BLOCK DIAGRAM - FLIP FLOP AND SEQUENTIAL LOGIC CIRCUITS
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KARNAUGH MAP KARNAUGH MAP KARNAUGH MAP
TA = (BC)’ TB = C’ TC = 1

Block Diagram:

Waveform:

ACTIVITY 2: VHDL BLOCK DIAGRAM - FLIP FLOP AND SEQUENTIAL LOGIC CIRCUITS
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Truth Table

1 1 Pulse 0 1 1 1 1
1 1 Pulse 1 1 1 1 0
1 1 Pulse 2 1 1 0 1
1 1 Pulse 3 1 1 0 0
1 1 Pulse 4 1 0 1 1
1 1 Pulse 5 1 0 1 0
1 1 Pulse 6 1 0 0 1
1 1 Pulse 7 1 0 0 0

2.7.2 Observations

2.7.3 Conclusion/s

ACTIVITY 2: VHDL BLOCK DIAGRAM - FLIP FLOP AND SEQUENTIAL LOGIC CIRCUITS
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2.7.4

Section: TE31 Date Performed: February 8, 2022

Course Code: CPE0027L Date Submitted: February 8, 2022

Course Title: Introduction to HDL

Instructor: Engr. Maribel Misola Activity No.: Formative 2

Student Name: Roxas, Alexis Angel B. Signature:

2.7.5 Rubrics/Rating

Criteria Grade

Activity Conduct (1-5)

Correctness of Command(s)/Program(s) (1-5) x 2

Completeness of Tasks (1-5)

Data Analysis and Results Interpretation (1-5)

Total Score

Mean Score = (Total Score / 5)

Percentage Score = (Total Score/25) * 100


Other Comments:

ACTIVITY 2: VHDL BLOCK DIAGRAM - FLIP FLOP AND SEQUENTIAL LOGIC CIRCUITS
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Powered by TCPDF ([Link])

Common questions

Powered by AI

A flip-flop is a circuit with two stable states, enabling it to store state information. In sequential logic circuits, the flip-flop maintains the output state even after the input signal has changed, thus allowing the circuit to 'remember' previous states .

Students are expected to gain the ability to simulate the operation of flip-flops using VHDL block diagrams, design circuit block diagrams of sequential circuits, implement designs using various flip-flops, and verify results against theoretical predictions, thereby developing practical engineering skills .

Truth tables provide a clear representation of all possible input and output states, useful for verifying correct circuit behavior. Karnaugh maps help simplify boolean expressions by visually organizing truth table information, reducing logic expressions and making circuit designs more efficient and easier to troubleshoot .

Tools like Quartus II are important because they provide a comprehensive design environment for constructing and testing digital circuits. They enable designers to simulate circuits, analyze waveforms, and ensure that proposed designs meet specifications. This reduces errors and speeds up the development process, allowing for efficient iteration and improvement .

Sequential logic circuits differ from combinational logic circuits as their output depends on the sequence of past inputs in addition to the current inputs, making them state-dependent. In contrast, combinational circuits generate output solely based on the current input signals without any dependency on past inputs .

The procedural steps include applying necessary inputs to pre-designed circuits, recording the subsequent outputs, and comparing these outputs with expected results. The procedure involves simulation, debugging, and analysis using VHDL block diagrams to validate circuit behavior .

When designing a 3-bit Down-Counter using T Flip-flops, considerations include ensuring that the flip-flops’ toggle function is correctly implemented to decrement the count, managing propagation delay, setting proper clock settings for synchronization, and using Karnaugh maps to simplify logic expressions for efficient operation .

A binary counter exemplifies the concept of sequential logic circuits as it progresses through a predetermined series of states in response to input pulses. The counter's next state depends on both its current state and input, illustrating how sequential circuits track and react to input sequences over time .

Simulation and implementation are crucial in understanding flip-flops as they allow engineers to model the behavior and function of digital circuits before the actual hardware is constructed. Simulating the operation helps in validating that theoretical design matches the practical functionality, identifying issues in circuit design, and optimizing the system .

The effectiveness of a sequential logic activity can be evaluated based on criteria such as correctness of implemented programs, completeness of executed tasks, data analysis quality, and interpretation of results. These factors together determine the student's ability to apply theoretical knowledge practically .

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