ANALOG DEVICES LC’M0s Complete, High Speed 12-Bit ADC AD7572A FEATURES Improved AD7572 Faster Conversion Time ‘AD7S72AXX03: 3 ns ‘AD7572AXX10: 10 ps 5 V and ~12V or -15 V Power Supply Operation Better Offset and Gain Error Specifications Extended Plastic Temperature Range {40°C to +85°C) Low Powor: 100 mW. ‘Small 24-Pin, 0.3" Wide DIP and SOIC DIP Packages GENERAL DESCRIPTION ‘The AD7S72A is an enhanced replacement for the industry stan dard AD7572. Improvements include faster conversion times of, 3 us for the AD7S72AXX03 and 10 ys for the AD?ST2AXX10. TThe required power supplies are SV and ~12 V or =15 V. Ad- ditional features are better offset and gain error specifications over the original AD7S72. ‘The AD7572A is a complete 12-bit ADC that offers high speed performance combined with low, CMOS power levels. The part uses an accurate, high speed DAC and comparator in a successive-approximation loop to achieve a fast conversion time. ‘An on-chip buried Zener diode provides a stable reference volt age to give low drift performance over the full temperature range and the specified accuracy is achieved without any user trims. An on-chip clock circuit is provided, which may be used ‘with a crystal for stand-alone operation, or the clock input may be driven from an external clock source such asa divided-down ‘microprocessor clock. The only other external components re {uired for basic operation of the AD7572A are decoupling ca- pacitors forthe supply voltages and reference output The AD7S72A has a high speed digital interface with three-state data outputs and can operate under the control of standard mi- croprocessor Read (RD) and decoded address (CS) signals. In- terface timing is sulfcienly fast to allow the AD7S72A to ‘operate with most microprocessors, with three-state enable times of only 90 ns and bus relinquish times of 75 ns. ‘The AD7S72A is fabricated in Analog Devices Linear Compat ble CMOS process (LC’MOS), an advanced all ior-implanted process that combines fast CMOS logic and linear, bipolar cir cuits om a single chip, thus achieving excellent linear perfor- mance while retaining low CMOS power levels. Anslog Devices is believed tobe accurate and nsibityis assumed by Analog Device fort ‘ahs of hira porte FUNCTIONAL BLOCK DIAGRAM rt roa (ee 5 H-O-SG PRODUCT HIGHLIGHTS 1, Fast Conversion Time Fast, 3 4s and 10 4s conversion times make the AD7S72A, idea! for DSP applications and wideband data acquisition systems, 2. Wide Power Supply Range ‘The AD7572A operates from 5 V and ~12 V power supplies. 3. Microprocessor Interface Fast, easy-to-use digital interface has three-state bus access times of 90 ns and bus relinguish times of 75 ns allowing the ADTS72A to interface to most microprocessors. 4. Low Power LC'MOS cireuitry gives low power drain (100 mW) from +5, =12 volt supplies. 5. 24-pin 0.3" DIP and SOIC packages offer space saving over parts in 28-pin 0.6" DIP. One Technology Way, P.0. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617132046700 Fax: 617/326-8703 Tw: 710/996-6577 “Telex: 924491 Cable: ANALOG NORWOODMASS.(op = +5V + 5%, Vos = —114 V to —165 V, AGND = DGND = OV, fey: AD7572A—SPECIFICATIONS 12'es corse nse Spectators agp to Sow Monon tae) La L 3 Parameter Version' | Version’ | Unite ‘Test Conditions/Comments ‘ACCURACY Resolution 2 Bas Integral Nonlinearity @ 25°C 212 LSB max Tran © Tae =u CSB max Differential Nonlinearity = SB max ‘Minimum Resolution for Which No ‘Missing Codes Are Guarameed | 12 2 2 Bits Offset Error @ 25°C 22 22 2 LSB max Trae 0 Toe = = = LSB max | Typical Change over Temp is =1 LSB Fill Seale (PS) Eero? @ 25°C 38 28 28 LsBmx | PS= SV Full Sale TO-* “ 3 6 pmC max | Ideal Last Code Transition ~ FS 3/2 LSBs ‘ANALOG INPUT Tnpor Volage Range ow+s [ors | or+s | Votes For Bipolar Operation See Figures 10 Input Current 35 Bs 35 mA max and 12 INTERNAL REFERENCE VOLTAGE Vgar Output @ 25°C -sa-sa | -sa-sa | sas | Vemma | 5.25 v=1% Van Output TC * 2 * pmrC typ | External Load Should Not Output Curren Sink Capability 580 550 380 BA max (Change During Conversion POWER SUPPLY REJECTION Voo Only a +2 212 LSB 9p PS Change, Vag = —12 Vor ~15 V Von © 45 V 1055 V Vs Only 22 =n LSB op FS Change, Von = SV Vgg = ~H14 Vio -16.5 V Looe nrots @S, RD, HBEN, CLK IN Vous Input Low Voltage +08 +08 408 V max Vop = 5 =5% Vt Hopat High Voleage a4 324 424 V min Cis lit Capaciance™ 0 10 10 pF max 5, RD, HBEN Tr Input Current 210 =10 =10 HA max = OV 0V op LEN Ty Input Current 20 =2 220 BA max Vin = OV 10 Vp TOsIc OUTPUTS, Dil-Dos, BUSY, CLK OUT Vous Output Low Valiage +04 +04 +04 Vmax Tyg = 16 mA, Vow Output High Voltage 40 +40 +40 V min Teoence ~ 200 nA Dubos Floating Sate Lesage Current | =10 =10 =10 HA max Floating State Output Capacitance’ | 15 5 18 PF max ‘CONVERSION TIME ‘ADIST2AXX03 Synchronous Clock 3.28 ans 25 sax foun = 4 MHz. See Under ‘Asynchronous Clock 3325 3325 33.25 ts minvus max | Control pus Synchronization ADIST2AXX10 Syachronous Clock 10 0 e ys max feu = 1.25 MB: [Asynchronous Clock senos | sen04 | - os mis max POWER REQUIREMENTS Yoo 4s +5 s V nom 15% for Specified Performance Ven Fie 15 | “12te-18 | “1210-18 | V nom AL V to ~165 V for Specified Performance Toe? fl 7 7 mA max GS = RD = Voo, AIN = 5V he 10 0 2 mA max GS = RD = Vop, AIN = 5V Power Dissipation 100 100 Lo mW yp “2v assias | assis | 1791s | mW max Vg = -RW-15V ores "Tempertue ange area follows: J, L Versione, 010 +70'C; A Version, -0°C 1 +88; § igen internal Vola Feference er 2FullSele TC = AFSIAT where AFS i Full-Scale change from T= +25°C 10 Ty OTe nels internal voltage rfereace dit. Semple texted To ensure compliance. “Power supply corent is measured when the ADTST2A is inactive, i, Speciation subject wo change without noice RD - BUSY HIGH. REV.AAD7572A TIMING CHARACTERISTICS’ v. V = 5%, Vos = 114 Vt0 -165 V0 Limit at 425°C | Limit t Pains Toon | Limit at Tyas Ta Parameter | (All Grades) | (J, L, A Grades)” | (S Grade) Units | Conditions/Comments 5 0 0 0 ns min | CS to RD Sewup Time u 190 230 270 1s max | RD to BUSY Propagation Delay e %0 ito 120 ns max } Data Access Time after RD, C, ~20 pF 135, 130 170 ins max | Data Access Time after RD, C,~100 pF & 5 s 8 rs min | RD Pulse Width & ° ° Q 1nsmin | CS to RD Hold Time we 70 0 100 ns max | Data Setup Time after BUSY w 15 15 Is rns min | Bus Relinguish Time 5 85 90 ns max % ° ° o tas min | HBEN to RD Sctup Time % 0 ° 0 1s min | HBEN to RD Hold Time a 200 200 200 rsmin | Delay Between Successive Read Operations NoTE "Timing Spsiations ate sample tested at +28°C to ensure compliance. All input contol sguls ae spied with © ef = Sms (10% wo WH of +5 V) and tamed fom a ylage evel of 16 V “rand fare measured wth the load ccuits of Figure land define asthe ime require for an output eros 8 V or 2.4. Cir defined a he time regired forthe data ines to change 0.8 V when iaded withthe circuit of Fig 2. Specifications subject o change withour sie 7 ABSOLUTE MAXIMUM RATINGS* en oe Vpp © DGND 0.3V0+7V ast a o Vss to DGND- +03Vto “17 V t gf, XGND 0 DaN “Oa VVgo #038 PGND pono AIN to AGND -15 Vito +18 V Digi inp Vstag i BOND # Hoh 2 0 Vout) |B MihZt0 Vest) TR I HENS RD, C3)... -03 Vs Vp 1030 fo to ou Voit) gtk ouput Vluge to DEND Figure 1 Load Grout for Access Time DILDO CLK OUT, BUSY)... -03¥5 Yop 03 ¥ pening Tepe Ringe Comme Gr venta) bv “1 Indu (Vers Lise “ase v Extended (S Version) . SSC to + 125°C a sions Tempe “Sete s0e 7 = Ln ampere ng 8 “one Power Ditton ny Faas) e275 1000 aka _— sage Derates above +75°C by 10 mW woo U Se 8 Von t0 HighZ Voto High zen eons mE Figure 2 Lod Creuts for Output Feat Delay =n cauriow: END lettoais Unhage soutie doe The dig save gpa ae doke pomce SLOTTED however, permanent damage may occur on unconnected devices subjected to high energy elec: twostatic fields. Unused devices must be stored in conductive foam or shunts. The foam should be discharged to the destination socket before devices are removed. REV.AAD7572A Model AD7S72ATNOB AD7S72AANO3 3s Bus AD7572ASQ03" | 3 us ‘AD7S72ALNO3 ‘AD7S72AAQ03 AD7572A]R03 ADTS72AAR03 AD7S72ATNIO ADTS72AAN10 ADTS72ALN1O Bus Bus Bus Bus 10 ps 10 ps 10 us ADIS72AJRIO_| 10 us Notes 'N = Pie DIP; Q ~ Cendip; R = Small Outline IC (SOIC) Conversion | Temperature ORDERING GUIDE PIN CONFIGURATION Range OC +70 | a cua ne | sei tae) oa oe ee | sme | S12 LsB og Mewes | SypmG | “1 ESB senna oewnwe | eer | Sie oC] sw Bereta e |eare| irc oe GE] SED Fay caer OC to +70°C. 45 ppmi"C | +1 LSB ee 7 40°C to +85°C | 45 ppm°C | =1 LSB mi wcw +0C | 28ppm"C | 212 LSB 0 oeto 70C | sSpomec | +1 9B ~oq [zon /ADTS72ASQ03 willbe avaible to 8638 processing oly. Conse your lal ales fie for reese PIN FUNCTION DESCRIPTION Pin No. Mnemonic __Description 1 AIN ‘Analog Input. 2 Vesr ‘Voltage Reference Output. The AD7S72A has its own internal ~5.25 V reference 3 AGND Analog Ground, 4...11 DIL... Dé Three State Data Outputs. They become active when CS and RD are brought low. 13...16 BLL... DOB Individual pin function is dependent upon High Byte Enable (HBEN) Input. DATA BUS OUTPUT, GS & RD = LOW Pin ¢ [Pin 5] Pin 6] Pin 7] Pin 8 [Pin 9] Pin 10] in 11] Pin 13] Pin 14] Pin 15] Pn 16 mnemonic: [pi [p10 [po [ps [p7 [ps [ps |p» p2io [pis [pom HBEN ~ Low [pB1i| DB10] DB» [Dae | DB? [Das [DBs De [DBs [DB? [DBI | DBO HBEN = HIGH] DB11|DB10] DB9 [pas [tow] Low] Low [Low [pan [B10 [Day | DBE NOTES SDIL DO ae the ADC dats ouput pis DBL | DBO ar the 1: convene resus, DBIL i tbe MSB R DGND Digital Ground v CLK IN Clock Input Pin. An excernal TTL compatible clock may be applied to this pin Alternatively 4 crystal or ceramic resonator may be connected between CLK IN (Pin 17) and CLK OUT (Pin 18), 18 CLK OUT Clock Ourput Pin, An inverted CLK IN signal appears at CLK OUT when an external clock is used. See CLK IN (Pin 17) description for crystal (resonator). 9 BEN High Byte Enable Input. Its primary function is to multiplex the 12 bits of conversion data onto the lower D7... DOVB outputs (4 MSBs or 8 LSBs). See Pin Description 4... 11 and 13... 16, Ie also disables conversion stat when HBEN is high 20 RD READ Input. This active LOW signal, in conjunction with CS, is used to enable the ourput data three-state drivers and initiate a conversion if CS and HBEN are low. 21 GS CHIP SELECT Input. This active LOW signal, in conjunction with RD is used to enable the ‘output data three-state drivers and initiate a conversion if RD and HBEN are low. 2 BUSY BUSY Output indicates converter status. BUSY is LOW during conversion 2B Ves Negative Supply, ~12 V 0-15 V. a Yoo Positive Supplv, +$ V. REV. AAD7572A OPERATIONAL DIAGRAM ‘An operational diagram for the AD7S72A is shown in Figure 3. ‘The AD7572A is a 12-bit successive approximation A/D con= verter, The addition of just a erystalceramic resonator and a few capacitors enables the device to perform the analog-to-digital function, ‘ ee cc wrosraays — Figure 3. AD7572A Operational Diagram CONVERTER DETAILS Conversion statis controlled by the CS, RD and HBEN inputs. At the start of conversion the successive approximation register (GAR) is reset and the three-state data ourputs are enabled, (Once a conversion cycle has begun it cannot be restarted. During conversion, the internal 12-bit voltage mode DAC out pt is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB), Referring to Figure 4, the AIN input connects to the comparator input via 2.5 k0 Figure 4. AD7572A AIN input ‘The DAC which has a similar 2.§ k® output impedance con rect to the same comparator input, Bit decisions are made by the comparator (zero crassing detector) which checks the addi- tion of each successive weighted bit from the DAC output. The MSB decision is made 80 ns (typically) after the second falling edge of CLK IN following a conversion start. Similarly, the suc- ‘ceeding bit decisions are made approximately 80 ns after a CLK REV.A IN edge until conversion is finished. At che end of conversion, ‘the DAC output current balances the AIN input current. The SAR contents (12-bit data word) which represent the AIN input signal is loaded into a 12-bit latch. = Sl Seen exo EQ ! { t Figure 5. Operating Waveforms Using an External Clock Source for CLK IN| CONTROL INPUTS SYNCHRONIZATION In applications where the RD control input is not synchronized with the ADC clock then conversion time can vary from 12 t0 13 CLK IN periods. This is because the ADC waits forthe first falling CLK IN edge after conversion start before the conversion procedure begins. Without synchronization, this delay ean vary from zero to an entire clock period. If a constant conversion time is required, then the following approach ensures a fixed 3.125 js conversion time for the ADTS72AXX03 and 10 us for the AD7S72AXX10: when initiating a conversion, RD must go low on either the rising edge of CLK IN or the falling edge of CLK OUT, DRIVING THE ANALOG INPUT During conversion, the AIN input current is modulated by the DAC output current at a rate equal to the CLK IN frequency Gi.e., 4 MHz when CLK IN = 4 MHz). The analog input volt- ‘age must remain fixed during this period and as a result must be driven from an op amp or sample-and-hold with a low output ‘impedance. The output impedance of an op amp is equal to the ‘open loop output impedance divided by the loop gain atthe fre quency of interest Suitable devices capable of driving the AD7S72A AIN input are the AD84S op amp or the ADS8S sample-and-hol. INTERNAL CLOCK OSCILLATOR Figure 6 shows the AD7572A internal clock circuit. A erystal or ceramic resonator may be connected between CLK IN (Pin 17) and CLK OUT (Pin 18) to provide a clock oscillator for the ADC timing. Alternatively the crystalitesonator may be omitted and an external clock source may be connected t0 CLK IN. For an external clock the markispace ratio can vary from 45/55 to 55/45, An inverted CLK IN signal will appear at the CLK OUT pin as shown in the operating waveforms of Figure 5. Figure 6. AD7572A Internal Clock CircuitAD7572A INTERNAL REFERENCE The AD7S72A has an on-chip, buffered, temperature compensated, buried Zener reference, which is factory erimmed to ~5.25 V 1%, It is internally connected to the DAC and is also available at Pin 2 to provide up t0 550 wA current to an external load For minimum code transition noise the reference output should ‘be decoupled with a capacitor to filter out wideband noise from the reference diode (10 ,F of tantalum in parallel with 100 nF ceramic}. Some applications will use the AD7S72A as an upgrade replacement for the AD7572, The recommended refer- ence decoupling for the AD7S72 differs from the ADTS72A in that it contains an additional 10 0 resistor in series with the capacitors. This resistor makes no difference to the performance of the 10 s version of the AD7S72A, but it does adversely affect the linearity performance of the 3 us version. So, applic: tions using the AD7S72A as a 3 us upgrade of the AD7572 ‘must replace the 10 0 reference resistor with a wire link. Figure 7. AD7S72A Internal ~5.25 V Reference UNIPOLAR OPERATION Figure 8 shows the ideal inpuvoutput characteristic for the 0 t0 5 volt input range of the AD7S72A. The designed code transi- tions occur midway between successive integer LSB values (.e., V2 LSB, 3/2 LSBs, 5/2 LSBs . . . FS-3/2 LSBs). The output code is natural binary with 1 LSB = FS/4096 ~ (5/4096) V Tam oss ss ' ' / * isnusesises Hee Figure 8. AD7572A Ideal InpuvOutput Transfer Characteristic UNIPOLAR OFFSET AND FULL-SCALE ERROR ADJUSTMENT In applications where absolute accuracy i important then offset, and full-scale error can be adjusted to zero. Offset error must be adjusted before full-scale error. Figure 9 shows the extra compo: nents required for full-scale error adjustment. Zero offset is achieved by adjusting the offset of the op amp driving AIN Ge, AL in Figure 9.). For 2eo offset error apply 0.61 mV (.e., 1/2 LSB) at Viy and adjust the op-amp offset voltage until the ADC ouput code fickers between 0000 0000 0000 and (0000 0000 0001 FFor zero full-scale error apply an analog input of 4.99817 V Ge., FS-3/2 LSBs or last code transition) at Vy and adjust R1 ‘until the ADC output code flickers between 1NTT 1111 1110 and, MATE Figure 9. Unipolar 0 to +5 V Operation with Gain Error Adjust BIPOLAR OPERATION Figures 10 and 12 show how bipolar operation can be achieved with the AD7S72A. Both circuits use an op amp to offset the analog signal (Vis) by 2.5 V. Alternatively, the op amp (AL) can be replaced by a sample hold as shown in Figure 24. The op amp transfer functions are given below: Figure 10: AIN = (Vjy + 2.5) volts Figure 12: AIN = (-V,y + 2.5) volts Both circuits have an analog input range of =2.5 V and an LSB size of 1.22 mV. The output codes are offset binary for Figure 10 and complementary offset binary for Figure 12. Their ideal inpuvioutput transfer characteristics after offset and full-scale adjustment are shown in Figures 11 and 13, Signal ranges other than =2.5 V are easily accommodated using different values of R3 and R4 for Figure 10, and a different R2 value for Figure 12. These resistors should be chosen such that the voltage range at AIN covers the full dynamic range (i. OV to $V) of the ADC. All resistors should be the same type and from the same manufacturer so that their temperature coef ficients match. Figure 10. AD7572A Bipolar Operation - Output Code is Offset Binary + REV.AADT572A Figure 11. Ideal InpuvOutput Transfer Characteristic for the Bipolar Circuit of Figure 10 Figure 12. AD7572A Bipolar Operation - Output Code is Complememary Offset Binary Figure 13. Ideal Input/Output Transfer Characteristic for the Bipolar Circuit of Figure 12 REV. A OFFSET AND FULL-SCALE ERROR In most Digital Signal Processing (DSP) applications offset and full-scale error have little oF no effect on system performance. A typical example isa digital ler, where an analog signal is quan- tized, digitally processed and recreated using a DAC. In these types of applications the offset error can be eliminated by ac coupling the recreated signal. Fullscale error effect is linear and does not cause problems as long as the input signal is within the full dynamic range of the ADC. An important parameter in DSP applications is Differential Nonlinearity and ths is not affected by ether offset or full-scale error. In measurement applications where absolute accuracy is required, offset and full-scale error can be adjusted to zero as in Figure 14. Figure 14. AD7572A Bipolar Operation with Offset and Gain Error Adjust BIPOLAR OFFSET AND FULL-SCALE ERROR ADJUSTMENT The bipolar circuit of Figure 10 can be adjusted for offset and full-scale errors, by including two potentiometers RS and R6, as shown in Figure 14, Offset must be adjusted before full-scale error. This is achieved by applying an analog input of 0.61 mV (12 LSB) at Vi and adjusting RS until the ADC output code flickers between 1000 0000 0000 and 1000 0000 0001 For full-scale error adjustment, the analog input must be at 2.49817 volts (4e., FS/2 -3/2 LSBs of lst transition point ‘Then R6 is adjusted until the ADC output code flickers between HU MH 1110 and 1111 101 111. A similar offset and full-scale error adjustment procedure may be employed for Figure 12 by making Rl and R2 variable. Off set must again be adjusted before full scale error. This is achieved by applying an analog input of 0.61 mV at Vig and adjusting RI until the ADC output code flickers berween OWL 1111 1110 and 0141 HLH LIL For full-scale error adjustment, apply a signal source of 2.49817 V at Vi and adjust R2 until the ADC output code ‘ickers bewween 0000 0000 0000 and 0000 0000 0001.ADTS72A APPLICATION HINTS Wire wrap boards are not recommended for high resolution ot high speed A/D converters. To obtain the best performance from the AD7S72A a printed circuit board is required. Layout for the printed circuit board should ensure that digital and ana- Jog signal lines are separated as much as possible. In particular, care should be taken not to run any digital crack alongside an analog signal track or underneath the ADS72A. The analog Input should be screened by AGND. AA single point analog ground (STAR ground) separate from the logic system ground should be established at Pin 3 (AGND) ot 35 close as possible to the AD7S72A as shown in Figure 15. Pin 12 (AD7S72A DGND) and all other analog grounds should be connected to this single analog ground point. No other digital grounds should be connected to this analog ground point. Low ‘impedance analog and digital power supply common returns are essential to low noise operation of the ADC and the fil width for these tracks should be as wide as possible, Noise: Input signal leads to AIN and signal return leads fom AGND (Pin 3) should be kept as short as possible to minimize ‘input noise coupling. In applications where this is not possible, a shielded cable between the signal source and the ADC is ree- ommended. Also, since any potential difference in grounds between the signal souree and ADC appears as an error voltage in series with the inpat signal, attention should be paid to reducing the ground circuit impedances as much as possible. In applications where the AD7S72A data outputs and control signals are connected to a continuously active microprocessor ‘bus, it is possible to get LSB errors in conversion results. These crtors are due to feedthrough from the microprocessor 10 the successive approximation comparator. The problem can be elim- inated by forcing the microprocessor into a WAIT state during conversion (see Slow Memory Mode interfacing), or by using ‘theee-state buffers to isolate the ADTS72A data bus. Figure 15. Power Supply Grounding Practice IMING AND CONTROL Conversion start and data read operations are controlled by three AD7S72A digital inputs; HBEN, CS and RD. Figure 16 shows the logic structure associated with these inputs. The three sig nals are internally gated so that a logic “0” is required on all three inputs to initiate a conversion. Once initiated it cannot be restarted until conversion is complete. Converter status is indi cated by the BUSY output, and this is low while conversion is in progress. Fis Figure 16. Internal Logic for Control Inputs CS, RD HBEN ‘There are two modes of operation as outlined by the timing dia trams of Figures 17 to 20, Slow Memory Mode is designed for ‘microprocessors which can be driven into a WAIT state, a READ operation brings CS and RD low which initiates acon. version and data is read when conversion is complete. The seo cond is the ROM Mode which does not require microprocessor WAIT states, » READ operation brings CS and RD low which initiates a conversion and reads the previous conversion result. DATA FORMAT ‘The output data format can either be a complete parallel load (DBI. . . DBO) for 16-bit microprocessors or z two byte load for §-bit microprocessors. Data is always right justified (ie., LSB is the most right-hand bit in a 16-bit word). For a two byte read, only data outputs D7 . . . DOS are used. Byte selection is governed by the HBEN input which eontrols an internal digital, ‘multiplexer. This multiplexes the 12-bit of conversion data onto the lower D7. . . DO/B outputs (4 MSBs or § LSBs) where it ‘can be read in two read cycles. The 4 MSBs always appear on DIL... D8 whenever the three-state output drivers are turned SLOW MEMORY MODE, PARALLEL READ (HBEN Low) FFigure 17 and Table I show the timing diagram and data bus status for Slow Memory Mode, Parallel Read. CS and RD going. low triggers a conversion and the AD7S72A acknowledges by taking BUSY low. Data from the previous conversion appears ‘on the three state data outputs. BUSY returns high atthe end of conversion when the output latches have been updated and the conversion result is placed on data outputs D1I . . . DOV. SLOW MEMORY MODE, TWO BYTE READ For a two byte read only 8 data outputs D7... . DOVS are used. Conversion start procedure and data output status for the first read operation is identical to Slow Memory Mode, Parle! Read, See Figure 18 timing diagram and Table IT data bus st tus, Ar the end of conversion the low data byte (DB7 . . . DBO) is read from the ADC. A second READ operation, with HBEN high, places the high byte on data outputs D311 .. . DOS and disables conversion stat, Note the 4MSBs appear on data out- puts DIT... D8 during the two READ operations above. | eV. |AD7572A ‘>| L. = Figure 17. Slow Memory Mode, Parallel Read Timing Diagram Table | Slow Memory Mode, Parallel Read Data Bus Status 'ADIS72A Data Outputs [Dli_| DIO [D9 [Ds | D7 [Dé [DS [D4 | D3ni | D210 | DLs | Dow Read pit | ppi0 | ps9 | pps | ps7 | pgs | pss [Bs | pes [paz | pBi | Dao ol aE AF a je ape ah “Xf FE {J \ ft | Jk Se ele he Figure 18. Slow Memory Mode, Two Byte Read Timing Diagram Table Il, Slow Memory Mode, Two Byte Read Data Bus Status ‘ADTS72A Data Outputs [D7 [D6 [Ds [D4 [Dam | Dano [Dis [Dow First Read pg7_|pas | pps [pss [pps | sz [pei | pBo Second Read! tow [tow | ow | row [psn | vaio [ pp9 [DBs ROM MODE, PARALLEL READ (HBEN = LOW) ‘The ROM Mode avoids placing a microprocessor into a wait state. A conversion is started with a READ operation, and the |2-bits of data from the previous conversion are available on data outputs DI1 . . . DO (see Figure 19 and Table III). This, data may be disregarded if not required. A second READ opera: tion reads the new data (DBI! . . . DBO) and stars another conversion. A delay atleast as long as the AD7S72A conversion time must be allowed between READ operations. ROM MODE, TWO BYTE READ AAs previously mentioned for a two byte read, only data outputs D7... . DOVS ate used. Conversion is started inthe normal way REV. A ‘with a READ operation and the data output stats isthe same as the ROM Mode, Parallel Read. See Figure 20 timing dia- ‘gram and Table IV data bus status. Two more READ opera- tions are required to access the new conversion result. A delay ‘equal to the AD7S72A conversion time must be allowed be tween conversion start and the second data READ operation. ‘The second READ operation, with HBEN high, disables con- version start and places the high byte (4 MSBs) on data outputs 3/11... DOVB. A third READ operation accesses the low data byte (DB7 . . . DBO) and starts another conversion. The 4MSBs appear on data outputs DIJ . . . D8 during all three read opera tions aboveADTS72A abe = Figure 19. ROM Mode, Parallel Read Timing Diagram Table ll ROM Mode, Parallel Read Data Bus Status ‘AD7S72A Data Outputs [DU | DIO [D9 [Ds [D7 [bs [Ds [bs | psa | D210 | Dis [Dow First Read (Old Data) | DBI | DBIO | DBe | Das | DB? | DB6 | Das | DBs | DBs | DB2 | DB _| DBO ‘Second Read pu | peio | pgs | pas | ps7 [ pB6 | pas [pss [pes [Dez | ppl | bBo Figure 20. ROM Mode, Two Byte Read Timing Diagram Table IV. ROM Mode, Two Byte Read Data Bus Status ‘AD7S72A Data Outputs [D7_ [D6 [Ds [D4 [ami | p20 | Dus [Dow First Read (Old Data) | DB7_[DB6 [Das [B+ [DBs |B? [Dei | DBO ‘Second Read tow [Low | Low [Low [pari | pBi0 | Dao | DBE Third Read Da? _| DBs | DBS [DBs [DBs | DR? | DBI [DBO MICROPROCESSOR INTERFACING The AD7S72A is designed to interface with microprocessors as a memory mapped device. The CS and RD control inputs are ‘common to all peripheral memory interfacing. he HBEN input serves as a data byte select for &-bit processors and is normally connected to the microprocessor address bus. _MC68000 Microprocessor Figure 21 shows a typical interface forthe 68000. The ADTS72A is operating in the Slow Memory Mode. Assuming -10- the AD7572A is located at address C000, then the following sin- ale 16-bit MOVE instruction both stats a conversion and reads the conversion result. Move,W $C000,D0 [At the beginning of the instruction cycle when the ADC address is selected, BUSY and CS assert DTACK, so that the 68000 is forced into a WAIT state. At the end of conversion BUSY returns high and the conversion result is placed in the DO regis ter of the uP. REV. AAD7572A i — csa000 ! Figure 21. AD7572A-MC68000 Interface 8085A, 280 MICROPROCESSOR Figure 22 shows an AD7S72A interface for the 280 and 8085A. The AD7572A is operating in the Slow Memory Mode and a two byte read is required. Not shown in the figure is the 8-bit latch required to demultiplex the 8085A. common address/data bbus. AO is used to assert HBEN, so that an even address (HBEN = LOW) to the AD7572A will start a conversion and read the low data byte. An odd address (HBEN ~ HIGH) will read the high data byte. This is accomplished with the single 16-bit LOAD instruction below. For the 80854 LHLD (B000) For the 280 LD HL, (B000) This is a wo byte read instruction which loads the ADC data (address BO00) into the HL register pair. During the first read operation, BUSY forces the microprocessor to WAIT for the AD7S72A conversion, No WAIT states ae inserted during the second read operation when the microprocessor is reading the high data byte ADIs72A* Figure 22, AD7572A-8085/280 Interface REV.A ne ‘TMS32010 MICROCOMPUTER Figure 23 shows an AD7S72A-TMS32010 interface, The AD7S72A is operating in the ROM Mode. The interface is designed for a maximum TMS32010 clock frequency of 18 MHz ‘but will typically work over the full TMS32010 clock frequency range. ‘The AD7S72A is mapped at a port address. The following VO instruction starts a conversion and reads the previous conversion. result into data memory. IN APA (PA = PORT ADDRESS) ‘When conversion is complete, a second /O instruction reads the up-to-date data into data memory and starts another conversion, [A delay atleast as long as the ADC conversion time must be allowed between 1/0 instructions. v am) Figure 23, AD7572A-TMS32010 Interface ‘AD1S72A-ADS85 SAMPLE-HOLD INTERFACE Figure 24 shows an ADS8S sample-hold amplifier driving the AAIN input of the AD7572A. The interface contains resistors Rl, R2, R3 and Ré ro allow a bipolar input signal range of =2.5 volts. The maximum sampling frequency is 166 kHz for the AD7S72AXX03 (3 ys conversion) and 77 kHz for the AD7572AXX10 (10 js conversion). This includes the sample- hold amplifier acquisition time (3 ys). Figure 24, AD7572A-AD585 Sample-and-Hold Interface‘AD7572A When an AD7572A conversion is initiated, the converter BUSY ‘output goes low indicating conversion isin progress. The falling ‘edge of this BUSY output signal places the sample-hold ampli- fier into the HOLD mode “freezing” the input signal to the AD7S72A. When conversion is finished, the BUSY output returns HIGH allowing the sample-hold to track the input nal. To achieve the maximum sampling rate, the AD7S72A out- ‘put data must be read within 3 ys immediately after conversion ‘while the sample-hold amplifier is acquiring the next sample. OUTLINE DIMENSIONS Dimensions shown in inches and (axa) 24-Pin Plastic DIP (N-24) 24-Pin Cerdip (Q-24) ae ee, s+ ee 24-Pin Plastic SOIC (R-24) ee REV. A cra04-10-1081 PRINTED IN US.A