1 VLSI Rabaey Lecture Videos Contents

2 1.EE141 - 1/20/2012 - Introduction to the course and Evolution of Computers

3 2.EE141 - 1/25/2012 - Fabrication, Yield, Design Metrices - Cost and Reliability(Noise
and Sources of Noise), Introduction to some terms related to VTC
4 3.EE141 - 1/27/2012 - Regenerative property,Design Metrices- Performance (Delay
Definitions and first order transient analysis) and Power,Eneregy and Power Delay
Product,Transistor Layout and Design Rules
5 4.EE141 - 2/1/2012 - Switch model of MOS and CMOS inverter ,CMOS inverter (first order
DC analysis),Symmetrical VTC,CMOS inverter transient response,Sizing of Inverter
Chain*(Performance)
6 5.EE141 - 2/3/2012 - Inverter Chain Sizing Continued and its impact on energy and area
,nmos(strong 0) and pmos(strong 1), CMOS logic
7 6.EE141 - 2/8/2012 - Sizing in complex logic,Delay(Sizing) of NAND and NOR,Why is NAND
faster than NOR in CMOS logic(logical effort),Logical Efforts of various gates,How to
decide which circuit is better for performance(Load small then intrinsic delay
factor(p) dominates and Large Load Logical Effort is deciding factor)
8 7.EE141 - 2/10/2012 - Branching Effort Examples,Wires, Varying (increasing)Thickness of
Wires as we go up the layers, Wire Models, Parallel plate capacitor model, Fringing
Capacitance, Capacitative coupling and noise, Resistance Of wires
9 8.EE141 - 2/15/2012 - Silicides reduces resistance,lumped model, Resistance of
transistor is of order 10^3ohm, Distributed RC model(Delay is only half of that
predicted by lumped RC model ), Elmore Delay ,Diffusion of step signal through
distributed rc leads to less steeper exponentials as we move towards
destination,Insertion of Repeaters in RC n/w,Decoders and optimization
10 9.EE141 - 2/22/2012 - Memory Decoder (continued), Predecoders, Physics of MOS,Threshold
Voltage,Body Effect, Linear and Saturation Region, Pinch Off,Drain Current
Equations,Channel Length Modulation, Velocity Saturation, Short Channel device
saturates early,Unified Model,Approximating Resistance of Transistor
11 10.EE141 - 2/24/2012 - DIBL,MOS capacitances, Overlap capacitances,Channel Capacitance
in different regions of operation,Diffusion(Junction) Capacitance, Channel Stop
Implant,Linearizing the junction capacitance, Derivation of VTC of CMOS inverter
12 11.EE141 - 2/29/2012 - For Vm=VDD/2 Rn=Rp,Strong nmos means wider nmos(or Rn is
low),Linear approximation of VTC, VTC for varying VDD, Inverter characterstics below
threshold(subthreshold),VDD>50mv for inverter characterstics, MID Term Solutions,
Discussion of Project
13 12.EE141 - 3/2/2012 - Discussion of project(continued), Ripple Carry Adder(Tdelay is
O(N)),Direct Implementation(28 transistors),Mirror Adder(Improve the logical effort of
A and B inputs), Sizing the mirror adder, Keep the critical inputs near the
output,Carry Bypass(Carry skip) Adder(O(N) but Td proportional to N/4), Carry Select
Adder(O(N)), Increase Block bit length to make square root carry select(O(sqrt(N))),
Rearrange the block bit length (increase then decrease) to get a faster carry bypass
adder
14 13.EE141 - 3/7/2012 - Carry Look Ahead adders, Logarithmic (Tree) Adders(Best adder
available O(log2N)),Brent Kung Tree(Disadv - Large Fanout),Kogge Stone (Disadv - Large
area , Adv- Fastest adder),Binary redundance representation,Relational operators
implementation,Multipliers, Array Multiplier,Carry Save Multiplier,Wallace Tree
Multiplier(log1.5N),Booth Multiplier
15 14.EE141 - 3/9/2012 - Memories, Static Memory(Data bit stored as voltage), Dynamic
Memory (Data bit stores as charge), Memory Classification, 2 stable and 1 meta stable
states in two inverter SRAM cell,Writing into cross -coupled pair inverter (overpower
the feedback),Ratioed Logic, Always write "0"(get ratio b/w access transistor((nmos)
and pmos,make nmos(access) strong than pmos), From read (get ratio b/w access
transistor(nmos) and nmos,make acess transistor(nmos) weak than nmos ), Read static
noise margin
16 15.EE141 - 3/14/2012 - SRAM ( 6-T Contd), Resistive Pull up SRAM, DRAM, 3-T DRAM cell(
needs to be refreshed, inverted value is read,dedicated bit line for read and write(due
to leakage but read is non destrcutive), 1-T DRAM cell(Destructive read thus sense
amplifier read and restore data), CMOS switching delay, Approximating the non linear
resistance of transistor([Link] Source(IdSAT),2. Current Source including some
finite resistance [Link] Approximation [Link] 2 Find Req), Resistance variation
with Vdd, Capacitances(Contribution of various capacitances in load capacitance)
17 16.EE141 - 3/16/2012 - Power Dissipation in CMOS(1. Switching Power(Dynamic
Power)(capacitor charge) 2. Leakage(subthreshold, Reverse Leakage Current) [Link]
Circuit Power [Link] Power), Capacitance values are different in power analysis from
delay analysis (as we go from 0->Vdd rather than 0->Vdd/2),Make input rise time
equivalent to output fall time to minimise short ckt current, To reduce subthreshold
current try to reduce the slope below Vth(80-90 mv reduction in voltage for decade
reduction in current), Threshold variation with Vds(DIBL) and Length L, Design
Techniques for performance -[Link] in Considerations in Delay(Tapered Sizing),Gates with
 fan in greater than 4 must be avoided(performance), Delay increases linearly with Fan
Out but quadratically with Fan In, 2. Transistor reordering (Keep critical inputs
closer to output),3. Alternate ckt implementation,[Link] Fan in and Fan out,5.
Reduce Voltage Swing
18 17.EE141 - 3/21/2012 - Moving to Ratioed Logic (Performance),Trade off is Power,prefer
NOR gates in nmos PDN ratioed logic(reason-NAND series nmos),For Calculating LE find
the active paths to VDD/Ground from output then take RgCg/RinvCinv,Conflicting Currents
take Reff=1/(1/Rn-1/Rp),Improved loads - 1. Adaptive loads( In PUN Two transistors ,
one with large W and one with small W . While transistion use larger W),[Link]
Cascode Switch Voltage Logic (DCSVL)(Not ratioed anymore and no static power
dissipation), Pass Transistor Logic,NMOS only logic and Level Restorer(Adv- Full Swing
and no static power dissipation in inverter disadv-ratioed logic between pass
transistorand Level restorer pmos),Complementary PTL(Instead of using level restorer
use differential output ), Transmission gates(added pmos thus slower), Transmission
gate multiplexers and XOR gates, Dynamic Logic (Adv over ratioed logic full swing , non
ratioed, no static power more dynamic power (more transistion and more clk
distrbution),faster than CMOS)
19 18.EE141 - 4/4/2012 - Mid term 2, Dynamic Logic( Faster than CMOS and also
non-ratioed,no static dissipation),NOR gates are better in dynamic logic style than
NAND gates,Dynamic inverter has very small Noise Margin, Challenges in Dynamic Logic -
[Link] leakage(rev biased diode) (Solution - [Link] at high freq and dont give
time to discharge 2. Bleeder or Level restorer(inverter feedback)) [Link] Sharing
20 19.EE141 - 4/6/2012 - [Link] Sharing( Solution - [Link] [Link] charge intermediate
nodes (bleeder)),[Link] Feedthrough (Bootstrapping)(Diode p-n in pmos might become FB
and might lead to Latch Up) (Solution is having substrate contects to provide currents
to go to ground or Vdd),[Link] Coupling , Cascading of Dynamic Inverters must be
done through Domino Logic(only 1->1 or 1->0 transistion allowed before second dynamic
invereter) (soln. 1(Domino logic)add static inverter in b/w also add level restorer, 2.
Delayed Clocks), Dynamic logic is non-inverting, NOR gates better than NAND in
Dynamic(Domino) Logic ,Assymetrical VTC(for the static inverter just after the dynamic
gate) to reduce tpLH makes it faster(reduce logical effort),can eliminate evaluate
transistors(except first stage) in Domino logic
21 20.EE141 - 4/11/2012 - CMOS layout, Euler Paths for efficient layout(continuous
diffusion stripes for both pmos and nmos),, Multifingered Transistors, Sequential
Logic, Latches vs Flip Flops,Set up and Hold Times,Writing into static latch(using MUX)
22 21.EE141 - 4/13/2012 - Recap,Latch doesn't solve race problem in sequential ckts(except
if duty cycle of clock < tp),master slave latch(is also a edge triggered register) to
solve race problem(assuming Ideal clk and ~clk),Latch based design,Set up and Hold
Time, Set up and Hold Up relation with tcq(5 %),C^2MOS(Master Slave) ( NORA -No
race),True Single phase clock (TSPC)(Also Master - slave, connect positive and negative
latch in series), Including Logic in TSPC(AND-LATCH(Tclk1>tp+Ts1) is slower than TSPC
embedded AND Latch(Tclk2>Ts1+del and del<tp)),Edge triggered latches (creating
pulses),setup and hold time inequalities,Clock skew
23 22.EE141 - 4/18/2012 - Clock skew(at two different places),its effect on
inequalities,Clock jitter(at the same place) and its effect on inequalities,Jitter has
Gaussian Distribution,Sources of clock uncertainity,Clk distribution should be such
that it should reach different points of ckts at same time,Latch based clocking,Time
borrowing in latches,Flip flop or Register(adv is no race conditiob but disadv is not
lenient with clock shortcomings(Hard edges)), Latch(adv is leniency with clock
shortcomings,Time Borrowing but disadv is race condition), Clock distribution(H-Tree),
clock grid(done locally only as consumes huge power)
24 23.EE141 - 4/20/2012 - Clocks and Power,What matters is to minimise clock skew and not
clock delay,PLL is used to multiply the frequency of crystal clock,Various clocking
systems development,Power Distribution,inverter is not a good power supply noise
rejection device,Multiple pins for power distribution,layers for vdd and
ground,Electromigration( soln -Limit the current per unit length)(electrons push the
ions and thus they move to different positions and can cause short or open ckts),Add
decoupling capacitance(Gate capacitance is used) to avoid sudden drop in v of supply
rails,Rc n/w do not produce ringing oscillations,Real Power distribution analogy is now
coming to new generations chips,switches in power line, when a block is not in use turn
off clock as well as power supply,Technology scaling,Full scaling(constant EF),Fixed
voltage and general scaling
25 24.EE141 - 4/25/2012 - Scaling , Vertical channel wrapped with gate provides more
control over channel(FINFET Or Trigate),Carbon Nano Tubes (Cylindrical covering of
channel with gate),Wire Scaling,Transition activity and power,Low Power Design
principles,Energy Performance Curve,Concurrency(Reducing clk freq(same performance) and
Area for low power),Parallelism(How many processors in parallel depends majorly on
reduction of VDD) and Pipelining(we should scale Vdd utilizing the speed up obtained if
we want low power design),Time Multiplexing to use same block again and again
26 25.EE141 - 4/27/2012 - Leakage Power, If a block is not being used turn off the clock
as well as disconnect from data bus,Staic power (Leakage power) reduction - [Link]
switches(Power gating) to disconnect power when not in use, [Link] biasing - increase
the Vth when not in use so that leakage current reduces substantially, [Link] voltage
Ramping->ramp from Vdd to 0 when not in use 4. Transistor stacking(Increase resistance
and for upper transistor Vth also increases due to body effect and thus current reduces
more),Power Gating(implicit transistor stacking) MTCMOS(Multi threshold CMOS), Digital
Circuit - Future Possibilities