0% found this document useful (0 votes)
220 views4 pages

Booth's Algorithm for Binary Multiplication

The document describes the Booth multiplication algorithm for multiplying binary integers represented in two's complement form. It explains that the algorithm works by examining pairs of bits in the multiplier and either adding, subtracting, or leaving unchanged the multiplicand in the partial product. The algorithm is implemented in hardware using registers to store the multiplicand, multiplier, and partial product, along with control logic to shift values and determine whether to add, subtract, or leave unchanged the multiplicand based on the examined multiplier bits. An example is provided showing the step-by-step multiplication of two negative numbers.

Uploaded by

Moses Dian
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
220 views4 pages

Booth's Algorithm for Binary Multiplication

The document describes the Booth multiplication algorithm for multiplying binary integers represented in two's complement form. It explains that the algorithm works by examining pairs of bits in the multiplier and either adding, subtracting, or leaving unchanged the multiplicand in the partial product. The algorithm is implemented in hardware using registers to store the multiplicand, multiplier, and partial product, along with control logic to shift values and determine whether to add, subtract, or leave unchanged the multiplicand based on the examined multiplier bits. An example is provided showing the step-by-step multiplication of two negative numbers.

Uploaded by

Moses Dian
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Multiplication for binary integers in signed-2's complement

representation
or
Booth Multiplication Algorithm
• Multiplication M x 14, where M is the multiplicand and 14 the multiplier, can be done as
M x 24 - M X 21 •
• Because +14 can be represented in binary as 001110. It has a string of 1's in the
from bit weight 2k to weight 2m and it is equivalent to 2k+1 - 2m.
• So, the number 14 can be represented as 2k+ l - 2m = 24 - 21 = 16 -2 = 14.
• Thus, the product can be obtained by shifting the binary multiplicand M four times to the
left and subtracting M shifted left once.
• Booth algorithm is based on the above said fact.
• Booth algorithm requires examination of the multiplier bits and shifting of the partial
product.
• Prior to the shifting, the multiplicand may be added to the partial product, subtracted
from the partial product, or left unchanged according to the following rules:
1. The multiplicand is subtracted from the partial product upon facing the first least
significant 1 in a string of 1's in the multiplier. i.e. Qn=1, Qn+1=0.
2. The multiplicand is added to the partial product upon facing the first 0 (provided that
there was a previous 1) in a string of O's in the multiplier. i.e. Qn=0, Qn+1=1
3. The partial product does not change when the multiplier bit is identical to the
previous multiplier bit. i.e. Qn=0, Qn+1=0 or i.e. Qn=1, Qn+1=1.

• The algorithm works for both positive or negative multipliers in 2's complement
representation.
• For example, a multiplier equal to - 14 is represented in 2's complement as 110010 and is
treated as - 24 + 22 - 21 = - 14.

Hardware implementation of Booth algorithm:


• We use 3 registers namely AC, BR, and QR.
• Accumulator AC is used for storing partial product along with QR register.
• Multiplicand and multiplier are stored in BR and QR respectively.
• Qn indicates the least significant bit of the multiplier in register QR.
• An extra flip-flop Qn+1, is appended to QR to facilitate a double bit inspection of the
multiplier.
• Sequence counter SC is set to a number n equal to the number of bits in the multiplier.
• The hardware implementation of Booth algorithm is shown in the following figure.
Hardware for Booth algorithm

• AC register and appended bit Qn+1 are initially cleared to 0.


• The two bits of the multiplier in Qn and Qn+1 are inspected.
• If the two bits are equal to 10, it means, it requires a subtraction of the
multiplicand from the partial product in AC. i.e. first 1 in a string of 1' s has
been encountered.
• If the two bits are equal to 01, it means, it requires the addition of the
multiplicand to the partial product in AC. i.e. first 0 in a string of 0' s has
been encountered.
• When the two bits are equal, the partial product does not change.
• An overflow cannot occur because the addition and subtraction of the
multiplicand follow each other.
• As a consequence, the two numbers that are added always have opposite
signs, a condition that avoid an overflow.
• Next step is to shift right the partial product and the multiplier in AC and
QR (including bit Qn+1).
• This is an arithmetic shift right(ashr) operation which shifts AC and QR to
the right and leaves the sign bit in AC unchanged.
• The sequence counter is decremented and the computational loop is
repeated n times.
• A numerical example of Booth algorithm is shown in the following table for n = 5.
• It shows the step-by-step multiplication of (- 9) x (- 13) = + 117.
• Note that the multiplier in QR is negative and that the multiplicand in BR is also
negative.
• The 10-bit product appears in AC and QR and is positive.
• The final value of Qn+1 is the original sign bit of the multiplier and should not be taken
as part of the product.

Common questions

Powered by AI

Booth's algorithm optimizes multiplication by minimizing the number of arithmetic operations required. When multiplying a number M by a constant like 14 in binary, the algorithm reinterprets 14 as 2^4 - 2^1, which involves shifting M left by four positions, then subtracting M shifted left by one position. This re-encoding reduces the number of operations and multiplies M by efficiently handling strings of consecutive 1s in the multiplier .

In Booth's algorithm, the Qn and Qn+1 bits are crucial for determining the operations performed on the multiplicand and the partial product. If Qn=1 and Qn+1=0, the multiplicand is subtracted from the partial product, whereas if Qn=0 and Qn+1=1, the multiplicand is added. If they are both equal, the partial product remains unchanged. This mechanism helps in optimizing the process of multiplication in binary systems by minimizing unnecessary operations .

Booth's algorithm offers significant methodological benefits over traditional binary multiplication techniques by reducing the number of necessary arithmetic operations. It leverages patterns in binary representation, especially in strings of 1s, to minimize operations through strategic additions and subtractions, rather than executing a sequence of shifts and adds for each bit. This results in increased efficiency, particularly when dealing with multipliers that contain repeated bits, reducing redundancy and computational overhead .

The hardware components AC, BR, and QR play critical roles in Booth's algorithm implementation. AC (Accumulator) holds the partial product and eventually part of the final product, while BR keeps the multiplicand throughout the process. QR contains the multiplier and interacts with Qn and Qn+1 to control when additions or subtractions occur. These registers facilitate controlled data manipulation, streamlining the multiplication process by ensuring operations are conducted efficiently without unnecessary recalculations .

Booth's algorithm avoids overflow by ensuring that the numbers being added always have opposite signs due to the alternating addition and subtraction of the multiplicand from the partial product. This systematic procedure avoids the scenario where two large positive or negative values are summed, which could lead to overflow .

To initialize Booth's algorithm, the following steps are performed: set the Accumulator (AC) and the appended bit Qn+1 to 0; load the multiplicand into the BR register and the multiplier into the QR register; Qn represents the least significant bit of the multiplier in QR; initialize the sequence counter (SC) to the bit-length of the multiplier. This setup prepares the registers and counters needed to systematically apply the algorithm's rules across all the multiplier's bits .

Booth's algorithm ensures the correct result for negative binary integers by using the 2's complement representation, which inherently handles negative numbers in binary arithmetic. As such, when both the multiplicand and the multiplier are negative, as in the example of multiplying -9 by -13, the algorithm correctly computes the positive product 117 by systematically treating the multiplier as a combination of subtractions and additions that mirror the required binary shifts and arithmetic .

The sequence counter in Booth's algorithm is crucial as it tracks and controls the multiplication iterations. Initially set to the number of bits in the multiplier, the counter decrements with each cycle, ensuring that the process continues only for the required number of steps. This mechanism prevents unnecessary operations beyond the multiplier's capacity, aligning computational resources with the specific demands of the operation and ensuring that each bit is processed precisely .

Booth's algorithm effectively handles negative multipliers by leveraging the signed-2's complement representation. It treats negative multipliers as a combination of positive and negative powers of two, which allows for the systematic addition and subtraction of the multiplicand from the partial product. This approach maintains the integrity of the intended product calculation even with negative values, as shown by the example of multiplying negative numbers like -9 and -13, where both the multiplicand and multiplier are negative, yet the algorithm accurately computes the positive product .

Shifting operations are integral to Booth's algorithm as they facilitate the alignment of the partial product with the multiplier's position. An arithmetic right shift (ashr) is used, which maintains the sign bit of the product in the AC register unchanged during right shifts. This operation ensures that the partial product's sign remains correct after each iterative step, contributing to the accuracy of the final product without altering its sign unnecessarily .

You might also like