CHAPTER Single-Stage Amplifiers Amplification is an essential function in most analog (and many digital) circuits. We amplify an analog or digital signal because it may be too small to drive a load, overcome the noise of a subsequent stage, or provide logical levels to a digital circuit, Amplification also plays a critical role in feedback systems (Chapter 8). In this chapter, we study the low-frequency behavior of single-stage CMOS amplifiers. Analyzing both the large-signal and the small-signal characteristics of each circuit, we develop intuitive techniques and models that prove useful in understanding more complex systems, An important part of a designer's Job is to use proper approximations so as to create a simple mental picture of a complicated circuit, The intuition thus gained makes it possible to formulate the behavior of most circuits by inspection rather than by lengthy calculations Following a brief review of basic concepts, we describe in this chapter four types of amplifiers: ‘common-source and common-gate topologies, source followers, and cascode configurations. In each ‘case, we begin with a simple model and gradually add second-order phenomena such as channel-length modulation and body effect. 3.1 m Applications Do you carry an amplifier? In all likelihood, yes. Your mobile phone, laptop, and digital camera all incorporate various types of amplifiers. The receiver in your phone must sense and amplify small signals received by the antenna, thus requiring a “low-noise” amplifier (LNA) at the front end (Fig. 3.1). As the signal travels down the receive chain, it must be further amplified by additional stages so as to reach an acceptably high level. This proves difficult because, in addition to the small desired signal, the antenna picks up other strong signals (“interferers”) that are ransmitted by various other users inthe same vicinity Your phone's transmitter too, employs amplifiers: to amplify the signal gencrated by the microphone and, ‘eventually, the signal delivered to the antenna. The “power amplifier” (PA) necessary for such delivery draws the most energy from the battery and still presents interesting challenges. 3.2 m General Consideral ns, An ideal amplifier generates an output, y(¢), that is @ linear replica ofthe input, x(1) yen exo GB.)46 Chap. 3 Single-Stage Amplifiers Desired Interferer Signal Receiver ‘Amplifying Stages LS} [orem KES miter Figure 3.1. General RF transceiver, where ay, denotes the gain, Since the output signal isin fact superimposed on 2 bias (de operating) point, fap, we can write the overall output as y(t) = ao + ex(0). In this case, the input-output (large-signal) characteristic ofthe circuit is a straight line [Fig. 3.2(a)]. However, asthe signal excursions become larger and the bias point of the transistor(s) is disturbed substantially, the gain (the slope of the characteristic) begins to vary [Fig. 3.2(b)]. We approximate this nonlinear characteristic by a polynomial: VD = a0 text) $apr(A) Fp a_A"O) 62 A nonlinear amplifier distorts the signal of interest or creates unwanted interactions among several signals that may coexist at the input. We return to the problem of nonlinearity in Chapter 14, y, y @ & Figure 3.2 Input-output characteristic of (a) linear and (6) nonlineat system ‘What aspects of the performance of an amplifier are important? In addition to gain and speed, such parameters as power dissipation, supply voltage, linearity, noise, or maximum voltage swings may be Important. Furthermore, the input and output impedances determine how the circuit interacts with the preceding and subsequent stages, In practice, most ofthese parameters trade with each other, making the design a multidimensional optimization problem. Ilustrated in the “analog design octagon’ of Fig. 3.3 such trade-offs present many challenges inthe design of high-performance amplifiers, equiting intuition and experience to arrive at an acceptable compromise. ‘Table 3.1 gives a preview of the amplifier topologies studied in this chapter, indicating the much wider use of the common-source (CS) stage than other circuit configurations. For these amplifiers, we must (1) sel up proper bias conditions so that each transistor provides the necessary transconductance and output resistance with certain quiescent currents and voltages, and (2) analyze the circuit's behavior as the input and output signals cause small or large departures from the bias input (small-signal and large-signal analyses, respectively). We deal with the later task here and defer the former to Chapter 5.Sec.3.3 Common-Source Stage a7 Noise > Lin Power Sain Dissipation InpuvOutput supply Impedance Votta ‘ Vottage ‘Speed ae ne ‘Swings Figure 3.3. Analog design octagon, Table 3.1 Ampitier categories. Commor-Sauree Stage Source Follower CommonGate Stage Castode Win Resistve Load With Resistive Bias With Resisve Load Telescopic Witn Diodo-Connected Load With Current-Source Bias With Current- Source Load Folded Win Current Souree Load Wit Active Load: Witn Source Degeneration 3.3 = Common-Source Stage 3.3.1 Common-Source Stage with Resistive Load By virtue ofits transconductance, a MOSFET converts changes in its gate-source voltage toa small-signal drain current, which can pass through a resistor (o generate an output voltage. Shown in Fig. 3.4(a), the ‘common-source stage performs such an operation.) We study both the large-signal and the small-signal behavior ofthe circuit. Note thatthe input impedance of the citcut is very high at low frequencies. If the input voltage increases from 2er0, Mis off and Vayr = Von Fig. 3.4(b)]. As Vin approaches Ven, My begins to tum on, drawing current from Rp and lowering Vay. Transistor My tums on in saturation regardless of the values of Vpp and Ry (Wwhy?), and we have 1 cM Wg Ven)? > ‘po — Roz HeCurp Win ~ Vr) 3) here channel-length modulation is neglected, With further increase in Vig, Vue drops more, and the tran- sistor continues to operate in saturation until Vi, exceeds Vous by Vr [point A in Fig. 34(b)]. Atthis point, Via ~ Vi = Vow ~ Rog aCur Wat — Vr)? 64) from which Vi.j — Vry and hence Vou; can be calculated, For Vn > Vins Min he tide region er = Vow = RorgtinCos © [2Vin Vein Vos = Ve 65) The common-souee topology is denied a teeing te input atthe gat and producing the ouput athe dain48 Chap. 3 Single-Stage Amplifiers Vout Yoo Vine Ven Vise Vin @ Figure 3.4. (a) Common-source stage, (b) input-output characteristic, (c) equivalent circuit inthe deep triode region, and (d) smalls ‘model fr the saturation region, If Vi is high enough to drive M; into the deep tiode region, Vasy < 2(Vin — Vrv1) and, from the equivalent cireuit of Fig. 3.40), Yop y G6) Yoo an 1 C, Wr, (Vin — Vein) aCasap Ro(Vin = Ve Since the transconductance drops in the wiode region, we usually ensute that Vous > Vin — Vir and hence the current operates to the left of point A in Fig. 3.4(b). Using @.3) asthe input-output characteristic and viewing its slope as the small-signal gain, we have Mu a = 6 = Ro daCon Win = View) 69 = -snRo 3.10) “This result can be directly derived from the observation that M, converts an input voltage change AV, to a drain current change gq AViy, and hence an output voltage change —gm, Rp AVin. The small-signal model of Fig. 3.4(d) yields the same result: Vay = 8 ViRp = —8m Vin Rp Note that, as mentioned in Chapter 2, Vi, Vi, and Vou in this figure denote small-signal quantities. Even though derived for small-signal operation, the equation A, = —g Rp predicts certain effects if the citouit senses a large signal swing. Since gq itself varies with the input signal according toSec.3.3 Common-Source Stage Bn = HnCor(W/L)(Vos — Vr), the gain of the circuit changes substantially ifthe signal is large. In other words, ifthe gain ofthe circuit varies significantly with the signal swing, then the circuit operates in the large-signal mode. The dependence ofthe gain upon the signal evel leads to nonlinearity (Chapter 14), usually an undesirable effect. ‘A-key result here is that to minimize the nonlinearity, the gain equation must be a weak function of signal-dependent parameters such as gn. We present several examples of this concept in this chapter and in Chapter 14. > Example3.1 Sketch the rain curent and wansconductance of M; in Fig. 3.4(a) as a function ofthe input voltage. Solution ‘The drain current becomes significant for Vip > Vrw. eventually approaching Vow Rp if Regt & Rp (Fig. 3.5(@)). Since in saturation, fq = fen Cox W/LM Vr), the transconductance begins to rise for Vi, > Vev. In the tiode region, Nanometer Design Notes How does the CS stage behave in nanometer technologies? The figure Br = HnCox(W/L)Vps, falling as Vi, exceeds Vig) (Fig. 35(b)]. Staring with Bq, (5), the reader can show that Vout ttn Cont W/L Rp Vout ey Win TP enon WIERD Vin A plots the simulated input-output char- acteristic for W/L = 2 ym/40 nm, Ry = 2kA and Vop = 1V. We observe that the circuit provides a gain of about inthe input range of0.4 V0.0 V. The outputswingis imitedto abowo.3V-0.8 Vor the gan not to crop significantly ‘which reaches a maxinnan if Vous Vin — Vw (point A), Vin Vin Vin Viet Vin Figure 3.5 < > Example3.2 ACS stages driven by a sinusoid, Vig = Vj cos 0y¢ + Vo, where Vos the bias value and Vis large enough to drive the transistor ito the off and trode regions. Sketch the gy ofthe transistor as a function of time Solution ‘Lets first sketch the output voltage Fig. 3.6), noting that when Vix = Vi + Vo, Vou is low, My isin the triode region, and fy assumes a small value. AS Vip falls and Voy, and fy Fse, Mh enters saturation at¢ = (when Vig ~ Vous Vu) and gy reaches its maximum (why). As Vig falls further, s0 do Ip and gy. AL! = 1p fm teaches zer0 ‘We observe that (@) since the voltage gain is approximately equal to ~gy, Rp It experiences the same variation 8 the gm and (b) gm varies periodically? We even expres aba Fourie seis in mote advanced cous.50 Chap. 3 Single-Stage Amplifiers Sm H & t Figure 3.6 < How do we maximize the voltage gain of a common-source stage? Writing (3.10) as G12) G.13) ‘Thus, the magnitude of A, canbe increased by increasing W/L or Vgp or decreasing Jp if other parameters are constant. It is important to understand the trade-offs resulting from this equation. A larger device size leads to greater device capacitances, and a higher Vzp limits the maximum voltage swings. For example, if Von — Veo = Vie— Vr. then M; is atthe edge of the triode region, allowing only very small swings at the output (and input). If Vp remains constant and Jp is reduced, then Rp mustincrease, thereby leading (oa greater time constant atthe output node. In other words, as noted in the analog design octagon, the circuit exhibits trade-offs between gain, bandwidth, and voltage swings. Lower supply voltages further lighten these trade-offs, or large values of Rp, the effect of channel-length modulation in My becomes significant, Modifying (8.3) to include this effect, we have G15)Sec.3.3 Common-Source Stage 51 ‘We recognize that (1/2)s4yCox(W/L)Vin ~ Vr)*& = Iro and Ro Ay = Ron = SBA, 6.16) Thus, roRp ~t 7 A ao ein ‘The small-signal model of Fig. 3.7 gives the same result with much less effort. That is, since SmVi(roIRD) = —Vour and Vi = Vins We have Vou/ Vin = —Sm(ol Ro). Figure 3.7 Small-signal model of CS stage including the transistor output > Example3.3 ‘Assuming that My in Fig. 3.8 is biased in sateration, calculate the small-signal vollage gain ofthe circuit, z Figure 3.8 Solution Since 1, introduces an infiite impedance (Rp = co), the gain is limited by the output resistance of My: Avs Bro G8) Called the “intrinsic gain” ofa tanssto, this quantity represents the maximum voltage gain that can be achieved using a single device. In today's CMOS technology, gmro of short-channel devices is between roughly 5 and 10. We usually assume 1/sm «ro In Fig, 38, Kirchhofs curren law (KCL) requites that Ip1 =f. Then, how can Vix change the current of M, if is constant? Writing the total rain curent of My as 1 Ww at = 5btnCox Vin Io = 50Cu 0 Ven) + Vou) G19) h 20 sve note that Vig appears in the square term and Vay in the linear term. As Vip increases, Vag must decrease such satement simply < thatthe product remains constant. We may nevertheless say “Ip, inereases as Vig increases.” refers tothe quadeatic pat of the equation.52 > Example 34 Chap. 3 Single-Stage Amplitiers ‘An important conclusion here is that, to maximize the voltage gain, we must maximize the (small- signal) load impedance. Why can we not replace the load with an open circuit? This is because the circuit slill needs a path from Vip to ground for the bias current of My. Wis possible o use the bulk (back gate) of a MOSFET asthe terminal controlling the channel, Shown in Fig. 3:9 is an example. Determine the voltage gain if. =O. oo fe Vea Neem Den et “ a How do we design a CS stage fora “A " given gain and supply voltage? With he Figure 3.9 W/L, Ip, and Ro under our contol, we seem to have a wide design space. A ‘good starting pont i to choose a small 105 ym/40 nm, a low From the small-signal MOS model developed in Chapter 2, we recall thatthe drain 501A. and a sufi current is given by sims Vin. Ths, Ay ian large load resistance to achieve device, W/L bias curren’, Solution mo. the required gain. To this end, we use ion to plotthe transconductance fof such a device as a function of o, obtaining gn 0.45 mS. Thus, for 8 3.3.2 CS Stage with Diode-Connected Load voltage gain of, say, 10, Rp must reach D2 Knits Is tis an accopiable In some CMOS technologies, itis difficult to fabricate resistors with tightly- design? The answer depends on the controlled values ot a reasonable physical size (Chapter 19). Consequently, it applieation, In addition to gain, the el- sty certain bandwictn, noise, and output swing requirements. is desirable to replace Rp in Fig. 3.4(a) with a MOS transistor. ‘A MOSFET can operate as a small-signal resistor if its gate and drain ate shorted [Fig. 3.10(2)]. Called a “diode-connected” device in analogy with its bipolar counterpart, this configuration exhibits small-signal behavior similar 1 that of two-terminal esistor. Note that the transistor is always in saturation because the drain and the gate have the same potential. Using the small-signal ‘equivalent shown in Fig. 3.10(b) to obtain the impedance of the device, we vwnite Vj = Vy and Jy = Vx/o + &m Vx. Thats, the impedance of the diode is simply equal to Vr/Ix = (1/8m)|lro ~ 1/8m- I body effect exists, we can ‘use the circuit in Fig. 3.11 to write Vi = ~Ve, Vis = Vx, and Vx Cam + meV + = 21) Diede-Connected Device @ w Figure 3.10 (@) Diode-connected NMOS and PMOS devices; (6) small-signal equivalent ciruitSec.3.3 Common-Source Stage 53 vm . 7 ImbVios Ui em fe Oe he : uO" KO (@) (b) igure 3.11 (a) Arrangement for measuring the equivalent resistance ofa diode-connected MOSFET; (©) small-signal equivalent circuit It follows that vs 1 Me ox Tx Sm + Bmb +70) : 1 =— tr 629 Bm + Sb > 1 G24) n+ San In the general case, Vx/'Ix = (1/8m)lIrol|(1/ms)- Interestingly, the impedance seen at the source of ‘M; is lower when body effect is included. Intuitive explanation of this effect is left as an exercise for the reader. From a large-signal point of view, a diode-comnected device acts as a “square-root” operator if its ‘curtent is considered the input and its Vas or Vas — Vrw the output (why). We zeturn to this point later. > Example3.5 ‘Consider the circuit shown in Fig. 3.12(a). In seme cases, we are interested in the impedance seen looking into the source, Ry. Determine Ry if = 0. ° © Figure 3.12 Impedance seen atthe source with k = Solution To determine Ry, we set all independent sources to zero, draw the small-signal model, and apply’ a voltage source as shown in Fig. 3.12(). Since Vj = —Vy and Vp, = —Vy, we bave Cm + tm )Vx = Ix 625)54 Chap. 3 Single-Stage Amplitiers and ve Te ta tems 626 This result should not be surprising: the topologies in Fig. 3.12(a) and Fig 3.11(a) are similar except thatthe drain of| ‘My in Fig, 3.12(b) is not ata ground, This difference does not manifest tse if 2, = 0. We sometimes say, “looking into the source of a MOSFET, we see Ie. assuming implicitly that k= y = < We now study a common-souce stage with a diode-connected load (Fig. 3.13). With negligible channel-length modulation, (3.24) can be substituted in (3.10) for the load impedance, yielding 6.27 3.28) where n = gais/na Expressing fq and gaa in terms of device dimensions and bias currents, we have VELAWIOT Ay = — FETE TON 3.2 V2 Co (W/L)at pr 6m) sav, since I (W/L)y 1 - 3 \ Wit G30) ‘This equation reveals an interesting property: if the variation of n with the output voltage is neglected, the gain is independent of the bias currents and voltages (so long as My slays in saturation). In other ‘words, as the input and output signal levels vary, the gain remains relatively constant, indicating that the input-output characteristic is relatively linear, Yoo Lp ms Vout Vin he Ma Figure 3.13. CS stage with = diade-connected load. The linear behavior of the circuit can also be confirmed by large-signal analysis. Neglecting channel- length modulation for simplicity, we have in Fig. 3.13, ben (2), eno! = fou en W) ) ¥ (F) We Yo = G32)Sec.3.3 Common-Source Stage 55 “Thus, if the variation of Vriza with Vow is small the circuit exhibits @ linear input-output characteristic. In essence, the squating function performed by M; (from the input voltage to its drain curvent) and the square root function performed by M;(Srom its drain current to its overdsive) at as f—(F(Q)) = x “The small-signal gain can also be computed by differentiating both sides with respect to Vi, (4 “which, upon application ofthe chain rule &Vr2/@Vig = (@Vr42/8 Vows) BVous/8Vin) = CB Vous reduces to 633) in) Wik 1 W/L T+ is instructive to study the overall large-signal characteristic of the circuit as well. But let us firs. ‘consider the circuit shown in Fig. 3.14(a), What is the final value of Vay if Ty drops to zero? As Ij decreases, so does the overdrive of Mz. Thus, for small 1, Ves» © Vea and Vssr © Vow — Verna In reality, the subthreshold conduction in M; eventually brings Voy, to Vpo if Ip approaches zero, but at 34) very low current levels, the finite capacitance at the output node slows dawn the change from Vow —Vrw2 to Vpp. This is illustrated in the time-domain waveforms of Fig. 3.14(b). For this reason, in circuits that Ihave frequent switching activity, we assume that Vay: remains around Vp — Vrjx when J; falls to small values. hh Yoo Voo-Vria 7 % @ & Figure 3.14 (2) Diode-connected device with stepped bias current; (b) variation of source voltage versus time, ‘Now we return to the circuit of Fig. 3.13. Plotted in Fig. 3.15 versus Vj, the output voltage equals Vp ~ Vrs if Vin < Vee. For Viy > Vea, Eq. (3.32) holds and Vy, follows an approximately stright line. As Vip exceeds Voy, + Vrin1 (beyond point A), My enters the triode region, and the characteristic becomes nonlinear Vath Voo - Vira] Figure 3.15 Input-outpt characteris ecb ras tage with dod connected Viet Vin joad.56 Chap. 3 Single-Stage Amplifiers ‘The diode-connected load of Fig. 3.13 can be implemented with a PMOS device as well. Shown in. Fig. 3.16, the cizcutis fre from body effect, providing a small-signal voltage gain equal to fag W/E) i /W]D2 Ay 8.35) where channel-length modulation is neglected. Yoo Em Vout Vin fa Mi Figure 3.16 CS stage with diode- ? connected PMOS device Equations (3.30) and (3.35) indicate that the gain of a common-source stage with diode-connected load is a relatively weak function of the device dimensions. For example, to achieve a gain of 5, He W/L),/{p.p(W/L)3] = 2S, plying that, with p, ~ 24, we must have (W/L), ~ 12.5(W/L).In a sense, hig gain requires a“strong” input device and a “weak” load device. In addition to disproportion- ately wide orlong transistors (and hence a large input or load capacitance). high gai translates to another important limitation: reduction in allowable voltage swings. Specifically, since in Fig. 3.16, foi = Io WY Was — Vem ©) Wass = Vous 836) i£2.= 0, revealing that Wess — ¥ Neem Den et oy es Lt us design and simulate a CS stage wath a diode-connested PMOS load in Inthe above example, the overdeive voltage of My must be times that of M, 4o-nm technology. We select W/L For example, with Vos: — Veni = 100 mV and [Vie] = 03 V, we have 5 1um/40 nm for the NMOS device and |¥55| = 0.8 V, severely limiting the output swing. This is another example 4 m/40 nm for the PMOS device. The large-signal LV characteristic is shown of the trade-offs suggested by the analog design octagon. Note that, with nvetgoe. Websense natthecrest diode-connected loads, the swing is constrained by both the required overdrive provides a smalsignal gain of about Voltage and the threshold voltage. That is, even with a small overdrive, the 4LStor an input range ofroughly0.4Vto output level cannot exceed Vp — |Vrath 05. this de sneep, Vor can each An interesting paradox arises here if we write gq—sC..(W/L)l Yoo when the inputiransistoris oft) y... _ Vr]. The voltage gain of the circuit is then given by lad = 6.38) Bn bin Cox(W /L (Vas = Voun) G9) yp Cox(W]D)alVos2 — Veal Equation (3.39) implies that A, is inversely proportional to Vas: ~ Vruh tis left for the reader to resolve the seemingly opposite ends suggested by (8.37) and 3.39),Sec.3.3 Common-Source Stage > Example3.6 Inthe citouit of Fig. 3.17, My i biased in saturation with a drain curent equal to), The curent source Js = 0.751 is added tothe circu. How is (3.37) modified for this case? Assume i Vo hm: O's Viney mt Figure 3.17 Solution, Since [Ip2l = 11/4, we have Ae G40) =— fee aad Vide oe Morsove Be (4) (os ~ Ven? ) (Vosa = Vera) G43) yieking Woss— Vena) _ Av ean Vosi=Veus 4 ‘Thus, for again ofS, the overdrive of M; need be only 1.25 times that of My. Alternatively, for a given overdrive voltage, this ciouit achieves a gain four Gimes that of the stage in Fig. 3.16, Intuitively tht is because for a tiven Vasa — Viral ifthe cutentdeceases by a factor of 4, then (W/L mst decrease proportionally, and snd = BipCor\W7yoTpa is lowered by the sare facto. < > Example3.7 A student atempts to calculate the voltage gain in the previous example by differentiating both sides of (3.42), Docs this approaci give a correct result?” Why? Solution Since Vos1 = Vou ~ Vo. differentiation and multiplication by Coy yield WY wy, 2 c, (© " vaca (S) e-em snp (2), =n tn oss Ie follows that 9Vpus/Vin = ~@mi/(48n2)- This incorrect result arises because (3.42) is valid for only one value (of Vin. AS Vin is perturbed by the signal, 1, departs from 4[7| and (3.42) cannot be differentiated <58 Chap. 3 Single-Stage Amplifiers In today's CMOS technology, channel-length modulation is quite significant and, more important, the behavior of tansistors notably departs from the squate law. Thus, the gain of the stage in Fig. 3.13 must be expressed as d= sa (Lire) os where gq1 and gy: must be obtained as described in Chapter 17. 3.3.3 CS Stage with Current-Source Load In applications requiting a large voltage gain in a single stage, the relationship A, = —g,,Rp suggests that we should increase the load impedance of the CS stage. With a resistor or diode-connected load, however, increasing the load resistance translates to a large de drop across the load, thereby limiting the output voltage swing ‘A mare practical approach is to replace the load with a device that does not obey Ohm's law, e.g... current source, Described briefly in Example 3.3, the resulting circuit is shown in Fig. 3.18, where both transistors operate in saturation, Since the total impedance seen at the output node is equal to ro1|iro2. the gain is given by is Ay = —$mi(roiliro2) 8.49) ‘The key point here is thatthe output impedance and the minimum required |Vins| of Mo are less strongly coupled than the value and voltage drop of a resistor; the former need not satisfy Ohm's law, but the latter ust, The voltage [Vpsz min] = [Vaso — Vr can be reduced to less than a hundred millivolts by simply Increasing the width of Mz, Ifr93 isnot sufficiently high, the length and width of M can be increased to achieve a smaller 2 while maintaining the same overdrive vollage. The penalty is the larger capacitance Introduced by M; at the output node. Figure 3.18 CS stage with cu ‘We should remark thatthe output bias voltage ofthe cicuit in Fig. 3.18 isnot well-defined. Thus, the stage is reliably biased only ifa feedback loop forces Vou t0 a known value (Chapter 8). The large-signal analysis of the circuit is left as an exercise for the reader ‘As explained in Chapter 2, the output impedance of MOSFETs ata given drain current ean be scaled by changing the channel length, i. tothe first order, cc 1/L, and hence ro c L/Tp. Since the gain of the stage shown in Fig. 3.18 is proportional to rou Iroz, We may surmise that longer transistors yield a higher voltage gain Letus consider My and My separately. If Ly is scaled up by a factor of (> 1), then W may need to be scaled proportionally as well. This is because, fora given drain curtent, Vast — Vran & 1/ /W7EN. ice, if Wi is not scaled, the overdrive voltage increases, limiting the output voltage swing. Also, since Sm & VOWTEY scaling up only Ly lowers guaSec.3.3 Common-Source Stage In applications where these issues are unimportant, W; can remain constant while L; increases. Thus, the intinsic gain of M; can be waitten as 1 Ft) paColo Gar ) malar > sniror = 2 indicating thatthe gain increases with L because % depends more strongly on L than gy does. Also, note that gmro decreases as Ip increases. Increasing L; while keeping W; constant increases ro; and hence the voltage gain, but atthe cost of higher [[Link] Which is required to maintain M; in saturation, > Example3.8 ‘Comypate the maximum output voltage swings of CS stages with resistive and current-source loads, Solution, For the resistvely-loaded stage (Fig. 3.19(a)), the maximum outpet voltage is near Vpp (when Vin falls to about Vein). The minizaum is the value that places My a the edge ofthe triode region, Vie = Vrini Yep Vop~ [Vesa Viva 7” wet itz at Edge of My Saturation Yin oe Vin = Vive Vin Af Me Vin— Veet @ © Figure 3.19 Ourput swing in CS stage with (a) resistive load and (b) curent-source lead For the stage with a current-souce load [Fig. 3.19¢b)] the maximum ouput voltage is that which places My at the edge of the triode region, Von ~ [Voss — Vrir2| Thus, the latter actually provides smaller swings than the {otmer, but can always achieve a higher gain if Ly and L> ate increased. 3.3.4 CS Stage with Active Load In the amplifier topology of Fig. 3.19(b), the PMOS device serves as a constant current source, Is it possible for M; to operate as an amplifying device? Yes; we can apply the input signal to the gate of ‘My as well [Fig. 3.20(a)], converting it to an “active” load. The reader may recognize this topology as a CMOS inverter. Suppose both transistors are in saturation and Y;, rises by AVo. Two changes now occur: (@) In, increases, pulling Vous lower, and (b) Ma injects less curtent into the output node, allowing Vous to ddrop. The two changes thus enhance each other, leading to a greater voltage gain. Equivalently, as seen in Fig. 3.20(b), the two transistors operate in parallel and collapse into one as illustrated in Fig. 3.20(c), Ie follows that —(gai + Sn2) Vin(Fo1lIPo2) = Vou, and hence Ay (rat + $m2)(rorllrox) 3.48) Compared to the amplifier of Fig. 3.19(b), this eircuit exhibits the same output resistance, ro1||ro2 higher transconductance. This topology is aso called a “complementary CS stage: ‘The amplifier of Fig. 3.20(a) must deal with two critical issues. First, the bias current of the two Uansistors is a strong function of PVT. In particular, since Vas: + [Vasal = Vop, Variations in Vop or the threshold voltages directly translate to changes in the drain currents. Second, the cizcuit amplifies ut 5960 Chap. 3 Single-Stage Amplifiers (80+ 8m2in $F ||ro2 ® © o Figure 3.20. (2) CS sage with active load, (b) small-signal model, and (c) simplified model supply voltage variations (“supply noise”)! To understand this point, consider the arrangement depicted in Fig. 3.21, where Vp is abias voltage to place M; and M; in saturation, In Problem 3.31, we prove that the small-signal gain from Vip to Voy: is given by Vout _ Smaton +1 Vow ror Tot 01 49) Nanometer Design Notes With minimum channel lengths, the CS stage wih current-source load provides a low gain, For example, 1 W/Dywos = 5 prvi40 nm and (W/L) patos — 10 40 nm, we obtain the input-output charactarisc shown in the ‘igure, where the maximum gain is Ve about 25 If we plol the slope, wo also see the useful output voltage range to be about 0.7 Vwith Von = 1 V. Outside this range, the gain drops consiceraly about half of the A, found above. These issues are addressed in Chapter 5 Figure 3.21 Arrangement for study- ing supply sensitivity of CS stage with tive load, 3.3.5 CS Stage with Triode Load AMOS device operating in the deep tiode region behaves as a resistor and ‘can therefore serve as the load in a CS stage. lustrated in Fig. 3.22, such a citcuit biases the gate of Mz ata sufficiently low level, ensuring that the load is in the deep wiode region for all output voltage swings. Since Rog = G51 FyCu WT Dao ~ Vo = Wr --| the voltage gain can be readily calculated. “The principal drawback of this circuit stems from the dependence of Rox aby ELL upon sepCoe. Vs. and Vrire. Since j4pCox and Vrxp vary with process and temperature, and since generating a precise value for Vs requires additional ‘complexity, this circuit is difficult to use. Triode loads, however, consume #77 #7 _*_' less voltage headroom than do diode-connected devices because in Fig. 3.22, Veurmar = Voo. Whereas in Fig. 3.16, Vousmax * Voo [Vote ealSec.3.3 Common-Source Stage Yoo Yoo [ Ma Rona Me Vest > Vet Vinh my Vie he Mi = z Figure 3.22 CS stage with trode load, Among the five CS variants studied above, those employing resistive, current-source, or active loads find wider usage than the other two. Yoo o Ro a Ma} —eVoa nV Yoel 6 Rs Rs ® Figure 3.23 CS stage with source degeneration, 3.3.6 CS Stage with Source Degeneration In some applications, the nonlinear dependence of the drain current upon the overdrive voltage introduces ‘excessive nonlinearity, making it desirable to “sofien” the device characteristics. In Sec. 3.3.2, we noted the linear behavior of a CS stage using a diode-comnected load, which allows “postcorrection” of the nonlinearity. Alternatively as depicted in Fig, 3.23(a), this can be accomplished by placing a “degenera- tion’ resistor in series with the source terminal so as to make the input device more linear. Let us neglect ‘channel-length modulation and body effect. Here, as Vix increases, so do Ip and the voltage drop across Rs. That is, a fraction of the change in Vix appears across the resistor rather than as the gate-source overdrive, thus leading to a smoother variation of Zp. From another perspective, we intend to make the sain equation a weaker function of gn, Since Vour = Voo — IpRp, the nonlinearity of the circuit arises from the nonlinear dependence of [p upon Vin. We note that Vous /@Vin = —(81p/@Vix)Ro, and define the equivalent transconductance of the circuit 8 Gy = @7p/@Vin.? Now, assuming that Ip = f (Ves). we write aly 52) af aos © Was Pin 53) As explained late, the output voltage must be kept constant when Gy i ealeulated, 6Chap. 3 Single-Stage Amplifiers Since Vos = Vin = Ip Re, we have aVe5/8Viq = 1~ Rs@lp/2Viq, obtaining G54) Bot, f/Vass is the transconductance of My, and Gu To 8.55) ‘The small-signal voltage gain is thus equal t0 Ay =-G_Rp 656) = aa 657) ‘The same result can be derived using the small-signal model of Fig. 3.23(b) by writing a KVL, V, Vy + TpRs, and noting that Zp = g Vj, Equation (3.55) implies that as Ry increases, Gy, becomes a weaker function of gj and hence the drain current. In fact, for Rs > 1/Sm, We have Gy © 1/Rs, ie, Mp ~ AVia/Rs, concluding that most of the change in Vix appears across Rs. We Say that the drain current i a “linearized” function of the input voltage. In Problem 3.30, we examine this effect from a different perspective, The linearization is obtained at the cost of lower gain [and higher noise (Chapter 7) For our subsequent calculations, itis useful to determine Gy in the presence of body effect and. channel-length modulation, With the aid of the equivalent circuit shown in Fig, 3.24, we tecognize that the current through Rs equals fay, and, therefore, Vig = Vi ++ JoueRs. Summing the currents at node X, we have Rs 5 Tout = Bu¥i ~ BuoV — 658) 1 = Sm (Vin — Dat R5) + Buble Rs) — 659) Ie follows that 3.60) aaro =e 361 Bet (em been Roo een s skO- = Figure 3.24 Small-signal equivalent = cineuit of a degenerated CS stageSec.3.3 Common-Source Stage Letus now examine the large-signal behavior of the CS stage with Rs = Oand Rs # 0. For Rs = 0, our derivations in Chapter 2 indicate that Ip and gm vary as shown in Fig. 3.25(a). For Rs # 0, the turn-on behavior is similar to that in Fig. 3.25(a) because, at low current levels, 1/¢ > Rs, and hence Gm * 8m [Fig. 325(b)]. As the overdrive and therefore gy, increase, the effect of degeneration, 1+ fas in (3.55), becomes more significant, For large values of V, (if M; is stil saturated), I is approximately a linear function of Vi, and Gy approaches 1/Rs. to, my to Sm 4 Rs 1 Rs Vin Yin Vin Ven Yin Vin Vin Via ° Figure 3.25 Drain current and transconductance of a CS device (a) without and (b) with source degeneration > Example3.9 Plot the small-signal voltage gain of the circuit in Fig. 3.28 asa function of the input bas voltage, Vip. Solution Using the results derived above for the equivalent transconductance of My and Rs, we arrive atthe plot shown in Fig. 3.26. For Vp slightly greater than Viz, 1/gm > Re and Ay © —fmRp. As Vin increases, degeneration bbocomes more significant and Ay = —tm Rp/(1-+mRs). For large values of Vp, Gm, © 1/Rs and Ay = —Rp/Rs. However, if Vin > Vous + Vr. thats, if Rp/p > Vr + Vow — Vin. Mi enters the tiode region and Ay dos Il Po Rs Gn Ro Vea Vn Figure 3.26 < Equation (3.57) can be rewritten as 6.62) ‘This result allows formulating the gain by inspection, First, Jet us examine the denominator of (3.62). ‘The expression is equal to the series combination of the inverse transconductance of the device and the explicit resistance seen from the source to ground, We call the denominator “the resistance seen in the source path” because if, as shown in Fig. 3.27, we disconnect the bottom terminal of Rs from ground and calculate the resistance seen “looking up” (while setting the input to zero), we obtain Rs + 1/2n.64 Chap. 3 Single-Stage Ampliiers Nanomute Design Notes a4 IA corre els ipa ioe oe \ dectbaraMOSvancsorerpererces 4) Sitest# te Vag Vos or Vogexcnede an tartan its, For seampl, In 4-9 Rs Ses eee teme et 4 tran bolo 1 ltresingy te ca aor Figure 3.27 Restane een inthe Code stucrecan ave Gece ress 3m source path ‘even If Von Is greter than alowed, AS canbe sean from the ciagram oolow, 5 Pedaincuntedercatee sea Vena, Noting thatthe numerator of (3.62) is the resistance seen atthe drain, we prosches Vie Mr experencas Weg = view the magnitude of the gain as the resistance seen atthe drain node divided Vop, whereas Mz sees Vps ~ Ve- by the total resistance in the source path. This method greatly simplifies the Vive: Simla Voss < Voo why). analysis of more complex cizcuits ie > Example3.10 a vu Assuming A = y= 0, calulate the small-signal gain ofthe circuit shown in sett Fig. 52800, verte wert t + Voo Yoo Ro Ro Vout Vou Vin be Ms Vin fe Ms ft My a na ) ) @ Figure 3.28 Solution [Noting that Mf; isa diode-connected device and simplifying the circuit to tht shown in Fig. 3.28(b), we use the above rule to write Ry Avs 363) < Output Resistance Anotherimportant consequence of source degenerationis the increase inthe output resistance of the stage, We calculate the output resistance first withthe aid ofthe equivalent circuit shown in Fig. 3.29, where the load resistor, Rp, is excluded for now. Note that body effect is also included to Figure 3.29 Equivalent ciruit for ea- cilatng the output resistance of a degen- crated CS stageSec.3.3 Common-Source Stage aurive at a general result, Since the current through Rs is equal to Zy, Vy = —fyRs, and the current flowing through ro is given by Lx ~ (8m + &ms)Vi = Ix + Um + Suu) Rex. Adding the voltage drops across 'p and Rs, we obtain Tolls + (Gm + Sme)Rslx] + Ix Rs = Vx 64) Tefollows that Ros = U+ Gm + Sn) Relro + Re 6.65) = [+ Gm + fns)rolRs +10 6.66) Equation (3.65) indicates that ro is “boosted” by a factor of 1+ (gy + gms)Rs and then added to Ry. Asan alternative perspective, iq (3.66) suggest that Rs is boosted by a factor of 1 + (8m + fns)To (8 Value close to the transistor’ intrinsic gain) and then added to ro, Both views prove useful in analyzing circuits. Note that the overall output resistance is equal to the parallel combination of Ry and Rp. IE (sm + Sn)Fo > 1, we have Rout * (Bm + Sas)ORs +0 en = Ut m+ Smad RsIro 3.68) “To gain more insight, let us consider the cixcuit of Fig. 3.29 with Rs = Oand Rs > 0.1f Rs =0, then SnVi = SnsViy = O and Ix = Vx/ro. On the other hand, if Rs > 0, we have IRs > 0 and Vi obtaining negative gy ¥; and gysVsy."us, the current supplied by Vy is less than Vy /ro, and hence the output impedance is greater than ro. ‘The relationship in (3.65) can also be derived by inspection. As shown in Fig. 3.30(a), we apply a voltage to the output node, change its value by AV, and measure the resulting change, AJ, in the output ‘current. Since the current through Rs must change by AJ (why’), we first compute the voltage change across Rs, To this end, we draw the circuit as shown in Fig. 3.30(b) and note that the resistance seen looking into the source of M; is equal to 1/(em + ms) (Eq. 3.24)], thus arriving atthe equivalent circuit in Fig. 3.30(¢). The voltage change across Rs is therefore equal to 1 a's Vas ~ Av Seat 6.69) Rs to inte a liv _Tiv ~y — Fv Hf, $70 Hb, $70 4 a 7 atin " | Aves Aves Rs Rs * Rs @ (b) te Figure 3.30 (a) Change in dain cusent in response to change in applied voltage to dain (6) small-signal model66 Chap. 3 Single-Stage Amplifiers “The change in the current is AVas Re B70) Av 87) T+ Go ¥ gus) Roro + Re thatis, =U + Gm + Sas)RsIro + Re 872) ar With the foregoing developments, we can now compute the gun ofa degenerated CS sage inthe ener ize, faking int scsount hath body effect and channs-ength modslation. Inthe equivalent circuit Sepictedin Fig. 3.31the coment through Ry musteqval that rough Rp ,—Vaw/ Ro. Tbs he sree vallage with respect wo groin and heb) i 9 — Vou s/ Ro, yielding Vi ~ Vig + VouRs/ Ro The eurent flowing trough ro from opto bottom can therfore be watt as Mow. — (Vi + ens Vid 3.73) Te (enV + asi 6 Vout Rs Yo 6. (Vig + Vou BE 3 = |r (Via + You Gm) Figure 3.31 Small-signal model of degenerated CS stage with Gite output sesistance. Since the voltage drops across ro and Rs musta up C0 Ve, We ave G1 Re Rs Rs + Vou SE) gue 8] ro — Vane RE 3.76 Be) Seatage|re Mage 070 Ie folows that Vos Mos 5 Vin Smb)Rsro_ om To gain more insight ino this result, we recognize that the last three terms in the denominator, namely, Rs +ro + (Gm + Sus) Rero, represent the output resistance of a MOS device degenerated by a resistor Rs, a8 originally derived in (3.66). Let us now rewrite (3.77) as jy = DEATORDIRS + ro + Gn + Ba0)Rsto] 1 7s) Ro + Rs ro + (8m + Bmw) Ror Rs +ro + Gm + 8un)Rsro _. Baro RolRs + tns)Rsro] en) is +70 + Gm + Eui)Rsro | Ro (Gu + gue) RevoSec.3.3 Common-Source Stage 67 ‘The two fractions in (3.79) represent two important parameters of the circuit: the firs is identical to that in G.61), ie., the equivalent transconductance of a degenerated MOSFET; and the second denotes the parallel combination of Rp and Rs + ro + (tm + &ws)Rsro, ic., the overall output resistance of the ‘The above discussion suggests that in some circuits, it may be easier to calculate the voltage gain by exploiting the following lemma. We recall that the output port ofa linear circuit can be represented by a Norton equivalent (Fig. 3.32(8)| ‘Lemma In a linear circuit, the voltage gain is equal to ~Gy Rea, where Gy denotes the transconduc~ tance of the circuit when the output is shorted to ground (Fig. 3.32(b)] and Ray represents the output resistance of the circuit when the input voltage is set to zero (Fig. 3.32(c)] Gp Calcutation Roy Calculation “ ¢| = @ © © Figure 3.32. (2) Norton equivalent ofa linear cteut (b) Gy calculation; and (©) Rou calculation ‘The lemma can be proved by noting thatthe output voltage in Fig. .32(a) is equal 10 —Iyap Ruse, a0 Tuas can be obtained by measuring the short-circuit current atthe output. Defining Ge = Loe/ Vin. We have Vous = —Gy Vip Rou. This lemma proves useful if Gy and Ryyy can be determined by inspection Note the direetion of Lue > Kxample3.11 Calculate the voltage gain ofthe circuit shown in Fig. 3.33. Assume that J is ideal Yoo fo Vout Vin Aft Rs = Figure 3.33 Solution ‘The transconductance and output resistance ofthe stage ate given by Eqs. (3.61) and (66, respectively. Thus, Ay = alll + em + tmsdr0 IRs +70) 80) Rea Gn + BRO = =tnro ean Interestingly, the voltage gain is equal tothe intrinsic gain of the transistor and independent of Rs. This is because, i Ips ideal, the current through Rs cannot change, and hence the small-signal voltage drop across Ry is e10—as iF Rs were zero itselt <6 Chap. 3 Single-Stage Amplifiers 3.4 @ Source Follower (Our analysis ofthe common-source stage indicates tha, to achieve high voltage gain with limited supply voltage, the load impedance must be as large as possible. If such a stage is to drive a low-impedance load, then a "buffer" must be placed after the amplifier so as to drive the load with negligible reduction in gain. The source follower (also called the “common-drain” stage) can operate as a voltage butter. Gain Stage Butter Yop High Viney Resistance Vou @ Figure 3.34 (2) Source follower, (b) example ofits role as a butler, and (c) is input-output characterise Ilustrated in Fig. 3.34(@), the source follower senses the signal atthe gate, while presenting a high input impedance, and drives the load at the source, allowing the source potential to “follow” the gate voltage, Figure 3.34(b) depiets how the circuit can be used to drive a low resistance without degrading the voltage gain of a CS stage. Beginning with the large-signal behavior of the source follower, we note that for Vix < Vris, My is off and Vay: = 0. AS Vix exceeds Very, M; tums on in saturation (why?) and Tp, flows through Rs [Fig. 3.34(0)]. As Vi, increases further, Vag follows the input with a difference (evel shift) equal to Vos. We can express the input-output characteristic as J bap Cox © (Vin = Ven — Vout) Ro = V. 3:82) ln Con Win = Vi = Vou) Rs = Vou ¢ where channel-length modulation is neglected. Let us ealeulate the small-signal gan of the circuit by Aitferetiating both sides of (3.82) with respect to Vy 1g Woy —y, 3Vrn _ 8V g _ 3¥ou Flax 2V n= Ves — Vou) (1 -oe- ) Ry G8) Since AVp11/9Vie = @Ven/8V52)(Vsu/2Vin) = Vous! ®Vin. Co Vey, Vr DR . Cox Vie — Veit ~ Vous at ie Gay mod F Mn Conr Vin — Vr — Vow) Rs +n) [Aso note that Cy w (Vin — Vr 3.85) Sm = Hn opt fin — Ven — G.85)Sec.3.4 Source Follower Consequently, sm Re 8 3.86) "TH Gm smi) ‘The same result is more easily obtained with the aid ofa small-signal equivalent cireuit. From Fig. 3.35, ‘we have Vig — Vi = Vous Vir = —Vouts 20d 8m Vi — SupVour = Vour/ Re. TUS, Vou/ Vin = Sm Re/ll + (8m + Sms) Rs Figure 3.35 Smull-signal equivalent iteuit of source follower Sketched in Fig. 3.36 vs. Vin, the voltage gain begins from zero for Vin “ Veu (that is, gy ~ 0) and. ‘monotonically increases, As the drain current and gy, increase, Ay approaches gm /(8m't 8ms) = 1/1). Since » itself slowly decreases With Voy, Ay would eventually become equal to unity, but for typical allowable source-bulk voltages, n remains greater than roughly 0.2 Ay 10 a co Figure 3.36 Voltage guin of source Vn Yin follower versus input voltage An important result of (3.86) i that evenif Ry — 20, the voltage gain ofa source flloweris not equal to one (unless body effect is removed as explained Inter), We return to this point later. Note that My in Fig, 3.34) remains in saturation if V, does not exeeed Von + Vrus Th the soutce follower of Fig. 3.34(a), the dain current of Mf heavily depends on the input de level For example if Vg changes from 0.7 Vto 1 V, Ip may increase hy factor of 2, and hence Vas ~ Vein by V2. Even if Vr is relatively constant, the inerease in Vos means that Va (= Vx ~ Vos) does not follow Vj faithfully, thereby incuting nonlinearity. To alleviate this isue, the resistor can be replaced by a constant cutent source as shown in Fig. 3.37(a. The current source ssl is implemented as an NMOS, ttansistor operating in the saturation region (Fig. 3.3700) Yoo Yoo Yin ha Vo fe Ma Figure 3.37 Source follower using (@) aa ideal current source, and (b) an, ° © NMOS transistor as a current source.70 Chap. 3 Single-Stage Ampliiers > Example3.12 ‘Suppose that in the source follower of Fig, 3.37(a), (W/L); = 20/05, fy = 200 HA, Vea = O.6V, 20F =0.7V, Vp = 1.2 tinCox = 50 WAIV?, and y — 008 VE (@) Caleulate Voy for Vig = 12 V. () IC is implemented as My in Fig. 3.370) find the minimum value of (W/Z)> for which My emmins saturated when Vig = 12. Sotton (Since the thesold voltage of Bf, depends on Vy, we peform spe terion. Noting that ae Vin = Ve — Vou)? oa We ae = natu (F), we fr asume that Vy * 0.6 V obtaining Veg = 0.153 [Link] we calla new Vr a Vii = Vruo-+ 7(/Tbe = Ven ~ VTP) oy = 0635 089) This indicates that Vsu i approximately 35 mV less than that calculated above, i¢. Vous 0.118 V. () Since the rain-source voltage of Mz sequal (00.118 V the deviceis saturated only if (Vos—Vr)2 < O.LI8V. With Ip = 200 4A, this gives (W/L): = 287/0.5. Note the substantial drain junction and overlap capacitance contributed by Mp to te output node. < > Example3.13, Explain intwitively why the gsi ofthe source follower in ig. 3.37(a) is equal to unity if J i ideal and Solution In this case, the drain current of My remains exactly constant, and so does Ves. Since Ve = Vin ~ Vast. We jerve that a change in Vix must equally appear in Voy. Alteratively, a¢ shown in Fig. 3.38, we ean say thatthe -signal drain current cannot flow through any path and must be zero, yielding Vi = O and Vous = Vin Figure 3.38 < ‘To gain a better understanding of source followers, let us calculate the small-signal output resistance of the circuit in Fig. 3.39(a). Using the equivalent circuit of Fig. 3.39(b) and noting that Vy = —Viy, we write 8.90) I Bn Vx — gnbVe Ie follows that Ray = Gor Bm + Sb >Sec.3.4 Source Follower n ° % © Figure 3.39 Calculation of he output impedance of @ source follower. ‘This result should not come as a surprise: the circuit in Fig. 3.39(b) is similar to that in Fig. 3.1106). Interestingly, body effect decreases the output resistance of source followers. To understand wir, sup- pose that in Fig. 339(e), Vx. decreases by AV so tht the drain current increases. With no body ef fect, only the gate-source voltage of My would increase by AV. With body effect, on the other hand, the threshold voltage of the device decreases as well. Thus, in (Vos — Vrw)*, the first term increases and the second decreases, resulting in a greater change in the drain current and hence a lower output impedance. ‘The above phenomenon can also be studied with the aid of the small-signal model shown in Fig.3.40(). tis important to note thatthe magnitude of the current souree sy Vis = smeVi is linearly proportional to the vollage across it (because the current source and the voltage source are in parallel), Such a bbehavioris that of a simple resistor equal 1/9, Yielding the small-signal model shown in Fig, 3400). “The equivalent resistor simply appears in parallel with the output, thereby lowering the overall output resistance. Since without I/gy, the outpu resistance equals 1/9, we conclude that Rout = I 6.92) 6.93) ‘Modeling the effect of gn4 by a rsistor—which is valid only for soutce followers—also helps explain the less-than-unity voltage gain implied by (3.86) for Rs = oo, As shown in the Thevenin equivalent “ om x Wx a * ’ no ve Vx t fa) to) Figure 3.40 Source follower including body elect.n Chap. 3 Single-Stage Amplifiers Figure 3.41 Represeotation of of Fig. 3.41, 94) = = 3.95) BaF Et For completeness, we also study a source follower with a finite load resistance and channel-length modulation (Fig. 3.42(a)]. Noting that 1/gy rot. roa. and Ry ate in parallel, we can reduce the circuit 1/gm)lirosllroal| Rx. It follows that to that shown in Fig, 3.42(c), where Rey a= Pa 90 va i 6 % eo Vout & signal equivalent circuit; ()simplilied mode Figure 3.42 (@) Source follower diving load resistance; () > Example 3.14 Calculate the voltage gain ofthe circuit shown in Fig. 3.43, Solution The impedance seen looking into the source of Ms (a diode-connected device) is equal t [1/2 + &min)llro2 ‘The impedance appears in parallel with 1/zmo1 and ros. Thus, 1 vroulirot aia East een ——hroaliroii— + ea enna ooh | BoSec.3.4 Source Follower mez Yoo Vin Aft Vout it~+¥oo me z Figure 3.43, < Source followers exhibit a high input impedance and a moderate output impedance, but at the cost of two drawbacks: nonlinearity and voltage headroom linstation. We consider these issues in detail. ‘As mentioned in relation to Fig. 3.34(a), even if a source follower is biased by an ideal current source, its input-output characteristic displays some nonlinearity due to the nonlinear dependence of Vr; upon. the source potential. In submicron technologies, ro ofthe transistor also changes substantially with Vps. thus introducing additional variation inthe small-signal gain of the circuit (Chapter 14). For this reason, typical source followers suffer from significant nonlinearity. ‘The nonlinearity duc to body effect can be climinated ifthe bulk is tied to the source. This is usually possible only for PFETs because all NFETs share the same substrate. Figure 3.44 shows a PMOS source follower employing two separate n-wells so as to eliminate the body effect of My. The lower mobility of PFET, however, yields ahigher output impedance in this case than that available in an NMOS counterpart, Yoo Vo Mz Vout Vine my © © Figure 3.44. (2) PMOS source follower with no body effect; (b) corresponding layout showing separate n-wells. Source followers also shift the de level of the signal by Vics, thereby consuming voltage headroom and limiting the voltage swings. To understand this point, consider the example illustrated in Fig. 3.45, ‘cascade of a common-source stage and a source follower. Without the source follower, the minimum allowable value of Vy would be equal to Vosi — Vr (for M; to remain in saturation). With the source follower, on the other hand, Vx must be greater than Vas2 + (Vass — Vrus) so that My is saturated. For ‘comparable overdrive voltages in M; and Ms, this means the allowable swing at X is reduced by Vasa, a substantial amount. tis also instructive to compare the gain of source followers and common-source stages when the load impedance is relatively low. A practical example is the need to drive an external 50-9 termination in aChap. 3 Single-Stage Amplifiers Figure 3.45 Cascade of source follower and CS stage, Yoo Yoo Vine & Vout , Vine mi @ ® Figure 3.46 (a) Source follower and (b) CS stage driving a load resistance high-frequency environment, As shown in Fig. 3.46(2), the load can be driven by a source follower with an overall voltage gain of Vox Re oe 3. Vir | Ret lB G88) sR 9 T+ ami Re G99) (On the other hand, as depicted in Fig. 3.46(b, the load can be included as part of a common-source stage, providing a gain of Vout Vin 6.100) The key difference between these two topologies isthe achievable voltage gain for a given bias current For example, if 1/1 ~ Rus then the source follower exhibits a gain of a most0.5, whereas the common- source stage provides a gain close to unity. Thus, source followers are not necessarily efficient drivers. The drawbacks of sourve followers, namely, nonlinearity due to body effect and voltage headroom consumption due to level shi, limit the use ofthis topology. Asa general rule, we avoid the use of source followers unless they become absolutely necessary. One application of source followers is in performing voltage-level shift, as illustrated by the following example. > Example 3.15 (@) In the circuit of Fig. 3.47(a),calelate the voltage gein if C sets aan a short atthe Frequency of interest, What Js the maximum de level of the input signal for which M; remains saturated? () To accommodate an input de level close to Vpp, the circuit is modified as shown in Fig, 3.47(0). What relationship between the gate-source voltages of Mz and Ms guarantees that Mj is saturated?Sec.3.5 Common-Gate Stage 5 oe @ ) Figure 3.47 Solution (@) Noting thatthe source of My is at ac ground, we write the gain as Ae = ~gnilrolro2il(l/am) G10 Since Vour = Vo ~ [Vosal, the maximum allowable dc level of Vig is equal to Von ~ [Vo: (©) IF Vin = Vop, then Vi = Vo ~ Vgsy. For My to be saturated when Vi Voss — Vrin = Voo ~ IWasal, and hence Voss + Veni = Vasal 1+ Vr Vpp, we must have Vop — < As explained in Chapter 7, source followers also introduce substantial noise. For this reason, the circuit of Fig. 3.47(6 is ill-suited to low-noise applications. 3.5 m Common-Gate Stage In common-source amplifiers and source followers, the input signal is applied to the gate of a MOSFE’ Itis also possible to apply the signal to the source terminal. Shown in Fig. 3.48(a), a common-gate (CG) stage senses the input at the source and produces the output at the drain. The gate is connected to a de voltage to establish proper operating conditions, Note that the bias current of M; flows through the input signal source. Alternatively, as depicted in Fig. 3.48(b), Mj can be biased by a constant current source, with the signal capacitively coupled tothe circuit, Voo Yoo fo Ro v. Vout LVe JM My Yin” 9 ® Figure 3.48 (a) Common-gate stage with direct coupling at input () CG stage with capacitive coupling at input76 Chap. 3 Single-Stage Amplifiers Vout Myott Yoo Vo-Vrihe rn Min Saturation Triode Region Fm igure 3.49 Common-gste input Vo- Via Vie oiput characteristic. We first study the large-signal behavior ofthe circuit in Fig. 3.48(a), For simplicity, let us assume that Vin decreases from a large positive value, Also, i = 0. For Vix > Vs — Vir, My is off and Vaus = Vop. For lower values of Vj. we can write Low Ly = SH Cor Vi = In = Fela — Ven)? (3.102) if M; is in saturation, As Vjq decreases, s0 docs Vou, eventually driving My into the triode region if Vp ~ $sCox ¥(Vs— Vin ~Vru)*Ro = Ve ~ Ve 6.103) The input-output characteristic is shown in Fig. 3.49, illustrating 2 case in which My enters the triode region as Vj, decreases. In the region where M; is saturated, we can express the output voltage as Vous = Veo — HitnCox Vs ~ Vn ~ Ven)? G.104) obtaining a small-signal gain of Since #Vr4/4Vin = Vrn/AVs— - : Wn (3.106) = am(l+m)Ro (3,107) Note that the gain is positive, Interestingly, body effect increases the equivalent transconductance of the stage. For a given bias current and supply voltage (L., a given power budget), how do we maximize the voltage gain of a CG stage? We can increase gq by widening the input device, eventually reaching subthreshold operation [2 ~ o/(E Vr)] (why?), and/or we can increase Rp and, inevitably, the de drop across it, We must bear in mind that the minimum allowable level of Vay in Fig. 3.48(b) is equal to Vos ~ Vrir + Vin. where Vix denotes the minimum voltage required by I > Example3.16 (@) Is tepossible for My in Fig. 4.48(a) to remain in saturation forthe entice range of Vig fT0m Oto Vo? (©) Is it possible for Mf; to remain in the triode region forthe entire range of Viq from Oto Von?Sec.3.5 Common-Gate Stage Solution, (a) Yes, itis possible, To so guarante, we choose Vow — Roly > Ve Vr, where Fp denotes the dain current at Vin =0. (@) Yes, itis possible. Vj > Vow + Vrw. then My tums on a the edge ofthe tiode region at Vin = Vow — Vr and goes deeper as Vig falls, Of couse, this choice of Vp is neither practical nor desirable < “The input impedance ofthe circuit is also important, We note that for 3 = 0 the impedance seen a the source of My in Fig. 3.48) is the same as that atthe source of M; in Fig. 3.39, namely, 1/(8m+ Ent) 1/lam(1 + n)). Thus, the body elfect decreases the input impedance of the common-gate stage. The relatively low input impedance ofthe conamon-gate stage proves useful in some applications > Example3.17 In Fig, 3.50, transistor Mf, senses AV and delivers « proportional curren to 50-S2 transmission line, The other fend of the lin is termingted by a 50-2 resistor in Fig. 3.50(a) and a common-gate stage in Fig. 3.50(6). Assume ney =0. (2) Calculate Vpe/ Vie a low frequencies for both aangements () Woat condition is necessary to minimize wave reflection at node X? Yoo Jon at JUL ton a av Tes av, (uinte ‘ @ ) Figure 3.50 Solution (a) Por smal signals applied tothe gle of Mf, the drain caren experiences achange equal to fi AVx. This current is drawn from Rp in Fig. 350(a) and Mf in Fig. 3.50(), producing an output vllage swing qual lofi AVx Ro. Thus. Ay = ~gmi fox bob eases. {b) To minimize reflection a node X, the resistance seen a the souceof Mz must equal 50 £1 and the reactance aust be small. Thus, 1/(Gm2 + fda) = 50 ©, which can be ensued by proper sizing and biasing of Ma. To minimize the capacitances ofthe traitor, itis desirable to use a small device based wa large current Recall that tm = J¥iinCoxW7T}I 5) In ation to higher power dissipation, this remedy also requires «large Vo for Me. “The key point inthis example is tha, while the overall volage gain in both arrangements equals ~fm Rp, the value of Ro in Fig. 3.50(6) can be much greater than 50 2 without introducing reflections at pot X."Thus, the ‘commonest cteuit can provide «higher voltage enn han that in Fig. 3.50) < ‘Now let us study the common-gate topology in a more general case, taking into account both the output impedance of the wansistor and the impedance of the signal source. Depicted in Fig. 3.51(a), the circuit can be analyzed with the aid of its equivalent shown in Fig. 3.51(b). Noting thatthe curtent flowingChap. 3 Single-Stage Amplifiers @ w Figure 3.51. (a) CG stage with nite transistor output resistance; (b) small-signal equvaleat circuit rough Rs is equal to ~Vous/Ro, we have in =0 3.108) Moreover, since the current through ro is equal to —Vour/Ro — gm Vi — Sub Vi. we can write mt Vous vo (=fat=saroati) Hace ca Upon substitution for V; from (3.108), (3.109) reduces to Ve Ro VourRs Vig = Vor 3.110 Ro ‘ 7 1k follows that Vout, Gn + Sup)ro +1 R Vin Fo+ Bm + Bmp roRs + Rs+ Ro ul) Note the similarity between (3.111) and (3.77). The gain of the common-gate stage is slightly higher due to body effect > Example3.18, Calculate the voltage gain ofthe circuit shown in Fig. 352(a) 4 40 and y 0, Solution ‘We firs find the Thevenin equivalent of Mj and Vin. As shown in Fig. 3:52(b), Mj operates as «source follower, the equivalent Thevenin voltage is given by euSec.3.5 Common-Gate Stage @ © 9 Figure 3.52 and the equivalent Thevenin existance i Ray =r01 any nti amt Recrawing he cic ain Fig. 3.52(6), we we (3.111) 0 wte veall 2 Geet tenon ko a - ona rorttt=t6m~servoa(roif |) +80 ro) at “This example demonstrates the ease with which a circuit can be analyzed by inspection—while relying on previously derived results—rather than by blindly writing KVL-s and KCL. < ‘The input and output impedances of the common-gate topology are also of interest. To obtain the impedance seen atthe source [Fig. 3.53(a)], We use the equivalent circuit in Fig. 3.53(b), Since Vi = —Vr and the current through ro is equal to Ly + 8mVi + &mbVi = Lx — (Bm + Smé) Vx, We can add up the voltages across ro and Rp and equate the result to Rolx + rollx — (8m + &m6)Vx] = Var 3.115) Ix eo My > 7 Vee ro Ix wKeOr Figure 3.53 (a) Input resistance of a CG stage; () small-signal equivalent circuit.80 Chap. 3 Single-Stage Amplifiers Thus, Ve Ry vee 6.116) Te T¥ GF Suro Ro 1 oun «ke __t mF Bnd Sm 4 Bn if G+ gns)Fo > 1. This result reveals thatthe drain impedance is divided by (s+ gme)Fo When seen atthe source. This is particularly important in short-channel devices because of their low intrinsic gain, “Two special cases of (3.116) are worth studying, First, suppose Ry — 0. Then, Ve ro Ty T+ Gm + eniro 1 G18) G19) yt tnt ame which is simply the impedance seen at the source of a source follower, a predictable result because if Rp =, the cixcuit configuration isthe same as in Fig. 3.39(@). Second, let us replace Rp with an ideal current source, Equation (3.117) predicts that the input impedance approaches infinity. While somewhat surprising. this result can be explained with the aid of Fig. 3.54. Since the total current through the transistor is fixed and equal to /;, a change in the source potential cannot change the device current, and hence Jy = 0. In other words, the input impedance of a common-gate stage is relatively low only if the load impedance connected to the drain is small, Figure 3.54. Input resistance of a CG stage with ideal curent-source load > Example3.19 Calculate the voltage gain of a common-gate stage with a curret-source load [Fig 355(a)} Solution Letting Rp approach infinity in (3.111), we have Au = n+ &mi)ro 1 G20 Interestingly the gain does not depend on Rs. From our foregoing discussion, we recognize that if Rp > 00, 0 does the impedance seen a the source of My, andthe small-signal voltage at node X becomes equal to Vin. We can ‘herefore simply the circuit as shown in Fig. 3.55(b), oadily arriving at (3.120),Sec.3.5 Common-Gate Stage a Vout Figure 3.55 < Our analysis ofthe degenerated CS stage and the CG stage gives another interesting insight, As ilustrated in Fig 3.56, we lovely say tht a transistor transforms ils source resistance up and its drain resistance down (when seen atthe appropriate trina) Yoo 1+ tm + Got Rs 7! (9mm + Smb) Fo) Ro My ro My ke kh, = . A oro Tmt amare Figure 3.56 Impedance transformation by a MOSFET In order to calculate the output impedance of the common-gate stage, we use the circuit in Fig. 3.57 We note thatthe result is similar to that in Fig. 3.29, and hence Ro = {1+ Gm + &na)FolRs + ro)|IRD 121) Yoo Mx Figure 3.57 Calculation of ouput = resistance of a CG stage2 Chap. 3 Single-Stage Ampliiers > Example3.20 {As seen in Example 317, the input signal of a common-gate stage may bea current rather than a vltage, Shown in Fig. 3.58 such an arrangement Calcolte Voy /ig andthe ostpat impedance ofthe cc fhe inp curent source exhibits am ouput impedance equl to Rp Yoo Ro +Vout hee 7 OF Figure 3.58 Solution To ind Vous/Iin, We replace Iiy and Rp with a Thevenin equivalent and use (3.111) to write Vou (em + sus)ro +1 Tn TOF Gn + RnblrORe + Rp Ro RoRp Gm) ‘The output impedance is simply equal to Rea 1+ Go + gaadrolRe +r0)IRD 6.123) < 3.6 m Cascode Stage As mentioned in Example 3.17, the input signal of a common-gate stage may be a current. We also ‘know that a transistor in a common-source arrangement converts a voltage signal to a current signal. The cascade of a CS stage and a CG stage is called a “cascode topology, providing many useful properties, Figure 3.59 shows the basic configuration: Mf, generates a small-signal drain current proportional to the small-signal input voltage, Vj, and M; simply routes the current to Ria. We call M; the input device and ‘M; the cascode device. Note that in this example, M; and M; carry equal bias and signal currents. As we describe the attributes of the circuit inthis section, many advantages of the cascode topology over a simple common-source stage become evident. This circuit is also known as the “telescopic” cascode. z Figure 3.59 Cascode stage “The em cascode i believed tobe the atouyn for “cascade odes" possibly invented in vacuum tbe daysSec.3.6 Cascode Stage ‘Before delving into our analysis itis instructive to explore the citcuit qualitatively. We wish to know what happens ifthe value of Vi, of Vs changes by a small amount. Assume that hoth Wansistors are in saturation and 2 = y = 0. If Vip rises by AV, then Ip incteases by gyi AV. This change in current flows through the impedance seen at X,i.,the impedance seen atthe source of Mp, which is equal to 1/2. Thus, Vx falls by an amount given by gm: AV - (1/gqa) (Fig. 3.60(a)]. The change in Ip; also flows through Rp, producing drop of f91.4V Rp in Vay—Just a in a simple CS stage Yoo Yoo: Voo Ro a AVR a wettha” E sv Tate av pins x Law x > x| av TH, Yeim e & Figure 3.60 Cascode stage sensing a signal atthe gate of (a) an input device and (b) a cascode device. Now, consider the case where Vi, is fixed and ¥, increases by AV. Since Vos: is constant and rot = 00, we simplify the circuit as shown in Fig. 3.60(b). How do Vx and Vny; change here? As far as node X is concemed, M; operates as a source follower because it senses an input, AV, at its gate and generates an output at X. With 2. = y= 0, the small-signal voltage gain of the follower is equal to unity regardless of the value of Rp (why?). Thus, Vy rises by AV. On the other hand, Vjy) does nor change because Ip» is equal to Zp; and hence remains constant. We say that the voltage gain from Vs t0 Vir is zero in this case, Letus now study the bias conditions of the cascode, till assuming that 2 — y = 0. For M; to operate in saturation, we must have Vy > Vig — Vin If My and M, are both in saturation, Mz operates as a source follower and Vy is determined primarily by Vp: Vx = Vs— Vasx. Thus, Vp — Vas2 > Vie— Vr and hence Vs > Vin = Vr ig. 3.61). For Mz to be saturated, Vaus > Vi — Vruss that is, Vout > Vin = Vrats + Voss ~ Vea 6.124) (Was: ~ Vran) + Wose— Vr) .125) igure 3.61 Allowable voltages in cascode stagea4 Chap. 3 Single-Stage Amplifiers Af Vs is chosen to place My atthe edge of saturation, Consequently the minimum output level for which both transistors operate in saturation is equal tothe overdrive voltage of M; plus that of Mz. In other words, addition of M, to the circuit reduces the output voltage swing by atleast the overdrive voltage of ‘Mz, We say that Mz is “stacked” on top of M;. We also loosely say thatthe minimum output voltage is equal to two overdrives of 2V ‘We now analyze the large-signal bebavior ofthe cascode stage shown in Fig. 3.59 as Vi, goes from zer0 to Vp. For Vig = Vint. My and My are off, Vou = Vo, and Vx * Vb ~ Vr (if subthreshold conduction is neglected) (Fig. 3.62). As Viy exceeds Vrari, M; begins to draw current, and Vou drops. Since Ip» increases, Voss: must increase as well, causing Vx to fall. As Vjq assumes sufficiently large values, two effects can occur: (1) Vy drops below Vig by Vris. forcing My int the triode region; (2) Vow drops below Vj by Vrur, driving M, into the triode region, Depending on the device dimensions andthe values of Rp and Vj, one effect may occur before the other. For example, if Vis relatively low, My may enter the triode region first. Note that if M; goes into the deep triode region, Vy and Vj) become nearly equal Figure 5.62 tnpuourpat Vine Yin chacacerstic of acatcode stage ‘Let us now consider the small-signal characteristics ofa cascode stage, assuming that both transistors operate in saturation, If % = 0, the voltage gain is equal to that of a common-source stage because the drain current produced by the input device must flaw through the cascode device. Ilustrated in the equivalent circuit of Fig. 3.63, this result is independent of the transconductance and body effect of My Itcan also be verified using Ay = —GrpRow Figure 3.63 Small-sgnal equivalent circuit of cascode stage > Example3.21 Calculate the voltage gain ofthe circuit shown in Fig. 3.64 if 20, Solution The small-signal drain curent of Mj, fmt Vin is divided between Rp and the impedance seen looking ino the source of Ma, 1/(tm2 + mia). Ths, the current flowing through M, is 6.26Sec.3.6 Cascode Stage 35 Yop a Vout Voie Viso—Hfa ans FP Figure 3.64 ‘he vote gain is therefore even by snu(Sna ~ tuRe Ro 2 ae T Emir oe < Figure 3.65 Calculation of ep tesloanee of cascode tage Output Resistance An important property ofthe cascode structure isis high output impedance, As ilustated in Fig. 3.65, for ealeulaion of Roy the Nanomuter Design Note circuit canbe viewed a a comon-surce stage with degeneration itor yyy, jane ean feual to roy Thus, fom (3.66), ranomter cascode carer sources tre only moderato bt ban single Rey = + Gn + ButadrosTr01 + 02 (6.128) fansatorsThe fate shows the FV characteristic. of an NMOS. curtent Assuming gro > 1, we have Roy © (Gm2 + Snin)Foaror. That is, Mz soure before and afer cascoding (ray boosts the output impedance of My by a factor of (gm + fms2)Fo2-AS shown and Black curves, respectvely). Here, in Fig. 3.66, cascoding can be extended to three or more stacked devices W/L = 5 uMm/40 nm for both devices. te achive higher ep inpednce, ft the egued sdlienalvlage Me tone a Ve <2 he output impedance. Figure 3.66 Triple cascode86 Chap. 3. Single-Stage Amplifiers ‘headroom makes such configurations less attractive. For example, the minimum output voltage ofa triple cascode is equal to the sum of three overdrive voltages. To appreciate the utility of a high output impedance, recall from the lemma in Sec. 3.3.3 that the voltage gain can be written as —[Link]. Since Gy is typically determined by the uansconductance of a twansistor, e.., My in Fig. 359, and hence bears trade-offs with the bias current and device capacitances, it is desirable to increase the voltage gain by maximizing Ry). Shown in Fig. 3.67 is an example. If both M; and Mz operate in saturation, then Gy, * gm1 and Row * (Gqa + &nia)Fon¥o1. Yielding ‘Ac = (Sma + &ni2)¥o28mi¥o1- Thus, the maximum voltage gain is roughly equal to the square of the intrinsic gain of the transistors. > Example3.22 Calculate the exact voltage gain ofthe circuit shown in ig. 3.67 Yoo h Vout Vora ma Vine Ms Figure 3.67 Cascode stage = with eurtent-sousce load. Solution The actual Gy of the stage is slightly less than gy because a fraction ofthe small-signal curent produced by My is shunted (o ground by ror. As depicted in Fig. 3.68(a) we short the output node fo ac ground and recognize that the impedance seen looking into the source of My is equal 0 (1/(aha2 + smi2)lIrox. Thus, st = Gt Vig 6.129) ears ed Yoo 4 Vout Me Yee Tou “Smt F01 Vin © Figure 3.68Sec.3.6 Cascode Stage [follows tha the overall transconductance ie equal to Gig = —Sestoultoxtgma + mi) +1 6.20 Foiro2Gna* &min) +01 +03 and hence the voltage gain is given by VAvl = Gn Rows oe. = tmro1l ma + mba on +1 6.132) Ie we had assumed that Gy. ~ fut then [Aol © gull] + (td + Sméa)roalrot + ros) ‘Another approach to calculating the voltage gain sto replace Vjy and My by a Thevenin equivalent, reducing the cuit to a common-gate stage. ustrated in Fig. 3.68(b. this method in conjunction with (3.111) gives the same result as 8.132), < tis also interesting to compare the inerease inthe output impedance due to cascoding with that due to increasing the length of the input transistor for a given bias current (Fig. 3.69). Suppose, for example, that the length of the input transistor of a CS stage is quadrupled while the width remains constant. Then, since Ty = (1/2)f4nCos(W/L)(Ves — Vru)?, the overdsive voltage is doubled, and the transistor consumes the same amount of voltage headroom as does a cascode stage. That is, the circuits of Figs. 3.69(b) and. (©) impose equal voltage swing constraints, Yo to to Moz w w Vin BE Vin Ae at Vine” Ms my aint @ cy © Figure 3.69 Increasing output impedance by increasing the device length or cascoding. ‘Now consider the output impedance achieved in each case. Since [Ww 2inCox elo 8.133) foro = Ti and 2 0% 1/L, quadrupling L only doubles the value of gure while cascoding results in an output impedance of roughly gq. Note thatthe transconductance of My in Fig. 3.69(b) is half that in Fig. 369(0), degrading the performance. In other words, fr a given voltage headroom, the cascode structure provides a higher output impedance ‘A cascode structure need not operate as an amplifier. Another popular application ofthis topology isin building constant current sources, The high ontpat impedance yields a current source closer to the idea but atthe cost of voltage headroom. For example, current soure J in Fig. 367 can be implemented as a PMOS cascode (Fig. 3.70), exhibiting an impedance equal to (1 + (gms + Smbs)Toslro4 + Fos. We calculate the voltage gain with the aid of the lemma illustrated in Fig, 3.32. Wating Gy. ~ gai. we note that Ryu is now equal to the parallel combination of the NMOS cascode output impedance and the PMOS cascode output impedance Ro = (U1 + (Gna + Bmi2)roal¥ on + roa}|K(1 + (Gna + $miadFoalros + ros) 134) a7Chap. 3 Single-Stage Ampliiers Yoo My Cascode Current My; Source Figure 3.70 NMOS eascode amplifier = swith PMOS cascode load. ‘The gain is given by [AcI ~ fn1 Row For typical values, we approximate the voltage gain as Aol * Sual(8n2ro2¥01)| (usr osto4) 8.135) > Example3.23 How much voltage swing can the cascode amplifier of Fig. 3.70 support at the output? Solution Recall {rom Fig. 3.61 that Vii can be chosen low enough to place M; at the edge of saturation, Viy = Voss + (Vass ~ Vein), allowing a minimum value of (Vasa ~ Vru2) + (Vest ~ Vrin) for Vou. Similatly. Vig can be chosen high enough tobias My atthe edge of saturation: Vin + Vassl = Von — [Vast ~ Vr. This choice allows ‘maximum value of Yop ~ Voss — Vrial ~ (Wass ~ Vras| Tor Vou Thus, the toal allowable voltage swing at the output is equa to tomax ~ Voumin = Yop ~ Wasi ~ Veins) ~ Wasa ~ Vena) ~ Voss ~ Veal —IVoss ~ Vrusl 3.136) ‘We loosely say thatthe output swing is equal o Vip minus four overdives ot Vp, sa < We should caution the reader that the de value atthe output of the cascode amplifier shown in Fig. 3.70 is poorly defined because two possibly unequal high-impedance current sources are placed in series, (What happens if two unequal ideal current sources appear in series?) For this reason, the cizcuit must be biased in a negative-feedback loop. Poor Man's Cascode A “minimalist” cascode current source omits the bias voltage necessary for the cascode device, Shown in Fig. 3.71, this “poor man's cascode” places Mz in the wiode region because Vest > Vrs and Vos, = Vos ~ Vast < Vosa— Vio. In fact, if My and Ms have identical dimensions, it’can be proved that the structure is equivalent to single transistor having twice the length—not really cascode mr Ma Figure 3.71 Poor man's cascode,Sec.3.6 Cascode Stage In modern CMOS technologies, however, transistors with different threshold voltages are available, allowing Mz to operate in saturation if M; has a lower threshold than Mz. For example, if Vrir2 — Vretu 150 mV and if Vos; ~ Vrary < 100 mY, then My is saturated and the circuit acts as a tue cascode. Shielding Property | Recall from Fig. 3.30 that the high output impedance arises from the fact that ifthe output-node voltage is changed by AV, the resulting change atthe source of the eascode device is much less. In a sense, the cascode transistor “shields” the input device from voltage variations at the output ‘The shielding property of cascodes proves useful in many circuits. > Example: 24 Two identical NMOS transistors ar ured as constant current sources in a system [Fig.3.72(2)]. However, dus to the intemal cizcuity ofthe system, Vy is higher than Vy by AV. (a) Calculate the resulting difference between Tp and Ip if #0, (@) Add cascode devices to My and Mz and repeat par (3) Analog ‘System Analog * y ‘System or Yo x Y Yea Ios Woo ms|P malo Ms Yor m] om my] ma, @ cy Figure 3.72 Solution (@) We have Ww, . fat — Io = 5 inCon PVs — Ven Visi — 2V ns x Ip ~ Ios = 5HtnCon Ps — Vr) OVos: V8) 6.37) Leo Mi — ven 2G@aV Fie Cor Mb — Vrw PGA) 6.38) () As shown in Fig, 3.72(b), cascoding reduces the elect of Vx and Vy upon Jp; and Ip, respectively. At ‘depicted in Fig, 3.30 an implied by Bq, (3.69), a difference AV between Vx and Vy translates toaditference AVeg ‘between P and equal to AVpg = AV" 3.139 2 = SVT east bnislrosPor Fron eee av — 6.140 Gat enon a Low y_aav Boy = tn = Hainoc (V5 = Ven)? 2 __ 3.4 ginon 7 ” Gm + fanror ou In other words, cascoding reduces the mismatch between pi and Ip by a factor of (gyms + gs)¥03 <20 [Nanometer Design Notes Let us implement a cascode stage with (WY/Luwos = 10 umia0 nm, (W/L) pmos = 20 pmi40 nm, and Ip (0.3 mA. The figure pots the input-output characteristic of the cicut, displayng roniinearly at the extromes of Voy. How do we quanity this nontinearity? We can say thatthe output swing ehould not cause, say, more than @ 20% drop Inthe small-signal voage gan, Plating ‘he derivative of the characters inthe figure, we observe that the allowable single-ended peak-to-peak output swing Is about 0.5 V if the gain must remain greater than 10. We also note thatthe ‘ain is fairly low, dictating longer PMOS dovices ita higher gains necessary. Vine — ‘OnsVin @ Chap. 3 Single-Stage Ampliiers ‘The shielding property of cascodes diminishes if the cascode device enters, the triode region. To understand why, let us consider the circuit in Fig. 3.73, assuming that Vy decreases ftom a large positive value. As Vy falls below Vin — Vrarn, Mz enters the tiode region and requires a greater gate-source overdrive so as to sustain the current drawn by M. We can write 1 w ' Ton = 5HtnCon (3) [2(Via — Vp — Vena) (Vx — Ve) — (Wx — Ve)" “ 3.142) ‘concluding that as Vy decreases, Vp also drops, so that Zp: remains constant. In other words, variation of Vy is less attenuated as it appears at P. If Vy falls sufficiently, Vp goes below V1 — Vrin, driving M; into the triode region. Figure 3.73 Output swing of ‘cascode sage 3.6.1 Folded Cascode “The idea behind the cascode structure isto conver the input vollage to acurtent and apply the result to @ common-gate stage. However, the input device and the cascode device need not be of the same type. For example, as depicted in Fig.374(a), a PMOS-NMOS combination performs the same function. In order to bias M; and M;, a current source must be added as in Fig. 3.74(b. Note that [fo + Zoo is equal to J; and hence constant. The small-signal ‘operations as follows. If Vj, becomes more positive, [/p| decreases, forcing ps toincrease and hence Vin to drop. The voltage gain and outputimpedance ofthe circuit can be obtained as calculated for the NMOS-NMOS cascode of Fig. 3.59. Shown in Fig. 3.74(c) is an NMOS-PMOS cascode. The advantages and disadvantages of these types will be explained Inter. Yoo Yeo Yoo Ro Ro 4 Vor Vine Vout Ma a Kos Vinten, Sf ove x Vout @" Ro © © Figure 3.74. (2 Simple folded cascode; (b folded cascode with prope biasing; (c) folded cascode with NMOS inputSec.3.6 Cascode Stage ‘The structures of Figs. 3.74(b) and (c) are called “folded cascode” stages because the small-signal ‘current is “folded” up [in Fig. 3.74(b)] or down {in Fig. 3.74(c)]. We should mention as a point of contrast that the bias current of M; in Fig. 3.70 flows through Mz, ic., itis “reused,” whereas those of My and Mz in Fig. 3.74(b) add up to 1). Thus, the total bias current in this case must be higher than that in Fig. 3.70 to achieve a comparable performance. Icis instructive to examine the large-signal behavior of a folded-cascode stage. Suppose that in Fig. 3.74(b), Viz decreases from Vpp to zero. For Vin > Vop — |Vrinil. Mi is off and M, carries all of /.? yielding Vie = Voo — AWRp. For Vig < Voo — |Vrizil, Mi tums on in saturation, giving 1 w > Tox = hh = 5 H4pCox (3) (op — Vin = [Wran* 6.143) As Vin drops, Ipz decreases further, falling to zero if Ip) = Ty. This occurs at Vix = Viet if 1 w 2 5H Con (), Won — Vin ~ [Vem 144) ‘Thus, 2h \ COD Vint = Vow — [Vranl 3.145) If Vip falls below this level, py tends to be greater than /;, and M; enters the triode region so as to ensure Ip = 1h. The result is plotted in Fig. 3.75. The reader is encouraged to determine the input voltage at which pi! = Io Vout h 4 Voo| Vos! oa Vop ~ Rola |--- Vir Voo—IVrnil Vin Vint Voo =I Vin Figure 3.75. Large-signal characteristics of folded cascode, What happens to Vx in the above test? As Inn drops, Vx rises, eaching Vs — Vriz for Ip: = 0. As ‘M, enters the triode region, Vx approaches Vo > Example3.25 Calculate the output impedance of the folded cascode shown in Fig, 3.76(2), where My operates as the bias current Sotution Using the simplified model in Fig. 3.76(b) and Eq, (3.66), we have. Rout = (+ (m2 + Smb2)Vo2l(rorliro3) +02 6.46) TIFT; is exceasively age, M, any eter the deep ode region, possibly driving 1 int the tode region at wel 192 Chap. 3. Single-Stage Ampliiers pe Ma gl Vo Mall Vo VosefeMs r|Fo2 @ © Figure 3.76 ‘Thus, the circuit exhibits an output impedance lower than that of a nonfolded (also called “telescopic") cascode < In order to achieve a high voltage gain, the load of a folded cascode can be implemented as a cascode itself (Fig. 3.77). This structure is studied more extensively in Chapter 9. Figure 3.77. Folded cascode with cascode load ‘Throughout this chapter, we have attempted to increase the output resistance of voltage amplifiers so as to obtain a high gain. This may scem to make the speed of the circuit quite susceptible to the load capacitance. However, as explained in Chapter 8, a high output impedance per se does not pose a serious issue if the amplifier is placed in a proper feedback loop, 3.7 m Choice of Device Models In this chapter, we have developed various expressions for the properties of single-stage amplifiers, Forexample, the voltage gain of adegenerated common-source stage can be as simple as —Ry/(Rs-+8!) for as complex as Eq. (3.77). How does one choose a sufficiently accurate device model or expression? The proper choice is not always straightforward, and making it is a skill gained through practice, expetience, and intuition. However, some general principles in choosing the model for each transistor can be followed. Fist, break the cigcuit down into a number of familiar topologies. Next, concentrate fon each subeizcuit and use the simplest transistor model (a single voltage-dependent current source forProblems. FETs operating in saturation) for all wansistors. I the drain of a device is connected to a high impedance (eg. the drain of another), then add ro ( its model. At this point, the basic properties of most circuits ‘can be determined by inspection. In a second, more accurate iteration, the body effect of devices whose source or bulk is not at ac ground can be included as wel. For bias calculations, it is usually adequate to neglect channel-length modulation and body effect in the first pass. These effects do introduce some error, but they can be included in the next iteration step—after the basic properties are understood. In today’s analog design, simulation of circuits is essential because the behavior of short-channel MOSFETs cannot be predicted accurately by hand calculations, Nonetheless, if the designer avoids a simple and intuitive analysis ofthe circuit and hence skips the task of gaining insight, then helshe cannot interpret the simulation results intelligently. For this reason, we say, “Don’t let the computer think for you.” Some say, “Don’t be « SPICE monkey.” Unless otherwise stated, in the following problems. use the device data shown in Table 2.1 and assume that Vop =3V where necessary. All device dimensions ate effective values and in microns, 3. For the circuit of Fig, 3.13, caleuate the small-signal voltage gain if (W/L), = $0/0,5. (W/L): = 10/05, and Ip = Ip2 = 0.5 mA. What is the gain if Mz is implemented as a diode-connected PMOS device Fig. 3.16)? 32, Inthe circuit of Fig. 3.18, assume that (W/L) both devices are in saturation, Recall that. 1/L. {a) Calculate the small-signal voltage gain (b) Calculate the maximum output voltage swing while oth devices aze saturated, 33. Inthe circuit of Fig. 3.4(a, assume that (W/L), = 50/05, Rp = 22 and 3. (a) Whats the small-signal gan if My isin saturation and Ip = 1 mA? (b) What input voltage places M; atthe edge ofthe triode region? What isthe small-signal gain under this condition? (©) What input voltage drives My into the wiode region by $0 mV? What is the small-signal gain under this, coniltion? 0.5 mA when 0/0.5, (W/L )a 10/2, and Toy = Ibs 3A, Suppose the common-source stage of Fig. 3.4(a isto provide an output swing from I V to 2.5 V, Assume that (W/L); = 50/0.5, Rp = 20, and d = 0. {a) Calculate the input voltages that yield Voar = 1 V and Vour = 2.5 V. (b) Calculate the drain current and the transconductance of Mj for both cases. {€) How much does the small-signal gain, gm Rp, vary as the output goes from 1 V (o 2.5 V? (Vatiation of smallsignal gsin can be viewed as nonineatity) 35. Calculate the intrinsic gan of an NMOS device and a PMOS device operatingin saturation with W/L. and [Ip] = 0.5 mA. Repeat these calculations if W/L = 100/1. 3.6. Assuming a constant L, plot the ininsic gain of a sauated device versus the gate-source voltage if (a) the Grain curent is constant, (b) W is constant. 0/05 37. Assuming aconstant £, plot the invinsic gain ofa saturated device versus W/Z. iC (a) the gate-source voltage is constant, (b) the drain curent is constant 3.8, An NMOS transistor with W/L = 50/0.5 is biased with Vo = 41.2 Vand Vs varied from 0 t0 3 V. (2) Assuming the bulk voltage is zero, plot the intrinsic gain versus Vos. (by Repeat part (a) fr a bulk vltage of —1 V. 39. For an NMOS device operating in saturation, plot gm, 70, and gmro 2s the bulk voltage goes from 0 0 ~0 ‘while other terminal voltages remain constaat. 0. The dean voltage is