Atmega328p

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Introduction to Atmega328p
• The Atmega328 is a very commonly used microcontroller board created by the Atmel. It can
support data up to eight bits and has a flash memory of thirty two-kilo bytes.
• This module also comprises of one kilobyte of EEPROM and two-kilo byte of inner static

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random access memory.
• Like Arduino, UNO atmega328 is also used with the Arduino Duemilanove board.
• There is a twenty-eight pinouts of atmega328.
• The voltage over which it operates is 3.3 volts to 5.5 volts, Usually, five volts are given to it.
• The most common features it provides are less price, less power usage, and has a real-time

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counter with the separate oscillators
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Features of Atmega328p
• There are twenty-eight pinouts on this module
• It has a central processing unit of RISC based on an eight-bit AVR (Automatic Voltage
Regulator).
• It has a ten-bit analog to digital converter.
• It has a flash memory of its two kilobytes.

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• It has a static ram of 2048 bytes.
• It has an EEPROM of 10244 bytes.
• There is eight analogs to digital converter channels it has.

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• There is six pulse width modulation pinout it has.
• It consists of one comparator.
• The voltage range over which it works is 1.8 volts to 5.5 volts.
Pinout of Atmega328p
• There are twenty-eight pinouts exits in the Atmega328.
• There are twenty pinouts of this module that operate as input and outputs.
• Fourteen input operates as digital pins six of them are pulse width modulation output
and six are of analog inputs and outputs.
• On the chip of this controller, ADC (Analog-to-Digital Converter) is already built. There

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are three pinouts Avcc(Voltage Common Collector for A/D Converter) , AREF(Analog
REFerence), GND, and AVcc are used for ADC operation.
• Analog to digital converter needed separate power supply.
• There are two pins are used as a crystal oscillator. These pins used to deliver a clock to
the atmega.
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• The pinouts VCC and GND are used to provides power to the module. The required
voltage for this module is 1.8 volts to 5.5 volts.
• Its GND is the ground terminal. AREF is a reference voltage that is used by analog to
digital converter for its resultant digital values.
Atmega328P Pinout:

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 Pin
pin Pin Function Pin Function Description
Description
1 PC6 Reset When this reset pin goes low the microcontroller & its program gets reset.
2 PD0 Digital Pin (RX- Input pin for serial communication
Reciever)
3 PD1 Digital Pin (TX- Output pin for serial communication
Translation)

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4 PD2 Digital Pin Pin 4 is used as an external interrupt 0
5 PD3 Digital Pin (PWM) Pin 5 is used as an external interrupt 1
6 PD4 Digital Pin Pin 6 is used for external counter source Timer0
7 Vcc Positive Voltage Positive supply of the system.
8 GND Ground Ground of the system
9

10

11
XTAL

XTAL

PD5
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Crystal Oscillator

Crystal Oscillator

Digital Pin (PWM-

This pin should be connected to one pin of the crystal oscillator to provide
external clock pulse to the chip
This pin should also be connected to another pin of the crystal oscillator to
provide external clock pulse to the chip
Pin 11 is used for external counter source Timer1
Pulse Width
Modulation)
12 PD6 Digital Pin (PWM) Positive Analog Comparator i/ps
 Pin
pin Pin Function Pin Function Description
Description
13 PD7 Digital Pin Negative Analog Comparator i/ps
14 PB0 Digital Pin Counter or Timer input source
15 PB1 Digital Pin counter or timer compare match A.
(PWM)
16 PB2 Digital Pin This pin is act as a slave choice i/p.

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(PWM)
17 PB3 Digital Pin This pin is used as a master data output and slave data input for SPI.
(PWM)
18 PB4 Digital Pin This pin is act as a master clock input and slave clock output.
19 PB5 Digital Pin This pin is act as a master clock output and slave clock input for SPI.
20
21

22
23
AVcc
AREF

GND
PC0
Analog
Reference
Ground
Analog Input
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Positive Voltage Positive voltage for ADC (power)
Analog Reference voltage for ADC (Analog to Digital Converter)

Ground of the system

Analog input digital value channel 0
24 PC1 Analog Input Analog input digital value channel 1
 Pin
pin Pin Function Pin Function Description
Description
25 PC2 Analog Input Analog input digital value channel 2
26 PC3 Analog Input Analog input digital value channel 3
27 PC4 Analog Input Analog input digital value channel 4. This pin can also be used as serial interface
connection for data.
28 PC5 Analog Input Analog input digital value channel 5. This pin also used as serial interface clock

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line.

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ATmega328p Architecture
In the below figure you can see the architecture of Atmega328 which described the complete internal
structure of the controller.

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A watchdog timer (WDT) is a timer that monitors microcontroller (MCU) programs to see if they are out of control or
have stopped operating.
A bandgap voltage reference is a temperature independent voltage reference circuit widely used in integrated circuits.
It produces a fixed (constant) voltage regardless of power supply variations, temperature changes, or circuit loading
from a device
Serial Peripheral Interface (SPI) is a synchronous serial data protocol used by microcontrollers for communicating
with one or more peripheral devices quickly over short distances

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The Two-Wire Interface (TWI) is similar to the I2C (Inter-integrated Circuit)interface with a few differences. The TWI
peripheral provides an interface to components on a unique two-wire bus, consisting of one clock line and one data line.
The TWI can be used with I²C compatible devices, such as a Real-Time Clock (RTC), memories, and sensors.
USART: A universal synchronous and asynchronous receiver-transmitter (USART) is a type of a serial interface device
that can be programmed to communicate asynchronously or synchronously

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POR/BOD:The PoR (power-on reset) system ensures that the microprocessor or microcontroller will start in the same
condition every time that it is powered up.
Many AVR® devices have an on-chip Brown-out Detection (BOD) circuit for monitoring the Operating Voltage (VCC) level
during operation.
debugWIRE: By using debugWIRE one has full read and write access to all memory and full control over the execution
flow
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which
input voltage is higher.
Memory Segmentation
• The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space.
• The AVR( Automatic Voltage Regulator /Alf and Vegard's RISC processor) core combines a rich instruction
set with 32 general purpose working registers.
• All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle.
• The resulting architecture is more code efficient while achieving throughputs up to ten times faster than

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conventional CISC microcontrollers.
• The ATmega328p provides the following features: 32K bytes of In- System Programmable Flash with Read-
While-Write capabilities, 1K bytes EEPROM, 2K bytes SRAM, 23 general purpose I/O lines, 32 general
purpose working registers, three flexible Timer/Counters with compare modes, internal and external
interrupts, a serial programmable USART (Universal Synchronous Asynchronous Receiver Transmitter), a

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byte-oriented 2-wire Serial Interface, an SPI (Serial peripheral interface) serial port, a 6-channel 10-bit ADC
a programmable Watchdog Timer with internal Oscillator, and five software selectable power saving modes.
• The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, USART, 2-wire Serial Interface, SPI
port, and interrupt system to continue functioning.
• The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip
functions until the next interrupt or hardware reset.
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The five different addressing modes for the data memory cover:
• Direct
– The direct addressing reaches the entire data space.
• Indirect with Displacement
– The indirect with displacement mode reaches 63 address locations from the base address
given by the Y- or Z-register.

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• Indirect
– In the register file, registers R26 to R31 feature the indirect addressing pointer registers.
• Indirect with Pre-decrement
– The address registers X, Y, and Z are decremented.
• Indirect with Post-increment

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– The address registers X, Y, and Z are incremented.
The 32 general purpose working registers, 64 I/O registers, 160 extended I/O registers, and the 2K bytes
of internal data SRAM in the device are all accessible through all these addressing modes.
In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while
the rest of the device is sleeping.
• The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to
minimize switching noise during ADC conversions.
• In Standby mode, the Oscillator is running while the rest of the device is sleeping.
• This allows very fast start-up combined with low power consumption.
• The device is manufactured using Atmel’s high density non-volatile memory technology.

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• The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial
interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on
the AVR core.
• The Boot program can use any interface to download the application program in the Application Flash
memory.

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• Software in the Boot Flash section will continue to run while the Application Flash section is updated,
providing true Read-While-Write operation.
• By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel
ATmega328P is a powerful microcontroller that provides a highly flexible and cost effective solution to many
embedded control applications.
• The ATmega328P AVR is supported with a full suite of program and system development tools including: C
Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.
I/O Ports
When used with an external clock, the ATmega328P has 21 pins that can be configured for general
purpose I/O.
Many of these can also be used for other purposes such as analog-to-digital conversion, timers, etc.
All the I/O port bits are capable of sourcing or sinking current to drive higher-current devices like LEDs.
For each port there are three registers that control the actions of the individual bits of the port:

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1) Data Direction Register (DDRx) - These registers determine whether the pins for that port are serving as
inputs or outputs. Initially, or upon a reset signal, the bits in the DDRs are all zero which makes the
corresponding I/O port bits inputs. To use a I/O port bit as an output, the corresponding bit in the DDR
must be set to a one.
2) Port Output Register (PORTx) - When an I/O bit is configured as an output the corresponding bit in the

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PORTx register control the state of the output. If the bit is a one, the output line will go high. If the bit is a
zero, the output line will go low. When an I/O bit is configured as in input, the bits in the PORTx register
determine whether the internal pull-up resister is enabled. Writing a one to a bit in PORTx register turns on
the corresponding pull-up resistor, and writing a zero turns it off.
3) Port Input Register (PINx) - The PINx registers are read-only registers and are used when the pin is
configured to be an input. The value of the bit in the register indicates the logic level on the corresponding
pin. If the pin is in the high state the value in the register is a one. If the pin is in the low state the value is a
zero.
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State of port bits when changing between input and output

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Port B (PB)
Port B on the ATmega328P has seven usable pins (PB0 through PB5 and PB7). A eighth bit, PB6, shares
a pin with the XTAL1 input. If the chip is configured for an external clock, this pin is not available for I/O.
Three of the pins (PB3, PB4 and PB5) are use for the SPI interface for programming the Flash memory.
These pins should not be used as inputs connected to sources that will continue to drive signals at the 328P
while in the reset state.

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Port C (PC)
Port C on the 328P has six pins (PC0 through PC5). A seventh bit, PC6, shares a pin with the RESET
input. By changing the configuration fuse settings this bit can be use for I/O. Most of the pins in PC are
shared with the analog-to-digital converter so if the ADC function is used one or more pins will not be
available for general purpose I/O. In addition, PC4 and PC5 are use for the I2C interface and will not be

Port D (PD)
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available for general I/O if I2C is used.

Port D on the 328P has eight pins (PD0 through PD7). Two of the pins, PD0 and PD1, are shared with
the serial communications interface and can not be used as I/O if the USART0 functions are used.
ATmega328p Applications
• The complete structure including Arduino and Atmgega328p is used in different applications.
• It used in different types of projects such as mobile embedded systems it prefers here due to
operation at different values of power operation
• As it comes with the high-level RISC structures, applied in applications where high-speed
application of programing exit

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• It helps to process digital data.
• It used in different controlling devices that are based on automation like machines.
• To design a small size plan and quadcopter this controller is used.

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Instruction Set
Instruction set of ATmega328P is categorised as follows
• opcodes
• data types
• addressing modes

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30 Opcodes
a) ALU instructions: ADC, ADD, AND, NOP, CP, EOR, OR, MOV

ADC: Adds two registers and the contents of the C Flag and places the result in the destination register Rd.
ADC Rd,Rr (Rd ← Rd + Rr + C )

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ADD: Adds two registers without the C Flag and places the result in the destination register Rd.
ADD Rd,Rr(Rd ← Rd + Rr)
AND: Performs the logical AND between the contents of register Rd and register Rr, and places the result in
the destination register Rd
AND Rd,Rr(Rd ← Rd • Rr)
NOP: This instruction performs a single cycle No Operation.
NOP(No)
CP: This instruction performs a compare between two registers Rd and Rr. None of the registers are
changed. All conditional branches can be used after this instruction.
CP Rd,Rr(Rd - Rr)
EOR: Performs the logical EOR(Exclusive OR) between the contents of register Rd and register Rr and places
the result in the destination register Rd.
EOR Rd,Rr(Rd ← Rd ⊕ Rr)
OR: Performs the logical OR between the contents of register Rd and register Rr, and places the result in

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the destination register Rd.
OR Rd,Rr(Rd ← Rd v Rr)
MOV: This instruction makes a copy of one register into another. The source register Rr is left unchanged,
while the destination register Rd is loaded with a copy of Rr.
MOV Rd,Rr(Rd ← Rr)

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b) Immediate instructions: CPI, ORI, ANDI, LDI
CPI: This instruction performs a compare between register Rd and a constant. The register is not changed.
All conditional branches can be used after this instruction.
CPI Rd,K(Rd - K)
ORI: Performs the logical OR between the contents of register Rd and a constant, and places the result in
the destination register Rd.
ORI Rd,K() Rd ← Rd v K
ANDI: Performs the logical AND between the contents of register Rd and a constant, and places the result
in the destination register Rd.
ANDI Rd,K(Rd ← Rd • K)
LDI: Loads an 8-bit constant directly to register 16 to 31.

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LDI Rd,K(Rd ← K)

c) Unary Logical instructions: COM, NEG, ASR, LSR

COM: This instruction performs a One’s Complement of register Rd.
COM Rd

NEG Rd M
NEG: Replaces the contents of register Rd with its two’s complement.

ASR: Shifts all bits in Rd one place to the right. Bit 7 is held constant. Bit 0 is loaded into the C Flag of the
SREG. This operation effectively divides a signed value by two without changing its sign. The Carry Flag can
be used to round the result.
ASR Rd
LSR: Shifts all bits in Rd one place to the right. Bit 7 is cleared. Bit 0 is loaded into the C Flag of the SREG.
This operation effectively divides an unsigned value by two. The C Flag can be used to round the result.
LSR Rd 0 → b7 - - - - - - - - - - - - - - - - - - b0 → C

d) Load/Store instructions: LDS, STS

LDS: Loads one byte from the data space to a register.

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LDS Rd,k(Rd ← (k))
STS: Stores one byte from a Register to the data space.
STS k,Rr((k) ← R)

e) Branch instructions: BRBS, BRBC (aka BRZS, BRZC, BRCS, BRCC)

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BRBS: Branch if Bit in SREG is Set. Conditional relative branch. Tests a single bit in SREG and branches
relatively to PC if the bit is set.
BRBS s,k(If SREG(s) = 1 then PC ← PC + k + 1, else PC ← PC + 1 )
BRBC: Branch if Carry Cleared. Conditional relative branch. Tests the Carry (C) flag and branches relatively
to the PC if C is cleared.
BRBC s,k(If C == 0 then PC ← PC + k + 1, else PC ← PC + 1)
Conditional branch based upon SREG bits (“Condition Codes”)
f) Input/Output instructions: IN, OUT
IN: Loads data from the I/O Space (Ports, Timers, Configuration Registers, etc.) into register Rd in the
Register File.
IN Rd,A(Rd ← I/O(A))
OUT: Stores data from register Rr in the Register File to I/O Space (Ports, Timers, Configuration Registers,

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etc.).
OUT A,Rr(I/O(A) ← Rr)

g) Call/Jump instructions: CALL, JMP

CALL: Calls to a subroutine within the entire Program memory. The return address (to the instruction after

CALL k(PC ← k ) M
the CALL) will be stored onto the Stack. (See also RCALL). The Stack Pointer uses a post-decrement scheme
during CALL. This instruction is not available in all devices as it is device specific instruction

JMP: Jump to an address within the entire Program memory. (See also RJMP). This instruction is not
available in all devices as it is device specific instruction
JMP k(PC ← k)
 h) Return instructions: RET, RETI
RET: Returns from subroutine. The return address is loaded from the STACK. The Stack Pointer uses a pre-
increment scheme during RET.
RET(PC(15:0) ← STACK)
RETI: Returns from interrupt. The return address is loaded from the STACK and the Global Interrupt Flag is
set.

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i) Stack instructions: PUSH, POP
PUSH: This instruction stores the contents of register Rr on the STACK. The Stack Pointer is post-
decremented by 1 after the PUSH. This instruction is not available in all devices as it is device specific
instruction
PUSH Rr(STACK ← Rr)

POP Rd(Rd ← STACK) M

POP: This instruction loads register Rd with a byte from the STACK. The Stack Pointer is pre-incremented by
1 before the POP. This instruction is not available in all devices as it is device specific instruction

j) Relative Jump instructions: RCALL, RJMP

RCALL: Relative call to an address within PC - 2K + 1 and PC + 2K (words). The return address (the instruction
after the RCALL) is stored onto the Stack.
RCALL k(PC ← PC + k + 1)
RJMP: Relative jump to an address within PC - 2K +1 and PC + 2K (words)
RJMP(PC ← PC + k + 1)
Addressing Modes
– Specify how the location of an operand is resolved
– non-memory addresses: immediate, register direct, etc.
– memory addresses: data direct, data indirect, data indirect with displacement, etc

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Instruction Set Summary

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