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VLSI Design Concepts and Techniques

This document contains questions about VLSI design concepts including propagation delay calculations for NMOS inverters, scaling factors, DRAM cell operation, lookup tables (LUTs) and FPGA architecture, controllability and observability, fault testing strategies, multiple choice questions on PLD and FPGA technologies, and fill in the blank questions related to multiplier design, PLA structure, LUT implementation, observability, PLA logic implementation, testing faults, CMOS logic behavior, and parity generator cells. It covers a wide range of topics in VLSI design from basic transistor characteristics and circuit design to programmable logic and testing techniques.

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mohan
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42 views3 pages

VLSI Design Concepts and Techniques

This document contains questions about VLSI design concepts including propagation delay calculations for NMOS inverters, scaling factors, DRAM cell operation, lookup tables (LUTs) and FPGA architecture, controllability and observability, fault testing strategies, multiple choice questions on PLD and FPGA technologies, and fill in the blank questions related to multiplier design, PLA structure, LUT implementation, observability, PLA logic implementation, testing faults, CMOS logic behavior, and parity generator cells. It covers a wide range of topics in VLSI design from basic transistor characteristics and circuit design to programmable logic and testing techniques.

Uploaded by

mohan
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

VLSI Design descriptive paper ece 3-2

1. a) Derive the propagation delay for NMOS inverter?

b) Determine the scaling factors of the following: (i) switching energy per gate (ii) channel resistance (iii)
Carrier density in channel (iv) Speed power product

2. a) Draw the circuit diagram of DRAM cell and explain its working.

b) Implement Static CMOS full adder.

3. a) What is LUT? Explain how an NAND gate is implemented using LUT?

b) Draw the block Diagram of FPGA and compare CPLD and FPGA.

4. a) What do you mean by Controllability and Observability? Write about Stuck Open ad Stuck Short
faults.

b) What is the need for Testing? Explain Design strategies for Test.

Multiple Choice

1. Adder using ____ technology can be used for speed improvement [ ]


a) CMOS
b) BiCMOS
c) nMOS
d) pMOS

2. Partitioning into subsystems are done at [ ]


a) design stage
b) prototype stage
c) testing stage
d) fabrication stage

3. Outputs of the AND gate in PLD is known as ____________ [ ]


a) Input lines
b) Output lines
c) Strobe lines
d) Control lines

4. The complex programmable logic device contains several PLD blocks and __________ [ ]
a) A language compiler
b) AND/OR arrays
c) Global interconnection matrix
d) Field-programmable switches

5. In negative logic convention, the true state is represented as: [ ]


a) 1
b) 0
c) -1
d) -0

6. Most FPGA logic modules utilize a ________ approach to create the desired logic functions. [ ]

a) AND array
b) Look‐up table
c) OR array
d) AND and OR array

7. EEPROM refers to ____________ [ ]


a) Electrically Erasable Programable Read Only Memory
b) Electronic Erasable Programable Read Only Memory
c) Electronic Erasable Programmed Read Only Memory
d) Electrically Erasable Programmed Read Only Memory

8. For programmable logic functions, which type of PLD should be used? [ ]


a) PLA
b) PAL
c) CPLD
d) SLD

 9. UV erasable memories are [ ]

a) PROM

b) EPROM

c) EEPROM

d) FLASH memory

10. Which design is preferred in n-bit adder? [ ]


a) many pass transistors in series
b) many pass transistors with suitable buffer
c) many pass transistors without suitable buffer
d) many pass transistors in parallel
Fill in the blanks

1. VLSI design of multiplier element basically requires _____


2. The general arrangement of PLA is_____
3. The lookup tables are part of ________
4. Being able to read out the result of the state changes as they occur is called_____
5. The PLA provides a systematic and regular way of implementing multiple output functions of n
variables in_____
6. Ability to control a node is called Controllability/Observability________
7. In nMOS logic circuit __________ is used as Load
8. For a four bit word, a one-bit shift left is equivalent to a_____
9. When both nMOS and pMOS transistors of CMOS logic gates are ON, the output is_____
10. The standard cell for an n-bit parity generator is_____

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