Introduction to
CMOS VLSI
Design
VLSI Circuit Layout:
Standard Cells
Peter Kogge
University of Notre Dame
Fall 2015, 2018
Based on material from
Prof. Jay Brockman, Joseph Nahas, University of Notre Dame
Prof. David Harris, Harvey Mudd College
[Link]
Outline
Design Rule Review
Layout Styles
Standard Cell Layouts
Wiring Tracks
Stick Diagrams
Euler Paths
Tracks and Spacing's
Area Estimation
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Audience Review Questions
What is a “Design Rule”?
What is “λ”?
Why is this a useful unit of measure?
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Design Rules from Ed. 3’s Back Cover
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A Conservative Set of Simpler Rules
Audience Question: Why are we using 4λ here, vs 3λ from rules
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Layout Styles
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Layout Styles
Custom
– Random transistor and other component positioning and
wiring.
Standard Cell
– Logic gates “pre-designed”
• Power rails (Vdd and Vss) on top and bottom
• Common N and P wells
– PMOS transistors on top
– NMOS transistors on bottom
– Gates wired together automatically using Place and Route tool.
Pitch-Matched Data Path
– Custom or automatic layout of logic in data channels.
• Typically 8, 16, 32, or 64 bits wide.
– Channels match each-other and mesh.
Memory will be discussed later
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Layout Styles:
An ND 12 bit Processor
standard
cell
Cells
datapath
Wiring
Channel
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Stick Figure Construction
Draw horizontal wires as follows
– Metal1 (blue) for Vdd on top
– Metal1 (blue) for gnd at bottom
– Diffusion for ptype just below Vdd
– Alternative: use green with a yellow box
– Diffusion for ntype just above Gnd
– Metal2 for longer range wires
Draw vertical poly for each gate input
Select which input corresponds to each vertical
– “Euler’s Algorithm” later on will tell us this
Determine how/where to wire or X
– Connections to Vdd/gnd
– Connections from p to n types
With “luck” you don’t have to “break” the diffusion
Key parameter to estimate from this: How “wide” is circuit?
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Stick Diagrams
Stick diagrams help plan layout quickly
– Need not be to scale
– Draw with color pencils or dry-erase markers
– Relative position of key components
What type of gates are these?
What are the widths of the nmos and pmos transistors?
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Alternative Invertor Circuit
Layouts (Single Well)
Vdd X
Vdd
X X X
A X Y A X Y
X X X
Gnd
Gnd X
(Ignore Substrate Taps for Now)
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Repetitive Custom Layout of
Ring Oscillator
Vdd
X X X X X X
X X X X X
X X X X X X
Gnd
X X
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Standardizing the Invertor
Standard Height
Vdd
Vdd and Ground match up
I/O Come down from M2 to
Wiring Bays below cell
Width can vary
Gnd
Out
In
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Standard Cell Layout of Ring
Oscillator
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Aside: Optimized Custom
Layout of Ring Oscillator
Vdd
X X X X X
Note internal wiring
X X
X X X X
X X X X X
Gnd
X X
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Complex Circuit Layouts
C (A+B) + AB
Single diffusion runs Multiple Diffusion runs
Can you draw the transistor diagram?
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Standard Cell Layout
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Gate Layout
Standard cell design methodology
– VDD and GND should be some standard height & parallel
– Within cell, all pMOS in top half and all nMOS in bottom half
– Preferred practice: diffusion for all transistors in a row
• With poly vertical
– All gates include well and substrate contacts
Multi-gate circuits constructed by “snapping” gates together
– If two standard cells abut, Vdd & GND “snap together”
– Adjacent gates must still satisfy design rules at boundaries
Bigger circuits constructed by rows of such multi-gates
– With “routing channels” between them for wiring
• Typically using 2 levels of metal
– And “flips” to align Vdd and Gnd
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Standard Cell Layout
Bus connects to
VDD Bus neighboring cells
Standard Height n well Well connects to
pmos transistors neighboring cells
Internal Gate Wiring
And Gate I/O contacts
nmos transistors Well connects to
p well neighboring cells
Bus connects to
VSS Bus
neighboring cells
Variable Width
Audience Question: Why is “connecting to neighbors” a good thing?
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Inverter Layout
NOT to scale!
In Out
preferred
What is the width of the nmos and pmos transistors? Why?
What happens to size of inverter if we want to change widths?
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NAND Gate Layouts
A B
Out
A
N
B
Audience Questions:
• What is preferred width of pMOS?
• Why is rightmost preferred? preferred
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Inside A Modern “Standard Cell”
VDD Bus
Have Diffusion running horizontally
– P type “below” the Vdd bus n well
– N type “above” the GND
pmos transistors
Have Poly running vertically
Internal Gate Wiring
Use metal to appropriately wire And Gate I/O contacts
diffusions
– To Vdd & GND nmos transistors
– To the other diffusion p well
– To different points in current
diffusion VSS Bus
Attach I/O contacts to metal
Question to be answered by later “Euler Path” algorithm:
Can we draw diffusion as single long rectangles without gaps?
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A Simple Standard Cell Library
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More Complex Gates
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Pitch-Matching (Fig. 1.65)
Would it help if:
A could be slightly
shorter?
C could be slightly
narrower?
D could be smaller?
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What If We Want to “Stack” Gates?
Vdd Vdd Vdd Vdd
Gnd Gnd Gnd Gnd
Gnd
Design Rule says what?
Vdd
Vdd
Gnd
But What if We “Flip”
One Row?
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MIPS ALU & Data Flow via Standard Cells
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Now for the Full 8 Bit Data Flow
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What If We Can’t Use the Internal
Wiring Channels?
Wiring Channel
Wiring Channel
Audience Questions:
1. How many levels of metal do we need for this?
2. How would you estimate the height of the wiring channels?
3. Why is deciding which logic gate standard cell goes where important?
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A Fully Synthesized 8-bit MIPS
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