CLOCK DIVIDER DESIGN

3.1 Introduction

In a PLL synthesizer, of all the PLL components, circuit design of the VCO and

the frequency divider is very critical. The reason partly is these components operate at

the highest frequencies within the PLL and also consume most of the power as

compared to the other components. As part of this thesis, a digital frequency divider

based on True Single Phase Clocking (TSPC) has been designed. It was more an attempt

to learn the different aspects of digital design at high frequencies. This work is mostly

based on the concepts provided in [20]. A divider with dual modulus of 256/288 has

been designed to divide the band of frequencies specified for the 802.11a WLAN

standard which is from 5.14 GHz to 5.72 GHz to a frequency of 20 MHz which forms

the reference frequency to the frequency synthesizer. This work does not include a

swallow counter needed for dynamic programmability

3.2 Circuit Configuration and Working

The frequency divider designed here consists of three main blocks, a divide-by2,

a divide-by-8/9 and a divide-by-16 block, as shown in figure 3.1. The divide-by-8/9

prescaler whose structure is shown in figure 3.2 proves to be a rather critical block. The

input frequency is first halved by a divide-by-2 circuit so that the speed constraints of

this prescaler can be relaxed. The prescaler is usually followed by a program counter

and a swallow counter which allows to dynamically control the overall division ratio

between 256 and 288 and to sweep the output frequency between 5.14 and 5.74 GHz in

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20-MHz steps. Hence, the synthesized signal is suitable to operate both in the

HiperLAN II bands [18] and in the 802.11a lower and middle bands [19], assuming

direct-conversion or low-IF receiver architectures.

Figure 3.1 Block diagram of frequency divider

Generally, a TSPC logic flip-flop (FF) is used to synchronize the programmable

divider output to the first divide-by-2 circuit output. This FF can cancel out the

accumulated time jitter due to the divide-by-8/9 prescaler and the divide-by-16 program

counter [12]. Two or three cascaded CMOS logic inverters are needed after the first

divide-by-2 to drive the divide-by-8/9 prescaler and the synchronizing FF.

Figure 3.2 Divide-by-8/9 prescaler topology

3.2.1 Divide-by-2 Circuit

The divide-by-2 circuit realized in the TSPC logic is shown in figure 3.3. The

salient feature of the TSPC clocking technique is that there is only one clock signal

needed to trigger the flip-flops and no extra clock phase is required whatsoever. This

technique is mainly used in dynamic CMOS circuits and helps to simplify the design.

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 V

Figure 3.3 Circuit schematic of a TSPC divide-by-2

The circuit consists of three parts. The first part is a gated inverter that consists

of MP1, MP4 and MN1, which passes the divider output to the following stage when In

goes low. The second part is a latch stage that consists of MP2, MP3, MN2, MN3, MN4

and MN5. This circuit will be activated and store the output of the gated inverter when

In is high. The PMOS transistors MP1 and MP2 are used to pre-charge the internal

nodes to increase the speed of the circuit. The output of the flip-flop is directly

connected back to the D-input to obtain the divide-by-2 function because the TSPC

circuit can completely isolate the sense and latch stage at different phases of the clock

signal. The static power of the circuit is zero because no direct path from supply to

ground exists and it only consumes dynamic power. One of the advantages of the TSPC

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divider is its simplicity. The circuit consists of only nine transistors. In some cases

where the inverted output is required an inverter is included which adds two more

transistors. The circuit requires an input signal of large amplitude, and it is very

sensitive to the slope of the signal. Therefore, a high-frequency input buffer may

sometimes be needed in front of the divider to drive it. The speed of the circuit greatly

depends on the voltage supply. The circuit will be slow if a low-voltage supply is used.

In order to operate at higher frequency, larger sizes of the transistors are needed to

increase the gm and thus make it operate faster. However, increasing the size also

increases loading for the previous stage and thus the trade-off should be considered

during design. Moreover, using larger transistor sizes will increase the degree of charge

leakage and charge sharing at the output nodes and thus will affect the minimum

operation frequency of the circuit.

3.2.2 Divide-by-8/9 Circuit

The divide-by-8/9 prescaler shown in figure 3.2 above, is comprised of a

divideby-2/3 synchronous divider and two asynchronous divide-by-2 circuits. While the

latter are implemented again in TSPC logic, the divide-by-2/3 circuit has been realized

using the extended true-single-phase-clock (E-TSPC) logic proposed in [21]. A block

diagram representation and the schematic of the divide-by-2/3 circuit are shown in

figure 3.4 and figure 3.5 respectively. Compared to the classical TSPC logic, the E-

TSPC avoids the stacked MOS structure that slows the switching speed, and all the

transistors are free from the body effect. For these reasons, E-TSPC logic allows higher

operating frequencies, although it features static power dissipation. However, this

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causes only a small increase in power dissipation, since at the frequencies of interest the

dynamic power consumption is dominant over the standby current [21].

Figure 3.4 Block level representation of divide-by-2/3 circuit

Figure 3.5 Schematic of divide-by-2/3 circuit

This logic also allows embedding complicated logic functions within the latches. This

results in very compact circuits and in a reduced number of transistors. The concept is

applied in the design of the divide-by-2/3 circuit, where the AND and the OR gates are

realized by adding only one transistor each as evident from figure 3.4.

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3.2.3 Divide-by-16 Circuit

The divide-by-16 program counter can be viewed as an extension of the

divideby-2 circuit. It is implemented by simply cascading four divide-by-2 circuits as

shown in figure 3.6. The output of this circuit is fed into the frequency synthesizer

where the PFD compares it with the reference frequency.

Figure 3.6 Block diagram of divide-by-16 circuit

Figure 3.3 Circuit schematic of divide-by-2

3.4 Simulation Results and Inferences

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 A frequency divider has been designed to operate at a frequency of 5 GHz. The

circuit was simulated using the Mentor Graphics Tool. The transient response of the

circuit to both sine wave and square wave input is shown in the plots that follow.

(a)

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 (b)
Figure 3.9 Transient response of divide-by-2 circuit to (a) sine wave input and (b)
square wave input

Figure 3.10 Schematic of divide-by-2 circuit

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 The divide-by-2/3 circuit has a control input MC. By applying the right voltage

at the control input the divider can be configured to work as either a divide-by-2 or

divide-by-3. If divide-by-2 operation is required MC should be set to a binary value of 1

(2.5 V) and if divide-by-3 operation is required MC should be set to a binary value of 0

(0 V). The waveforms are shown in figures 3.11 and 3.12.

(a)

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 (b)
Figure 3.11 Transient response of divide-by-2/3 circuit with control input MC = 0, to (a)
sine wave input and (b) square wave input

(a)
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 (b)
Figure 3.12 Transient response of divide-by-2/3 circuit with control input MC = 1, to (a)
sine wave input and (b) square wave input

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Figure 3.13 Schematic of divide-by-2/3 circuit (refer figure 3.5)

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 (a)

(b)
Figure 3.14 Transient response of divide-by-8/9 circuit with control input MC = 1, to (a)
sine wave input and (b) square wave input
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 (a)

(b)
Figure 3.15 Transient response of divide-by-8/9 circuit with control input MC = 0, to (a)
sine wave input and (b) square wave input

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Figure 3.16 Waveforms at intermediate nodes in circuit

Figure 3.17 Waveform of complete circuit

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 Layout

A full custom layout of the divider shown in Figures 3.18 and 3.19 was designed

to optimize for area and reduce interconnect parasitics. This helps to achieve greater

speed of operation.

Figure 3.18 Layout of divide-by-2 circuit

Figure 3.19 Layout of divide-by-2/3 circuit

the transistors is kept at the minimum the technology allows which is 0.25 µm.

Table 3.2 Transistor Widths of Divide-by-2 Circuit

MP1 1.5

MP2 1.9

MP3 2.4

MP4 1.5

MN1 0.5

MN2 1

MN3 1.5

MN4 1.7

MN5 1.7

Table 3.3 Transistor Widths of Divide-by-2/3 Circuit

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PMOS Transistor Width (W) in µm NMOS Transistor Width (W) in µm

Mp1 3 Mn1 0.5

Mp2 2 Mn2 1.3

Mp3 3 Mn3 2

Mp3 1.5 Mn4 2

Mp5 3 Mn5 0.5

Mp6 3 Mn6 0.5

Mp7 2 Mn7 1.3

Mp8 3 Mn8 3

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