JFET
• a "Unipolar" device that depends only on the conduction of
electrons (N-channel) or holes (P-channel).
• a three-terminal device used for amplification and switching
Application.
• a voltage-controlled device.
• high input resistance
Device structure n-channel JFET
Depletion layer
Two types of JFET
• n-channel JFET
• p-channel JFET
• If the channel is doped with a donor impurity, n-type
material is formed and the channel current will consist of
electrons.
• If the channel is doped with an acceptor impurity, p-type
material will be formed and the channel current will consist
of holes.
• n-channel devices have greater conductivity than p channel
types, since electrons have higher mobility than holes; thus
n-channel JFETs are approximately twice as efficient
conductors compared to their p-channel counterparts.
• Have three Terminal: Drain – D, Gate –G and Source – S
n-channel JFET
• Major structure is n-type materials(channels) between
embedded p-type material to form 2 p-n junction
• In the normal operation of a n-channel device, the drain(D)
is positive with respect to the source(S).
• Because the resistance of the channel depends on the gate-
to-source voltage(VGS), the drain current(ID) is controlled
by that voltage.
S
P-channel JFET
• Major structure is p-type material(channel) between
embedded n-type material to form 2 n-p junction
• Current flow from source(s) to drain
• Holes injected to source(s) through p-type channel and
flowed to drain
Basic Operation(n-channel)
• The figure below shows dc bias voltages applied to a n-channel
device.
• 𝑉𝐷𝐷 provides a drain-to-source voltage and supplies current from
drain to source.
• VGG sets the reverse-bias voltage between the gate and the source.
• The JFET is always operated with the gate-source pn junction reverse-
biased.
• Reverse-biasing of the gate-source junction with a negative gate
voltage produces a depletion region along the pn junction, which
extends into the n channel and thus the channel resistance can be
controlled by varying the gate voltage, thereby controlling the amount
of drain current ID.
• The most depleted portion is in the high field between
the G and the D, and the least depleted area is between
the G and the S.
JFET Symbols
• The figure below shows schematic symbols for both n-
channel and p-channel JFETs.
• The arrow on the gate points “in” for n channel and “out”
for p channel.
n-channel p-channel
JFET characteristics
Drain characteristic curve(DCC): two basic case
I. 𝑉𝑔𝑠 = 0 𝑎𝑛𝑑 𝑉𝐷𝑆 increasing with some positive value
II. Vgs< 0, VDS at some positive value
I. Vgs= 0 and VDS increase with some positive value
ID increase for small value of VDS
For large value of VDS the depletion layer become wider, causing
the resistance of the channel increase and ceases the current
increase with VDS
• The gate-to-source voltage is zero ( Vgs =0V) and
produced by shorting the gate to the source, as shown in
figure (a) where both are grounded.
(a)
(b)The drain characteristic curve of a
(a) JFET with Vgs = 0 and variable VDS JFET for VGS = 0.
• As VDD is increased from 0V, ID will increase
proportionally. This is shown in figure (b) between points A
and B. In this area, the channel resistance is essentially
constant because the depletion region is not large enough to
have significant effect.
• Because VDD and ID are related by Ohm’s law, this region
called the ohmic region.
• At point B in the figure, the curve levels off and enters the
active region where ID becomes essentially constant.
• As VDD increases from point B to point C, the reverse-bias
voltage from gate to drain produces a depletion region large
enough to offset the increase in VDS, thus keeping ID
relatively constant.
Pinch-Off Voltage
• For Vgs = 0, the value of VDS at which ID ceases to increase
regardless of VDD increases is called the pinch-off voltage
(point B) and the current at this point is called maximum
drain current (IDSS)..
Breakdown
• As shown in figure(c), breakdown occurs at point C when ID
begins to increase very rapidly with any further increase
in VDS.
• Breakdown can result in irreversible damage to the device,
so JFETs are always operated below breakdown.
II. Vgs < 0, VDS at some positive value
ID
(a) JFET biased withVgs (b) JFET I – V characteristic curve
• With increased magnitude of voltage applied to the gate(𝑉𝑔𝑠 ) the
ID is limited and the pinch-off voltage is also lowered as well.
• ID decreases as the magnitude of VGS is increased to larger
negative values because of the narrowing of the channel.
• Pinch-off occurs at a lower VDS as VGS is increased to more
negative values.
• The value of Vgsthat makes ID approximately zero is the
cutoff voltage (Vgs(off)).
• The JFET must be operated between Vgs= 0 and VGS(off).
• For gate-to-source voltages ranging from 𝑉𝑔𝑠 =
0 𝑡𝑜 𝑉𝑔𝑠(𝑜𝑓𝑓) , ID will vary from a maximum of IDSS (Drain
to Source current with gate Shorted) to a minimum of
almost zero.
• For each increase in magnitude of Vgs, the JFET reaches
pinch-off, where constant current begins.
Comparison of Pinch-Off Voltage and Cutoff Voltage
• There is a difference between pinch-offand cutoff voltage
and also there is a connection.
• The pinch-off voltage (𝑉𝑝 )is the value of 𝑉𝐷𝑆 at which the
drain current becomes constant and equal to 𝐼𝐷𝑆𝑆 and is
always measured at 𝑉𝐺𝑆 = 0.
• However, pinch-off occurs for 𝑉𝐷𝑆 values less than
𝑉𝑃 when 𝑉𝑔𝑠 is nonzero.
• Pinch-off is the minimum value of 𝑉𝐷𝑆 attained at
which 𝐼𝐷 becomes constant and it is varies with 𝑉𝐺𝑆 .
• 𝑉𝑔𝑠(𝑜𝑓𝑓) 𝑎𝑛𝑑 𝑉𝑃 are always equal in magnitude but opposite
in sign.
Ex. For the JFET in Figure below, Vgs(off) = - 4 V and IDSS = 12 mA.
Determine the minimum value of VDD required to put the device in
the constant-current area of operation.
• The minimum value of VDS for the JFET to
be in its constant-current area is
VDS = VP = 4 V
• In the constant-current area with VGS = 0V,
ID = IDSS = 12 mA
• The voltage drop across the drain resistor is:
VRD = IDRD = (12 mA)(560Ω) = 6.72 V
• Apply Kirchhoff’s law around the drain circuit.
VDD = VDS + VRD = 4 V + 6.72 V = 10.7 V. The is the value of
VDD to make VDS = VP and put the device in the constant-current area.
JFET Transfer Characteristic curve(TCC)
• TCC will show the value of ID at certain value of VGS
• The range of 𝑉𝑔𝑠 values from zero to 𝑉𝑔𝑠(𝑜𝑓𝑓) controls the
amount of drain current.
• For an n-channel JFET, 𝑉𝑔𝑠(𝑜𝑓𝑓) is negative, and for a p-
channel JFET, 𝑉𝑔𝑠(𝑜𝑓𝑓) is positive.
Relation of Vgs and ID
• 𝐼𝐷 = 0 𝑤ℎ𝑒𝑛 𝑉𝑔𝑠 = 𝑉𝑔𝑠(𝑜𝑓𝑓)
𝐼𝐷𝑆𝑆
• 𝐼𝐷 = 𝑤ℎ𝑒𝑛 𝑉𝑔𝑠 = 0.5𝑉𝑔𝑠(𝑜𝑓𝑓)
4
𝐼𝐷𝑆𝑆
• 𝐼𝐷 = 𝑤ℎ𝑒𝑛 𝑉𝑔𝑠 = 0.3𝑉𝑔𝑠(𝑜𝑓𝑓)
2
• 𝐼𝐷 = 𝐼𝐷𝑠𝑠 𝑤ℎ𝑒𝑛 𝑉𝑔𝑠 = 0
• The figure above shows a general transfer characteristic
curve that illustrates graphically the relationship
between 𝑉𝑔𝑠 and 𝐼𝐷 .
• The curve is also known as a trans-conductance curve. The
bottom end of the curve is at a point on the 𝑉𝑔𝑠 axis equal
to 𝑉𝑔𝑠(𝑜𝑓𝑓) and the top end of the curve is at a point on
the 𝐼𝐷 axis equal to 𝐼𝐷𝑆𝑆 .
• A JFET transfer characteristic curve is expressed
approximately as
2
𝑉𝑔𝑠
𝐼𝐷 ≅ 𝐼𝐷𝑆𝑆 1 −
𝑉𝑔𝑠(𝑜𝑓𝑓)
• ID can be determined for any VGSif VGS(off) and IDSS are
known.
• VGS(off) and IDSS are usually available from the JFET
datasheet.
• Transfer characteristic curve (blue) can be developed from
Drain characteristic curves (green) by plotting values of ID
for the values of Vgs taken from drain curves at pinch-off.
1. A particular n-channel JFET has a Vgs(off)= - 5V and
IDSS= 10mA
a) Draw the complete DCC of the JFET.
b) What is Vp for the JFET ?
c) What is ID when VGS= -7V?
2. Given IDSS of JFET n channel is 6mA and Vgs(off)= -7V.
By using these values , determine the drain current, ID
for Vgs=0V , Vgs=-4V and Vgs= -6V, Vgs= -8V .Then draw
the TCC of the JFET.
When:
VGS = 0 ID = ?
VGS = -4V ID = ?
VGS = -6V ID = ?
VGS = -8V ID = ?
JFET Forward Trans-conductance
• The forward trans-conductance (transfer conductance), is
the change in drain current ∆𝐼𝐷 for a given change in gate-
to-source voltage ∆𝑉𝑔𝑠 with the drain-to-source voltage
constant. It is expressed as a ratio and has the unit of
Siemens (S) and give by
∆𝐼𝐷
𝑔𝑚 =
∆𝑉𝐺𝑆
𝑉𝑔𝑠
𝑔𝑚 = 𝑔𝑚0 1 − ,
𝑉𝑔𝑠(𝑜𝑓𝑓)
where the value of gm0 is not
available in data sheet , it can be
calculate using this formula:
2𝐼𝐷𝑆𝑆
𝑔𝑚0 =
𝑉𝑔𝑠(𝑜𝑓𝑓)
JFET: Input Resistance, Rin
• In put resistance (RIN) of the JFET is the resistance of the
reverse-biased gate-source junction. At given Vgs with
reverse gate –source current (𝐼𝑔𝑠𝑠 ), input resistance Rin can
be given by:
𝑉𝑔𝑠
𝑅𝑖𝑛 =
𝐼𝑔𝑠𝑠
where Igss= Gate Reverse Current (if not given refer data
sheet)
• The value of input resistance is absolute value (no sign).
Exercise
1. Calculate input resistance, RIn if Igss= -2nA and Vgs= -20V.
2. For a 2N5457 JFET: typically, IDSS = 3.0 mA, VGS(off) = -6V
maximum, and gfs(max) = 5000 µS and Vgs = -4V. Determine
(a) forward transconductance for VGS = -4V,
(b) ID
3. A JFET has a drain current of 5 mA. If IDSS = 10 mA
and VGS (off) = – 6 V, find the value of (i) VGS and (ii)
VP