Application Report

SBOA114 – February 2006

Design Methodology for MFB Filters in ADC Interface

Applications
Michael Steffes .................................................................................................... High-Speed Products

ABSTRACT
While the Multiple FeedBack (MFB) filter topology is well-known, its application to very
high dynamic range analog-to-digital converter (ADC) interfaces requires a careful
consideration of component value selection. This application report develops the ideal
transfer function, then introduces a component selection methodology and discusses its
impact on noise and distortion. The impact of amplifier Gain Bandwidth Product on final
pole locations is also included, showing several examples. A complete high dynamic
range, differential I/O filter for wide dynamic range ADC driving is then designed. A
simple design spreadsheet embodying this design approach is available for download
with this application report.

Contents
1 MFB Filter Transfer Function...................................................................... 2
2 MFB Active Filter Noise Gain Analysis .......................................................... 5
3 Setting the Integrator Pole to Improve Noise and Distortion .................................. 7
4 Example Designs Showing the Impact of Integrator Pole Location .......................... 8
5 MFB Filter Implemented with Non-Unity-Gain Stable Op Amps ........................... 12
6 Differential Version of 3rd-Order Design ....................................................... 15
7 Pole Sensitivity to Amplifier Gain Bandwidth Product ........................................ 17
8 Summary ........................................................................................... 20
9 References ......................................................................................... 20
Appendix A Output Noise Analysis .................................................................. 21
Appendix B Solution for R3 and C1 .................................................................. 23
Appendix C Effect of an Equal C Target ............................................................ 26
Appendix D Noise Gain Zeroes with C1 = ∞ ........................................................ 27
Appendix E Noise Gain Zeroes for R3 = R2 Targeted ............................................. 30

List of Figures
1 MFB Filter Topology ................................................................................ 2
2 DC Analysis Circuit ................................................................................. 3
3 Feedback Analysis Circuit for MFB Filter ........................................................ 6
4 Initial Test Circuit using the OPA820 in a 1MHz, Butterworth Low-Pass Filter
Configuration ........................................................................................ 9
5 Noise Gain and Open-Loop Gain for Circuit in Figure 4 ...................................... 9
6 New Design Circuit with Noise Gain Peaking ................................................. 10
7 Noise Gain Plot for Figure 6 ..................................................................... 10
8 Simulated Small Signal Bandwidth for Figure 4 and Figure 6............................... 11
9 Output Spot Noise Comparison ................................................................. 12
10 Noise Gain Plot for Initial OPA2614 MFB Filter Design ...................................... 13
11 Noise Gain with OPA2614 Open-Loop Gain for CT = 31.8pF ............................... 14
12 Frequency Response for the OPA2614 MFB Filter Design (Each 1/2 of Figure 14) ..... 14
13 Expanded View of 3rd-Order Filter Response (see Figure 14) ............................. 15
14 Single-Supply Differential ADC Interface with 3rd-Order Bessel Filter (with f-3dB =
FilterPro is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.

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MFB Filter Transfer Function

5MHz) ............................................................................................... 16
15 OPA2614 Single +5V Distortion for Noninverting Differential Gain of 8 ................... 17
A-1 Noise Analysis Circuit for MFB Filter ........................................................... 21

1 MFB Filter Transfer Function

The Multiple FeedBack (MFB) filter is widely used for very high dynamic range ADC input stages. This
filter offers exceptional stop band rejection over other filter topologies (Ref. 1). Figure 1 shows the starting
point for this filter design.
R1

C2

R3 R2
VI

C1 VFB VO

Figure 1. MFB Filter Topology

This design is an inverting signal path, 2nd-order, low-pass filter that offers numerous advantages over
Sallen-Key filters. This single-ended I/O interface can be easily adapted to a differential I/O interface, as
will be shown later.
A few of the advantages of this topology include:
1. No gain for the noninverting current noise and/or DC bias current. Figure 1 shows the non-inverting
input grounded, which is great for reducing noise but less than ideal for DC precision. Adding a resistor
equal to the DC impedance looking out the inverting node achieves bias current cancellation; adding a
capacitor across this resistor reduces the noise contribution for the resistor and the op amp bias
current noise. If the amplifier is a JFET or CMOS type, this bias current cancellation will not work and
the noninverting input should simply be set to ground or a desired reference voltage.
2. The in-band signal gain is set by – (R1/R3). As will be shown, R3 also sets the Q of the filter while
having no influence over ωo.
Embedded within the filter is an Integrator comprised of R2 and C2, along with the Voltage FeedBack
(VFB) op amp. This design normally needs to be implemented using a unity-gain stable, VFB op amp
because the core gain element needs to be configured as an Integrator. There are dynamic range
advantages to using non-unity-gain stable VFB amplifiers and a design approach for successfully applying
those types of devices will be shown later. However, a Current FeedBack (CFB) op amp is usually not
suitable to this type of filter since its local stability requires a feedback resistor nearly equal to a
recommended value. A capacitive feedback as required in Figure 1 will typically not work with CFB amps
without some design tricks that usually impair noise performance (Ref. 2). Since the emerging Fully
Differential Amplifiers (FDA) are essentially voltage feedback op amps, they can also be applied quite
successfully to this topology (Ref. 3).
Numerous approaches to selecting the component values are available in the literature (see, for example,
Ref. 4). An equal-R approach is common, and will be shown as a desirable approach once an initial R2 is
chosen. As ADCs continue to improve, the resistor noise in this filter can actually be a dominant element
in the total noise spectrum delivered to the converter input. One outcome of the equal-R design (Ref. 4) is
that quite unequal Cs are then required for most filter targets. That is in fact generally true for this filter
type (as will be shown later). If an equal C design is desired, another filter type should be considered
(Sallen-Key).

2 Design Methodology for MFB Filters in ADC Interface Applications SBOA114 – February 2006
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MFB Filter Transfer Function

The Laplace transfer function for the circuit of Figure 1 is shown as Equation 1.
Vo 1 1
 ·
Vi C 1C 2R 2R 3
2 1
s
s C
1R 2R 3
R
R 1


3
R3
2
1
R1 R 1R 2C 1C 2
(1)
The various design goals of interest in this equation can be solved as:
• the DC gain (where s = 0):
R in VV
A V
DC 
1
R3 (2)
• characteristic frequency:

o
R R 1C C
1 2 1 2

in radians
(3)
• the quality factor:

 C1
C2
Q
unitless
 R1
R2


R2
R1
R R

R1 2
3
(4)
R
Or, with
 1
R 2,

R3 C1
C2



Q 
R 2 

R 3

1

(5)
As is usually the case in active filter design, there are more passive elements to be resolved than filter
characteristics. Here, there are five elements and only three targets. This situation often leads to the very
common equal-R assumption to reach a design where that is a somewhat arbitrary way to eliminate one
degree of freedom. There should be a more rational way to select component values for these filters.
Looking at the circuit of Figure 1 at DC gives the simplified circuit of Figure 2 that will be used to show the
DC part of the low-pass filter.
R1

R3 R2
VI

VO

RP

Set: RP = R2 + R1 úú R3

Figure 2. DC Analysis Circuit

A resistor (RP) has been added on the noninverting input to provide for DC bias current cancellation in the
output offset voltage. Setting it as shown reduces the output DC error to (IOS • R1) if the op amp shows an
input bias current that has an offset current specification. Again, JFET or CMOS amplifiers would not use
this RP resistor for output DC error reduction.

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MFB Filter Transfer Function

The total output noise is a considerably more involved discussion. Appendix A develops that expression
for the circuit of Figure 2, where the bandlimiting effects of the filter capacitors are neglected. The total
output noise is given as Equation 6 (which is also Equation A-3 in Appendix A), where the terms arising
from RP are neglected.

eo   (e n) 
2 R
1
1
R3

2

4kTR2  R
1
1
R3

2

4kTR1  R
R3
  
2 R
1
1
i n R 2 1
1
R1
R3
 
2

(6)
It would be reasonable to assume that most designs would not want the resistor terms to add too much
more noise at the output than the op amp noise voltage itself. This idea can be used to develop
Equation 7 (Equation A-4 in Appendix A) where the op amp noise voltage (squared) is targeted to be
equal to the total noise power contribution of the R2 and R3 resistors at the output.
2 2

 R
1
1
R3
 en 2 
 4kTR 2
inR 2
2
 R
1
1
R3
 
i n
2

2R 2R1 1

R1
R3
(7)
This expression still includes both R1 and R3. R3 is also a resistor that will contribute to the total output
noise in a similar fashion to R2. It would be preferable to make it as low as possible within the constraint
that it should not load the driving signal source to the point of creating a dominant distortion mechanism in
that prior stage. As a maximum value, it might be reasonable to let it equal R2 while recognizing that
moving it lower will benefit the total output noise. If R3 is tentatively set equal to R2, Equation 7 can be
simplified and put into a form to solve for R2, as shown in Equation 8 (from Equation A-13 in Appendix A).
2
2
R 2
R2  1
A V
1
3A V
 4kT  1
A V
2
(i n )

1
3A V
 
en
in
0
(8)
This equation may then be solved using the quadratic equation for an initial target value for R2 as shown
in Equation 9 (where only the positive solution for R2 is used; note that Equation 9 is also Equation A-14 in
Appendix A).

R2  1
A V
1
3A V
 2kT
2
(in )
 



1

1
3A V
1
A V
 en
2kT

2
1


 (9)
This formula gives an initial suggested value for R2 (note that embedded in this solution is the assumption
that R3 will then be set equal to R2). Both R2 and R3 may be set lower to improve noise. Recognize,
however, that very low values will start to load the output stage driving into this filter and the filter op amp
output stage (if R1 is also very low). They can also be set higher to lighten the loading where an increase
in total output noise will be the result.
Once R2 is selected, either from this noise consideration or from some other approach, we now need to
select one of the capacitor values to remove it from the filter design equations. With two elements
selected, the remaining three can be used to set the three filter design goals. In solving to achieve the
desired filter shape, it is possible (Appendix B) to arrive at an equation for C1 that shows a critical
constraint on the R2C2 product. That constraint can be seen in Equation 10 (which is taken from
Appendix B as Equation B-22):
Q
C1 

o R 2 1Q
o R 2C2
1
A V (10)
Equation 10 clearly shows that the R2C2 product must be low enough to keep the solution for C1 > 0. That
constraint is shown as Equation 11:

o R 2C 2  1 for C1  0
Q
1
A V (11)
or:
1  Q
1
A V ratio of Integrator pole to target
o

o R 2C 2 (12)

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MFB Active Filter Noise Gain Analysis

(1 / ωoR2C2) is physically the ratio of the Integrator pole to the target ωo. Equation 12 sets a minimum limit
for that ratio, while moving above that limit is essentially moving the Integrator pole out relative to ωo
(reducing C2 if ωo and R2 are fixed). Solving for equality in Equation 12 solves for an infinite value of C1.
So, moving the Integrator pole out also reduces the required value for C1 from infinity to some more
reasonable value.
While Equation 11 and Equation 12 give a nice limit on a solution for C2 and C1 (note that once C2 is
selected, Equation 10 gives C1 completely defined by the desired filter shape and a selected R2 value),
they do not tell us much about where to place the Integrator pole.
One option considered for many active filter designs is to set the two capacitors equal. This solution is
sometimes considered preferable to get better matching in order to minimize the sensitivity functions.
Equation 10 actually gives us an easy way to test this approach by temporarily targeting C1 = C2, then
solving the resulting expression for C2 (Appendix C). Equation 13 shows the resulting quadratic while
Equation 14 shows the solution for C2. Again, this simplified approach is only possible if R2 is initially
selected from either a noise approach or some other consideration.
C 22  C 2 1
1 0
R 2 Q
o
1
AV (R 2
o) 2
1
A V
(13)
(which is Equation C-3 in Appendix C;)

C2  1
2Q R 2
o
1A V

1
1(2Q) (1A )
2
V
(14)
(which is Equation C-10 in Appendix C;)
The radical in Equation 14 only solves for non-imaginary C2 values if (2Q)2 • (1 + AV) ≤ 1. Assuming a
minimum AV = 1 requires a Q < 0.353. Setting Q = 0.353 and AV = 1 gives a C2 solution that is two
repeated values given in Equation 15:
C 2
C1
1
1.43R 2
o (15)
Using an active filter for a Q < 0.5 (two real poles) and/or gain < 1 is unlikely because a simple passive
circuit can easily provide attenuation and two real poles without requiring an active element. Thus, an
equal C design is interesting but not particularly useful for an MFB filter design.

2 MFB Active Filter Noise Gain Analysis

One possible approach to setting the (1 / R2C2) product (Integrator pole location) is to investigate what
impact it might have on the resulting noise gain for the completed filter. Recall that the noise gain is the
reciprocal of the feedback attenuation from the op amp output pin back to the inverting input pin. This
noise gain is an important consideration for at least three reasons.
1. Any peaking in the noise gain will, of course, peak up the gain to the output for the total equivalent
input voltage noise (including the R2 effects considered earlier).
2. Noise gain peaking will also reduce the loop gain. All other things being equal, reduced loop gain will
show up as higher output harmonic distortion.
3. The point where the noise gain crosses the open-loop gain (in a Bode plot) also determines the loop
gain phase margin. Phase margin at this crossover point sets the stability for the overall design.
The feedback divider circuit for the MFB filter is shown in Figure 3. An added element is included here that
was not in Figure 1—a parasitic or intentional capacitor (CT) on the inverting input pin.

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MFB Active Filter Noise Gain Analysis

R1

C2 R2
V
–

VO

CT C1 R3

Source input, assumed

low impedance.

Figure 3. Feedback Analysis Circuit for MFB Filter

Here, it is easy to see the multiple feedback nature of the circuit. At DC, the path is through R1 and R2,
while at high frequencies it is through C2.
The desired Laplace transfer function here is from VO to V– (the inverting input voltage). This attenuator is
normally referred to as the β in control theory discussions of negative feedback systems. The solution for
β is shown as Equation 16.

C2
s 2
s  1
C 1R 3


C R1  R
R R 1C C
1 2 1 2

 V
 ·
1 1 2

VO CT
C2
s 2
s  1
C 1R 3 2 2 T 2 2 1 3 1 T


C R1  R
R C 1
C
R R  R 1C C
C
1 1 2
(16)
We are normally more interested in looking at 1 / β, which will be the noise gain discussed earlier.
Inverting Equation 16 gives Equation 17.

s 2
s  1

C R1  R 
R C 1
C 
R R  R  1C C
C  

1  1
C T ·  C 1R 3 1 1 2 2 T 2 2 1 3 1 T 2

C2
s 2
s  1
C 1R 3 1 1 2


C R1  R 
R R 1C C
1 2 1 2
(17)
There are several key points to Equation 17:
1. The poles are identical to the desired filter poles.
2. The DC (s = 0) gain becomes (1 + R1/R3).
3. The high frequency gain (as s→∞) goes to (1 + CT/C2).
4. If CT << C2, then the high frequency noise gain approaches 1.
The noise gain transfer function has two zeroes and two poles. The transition between the DC gain and
high frequency gain depends on the relative position of the zeroes and poles. It would be preferable to
minimize the peaking in the noise gain within the desired low-pass frequency band as it makes this
transition from the DC gain to the s→∞ gain. If the desired filter shape calls for a high Q, peaking in this
noise gain response is unavoidable as the frequency approaches ωo. If, however, one or both zeroes are
placed to fall below the ωo frequency, added noise gain peaking results that might be unnecessary. The
question then is whether or not those zeroes can be placed above ωo in order to limit any additional
in-band peaking for the noise gain.
Starting from Equation 17, first set CT = 0 for this portion of the analysis. It will be used later to allow
non-unity-gain stable amplifiers to be used in the MFB topology, but will unnecessarily complicate the
resolution of (1 / R2C2). Rewriting Equation 17 with this simplification yields Equation 18.

s 2
s  1
C 1R 3

C R1  R 
R 1C
1 1 2 2 2

1
R 2 R 1  R 3  C 1 C 2
1


s 2
s  1
C 1R 3

C R1  R 
1 1 2

1
R 1R 2C 1C 2
(18)

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Setting the Integrator Pole to Improve Noise and Distortion

Then, observing that the numerator coefficients are very nearly the same as the denominator coefficients,
we can rewrite the noise gain equation in terms of the desired filter characteristics as shown in
Equation 19.

s 2
s o
Q

R 1C 

1
A 
V o
2

1 2 2
MFB noise gain


s 2
s  Qo
o 2
(19)
Here, it becomes very apparent that the embedded Integrator pole location, (1 / R2C2), is the one added
degree of freedom in setting the noise gain zeroes. All of the other elements feeding into the noise gain
zero coefficients are set by the desired low-pass, 2nd-order filter terms. It is therefore very useful to cast
the design analysis in terms of this Integrator pole location. More specifically, working in terms of the ratio
(1 / ωoR2C2) allows better simplification and is simply the ratio of the target characteristic frequency and
the embedded Integrator pole location.

3 Setting the Integrator Pole to Improve Noise and Distortion

One limit to the range on (1 / ωoR2C2) has already been set in Equation 12 to achieve real values for C1.
Setting (1 / ωoR2C2) equal to Q (1 + AV) will solve C1 for infinity and R3 for zero. Neither of these values
are particularly useful for implementation, but are interesting as a limit to the noise gain zero locations.
Using Equation 12 to set a minimum level for 1 / R2C2 gives ωo • Q • (1 + AV). Putting this result into the
numerator of Equation 19, and solving for the equivalent QC for the zeroes of the noise gain in terms of
the desired filter shape terms, gives Equation 20 (from Appendix D, Equation D-9).
Q 1
A V
QC   x 2 [ where x  Q 1
AV ]
1
Q 2
1
A V 1
x (20)
This result is very useful in that it clearly shows the maximum possible value for QC is one-half. (1) This
occurs for any combination of desired AV and Q that sets Q • √(1 + Av) = 1. The most common condition
for this would be Q = 0.707 (Butterworth target) and AV = 2. That combination, with a target for the
Integrator pole set by Equation 12, gives repeated real zeroes at ωo / Q (Appendix D). Several important
conclusions come from this combination.
1. The noise gain zeroes are always two real zeroes.
2. They are repeated, and at the maximum value, at ωo / Q for the specific conditions described above
(which is not realizable since C1 = ∞).
3. For Q > 1, it will necessarily be the case that one of the zeroes will fall below the target ωo. This
observation says that higher Q targets in the MFB filter have an added peaking in the noise gain
beyond just the desired filter pole peaking because one of the noise gain zeroes moves below ωo.
4. Moving the target (1 / ωoR2C2) up (moving the Integrator pole out) to get a real solution for C1
effectively moves one of the zeroes up in frequency and the other down in frequency along the
negative real axis in the s-plane.
5. It turns out that this higher zero location corresponds very closely to 1 / R2C2 as the zeroes become
widely separated.
As the (1 / ωoR2C2) target is increased from its minimum of Q • (1 + AV), C1 comes down from infinity and
R3 increases from zero. These changes are both desirable within some limits. As R3 starts to increase
beyond the targeted R2 value (from the noise analysis of Equation 9), it will also start to add meaningfully
to the total output noise. One possible limit to R3 is to set it equal to R2 and resolve what this means for a
(1 / ωoR2C2) target. Equation 21 shows this result (from Appendix E).
1  Q
2A V
1 [ where R 3  R2 is desired ]

o R 2C 2 (21)
Appendix E goes on to solve for the resulting zero location if Equation 21 is used to set 1 / R2C2. That
result is shown as Equation 22 (Equation E-16 from Appendix E).

Z 1 , 2   o 1Q 2 2A V1   1

2Q



 1 2Q 1A V
1Q 2(2AV1)


2

 (22)
(1) x / (1 + x2) reaches a maximum value equal to 1/2 over 0 ≤ x ≤ ∞ at x = 1.

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Example Designs Showing the Impact of Integrator Pole Location

Setting 1 / R2C2 as given in Equation 21 gets R3 = R2. It also sets the two noise gain zeroes as given by
Equation 22. Moving the target (1 / ωoR2C2) below the value set by Equation 21 pulls the Integrator pole
down, moves the lower zero to a higher frequency (acting to reduce the noise gain peaking), and reduces
R3 below R2. All of these desirable effects suggest that (1 / ωoR2C2) should be set slightly below the value
determined by Equation 21 as long as the resulting R3 is not so low as to present too heavy a load for the
driving source into the filter. Since R3 in Figure 1 looks into a virtual ground node in-band, the input
impedance below cutoff will be R3. Conversely, moving the (1 / ωoR2C2) above the value set by
Equation 21 increases R3 beyond the targeted R2 value, moves the lower noise gain zero down further
(causing added peaking in the noise gain within the desired frequency passband), and extends the higher
noise gain zero out in frequency (approximating the 1 / R2C2 Integrator pole location).
In summary, the (1 / ωoR2C2) target should be set within the range indicated in Equation 23.
Q
A V
1  1  Q
2A V
1

o 2C 2
R (23)
Setting 1 
Q
2A
1 gives R  R
o V 3 2
R 2C 2

while setting 1 
oQ
A V
1 gives C 1   and R3  0
R 2C 2 (24)

4 Example Designs Showing the Impact of Integrator Pole Location

Now let's use these results to step through a design and observe the noise and distortion that results from
various selections of (1 / ωoR2C2). All of these designs give the desired filter shape. It is the noise gain
shape and noise contributions of the resistor values that are of interest here.
Start with a target design given by:
• ωo = 2π • 1MHz
• Q = 0.707
• AV = 2 (gives a negative gain of 2 for the signal path)
Then, pick an amplifier to get its noise and open-loop gain characteristic. For this first example, we will
use the single channel OPA820—a relatively low-noise, unity-gain stable, wideband VFB op amp. The
necessary specifications for this part of the design are shown in Table 1.

Table 1. OPA820 Noise and Open-Loop Gain

Specifications
PART NO. GBW (MHz) en (nV/√Hz) AOL (V/V) in (pA/√Hz)
OPA820 280 2.5 2000 1.7

The targeted maximum R2 value is calculated using Equation 9, giving this result:
• Suggested R2 = 366.38Ω
Picking R2 = 250Ω will allow us to proceed to setting the (1 / ωoR2C2) target. The recommended range
(using Equation 23) is:
• Minimum allowed ratio of Integrator/ωo pole is: 2.12
– This result sets a limit to getting a valid solution for C1
• Maximum value to get R3 = R2 is: 3.53
– This result sets R3 = R2 for noise control
If the R3 = R2 value is chosen, the resulting zero locations are (from Equation 22):
• First, compute the radical for the polynomial: 0.714241334
– The lower zero location is 707kHz
– The upper zero location is 4.24MHz

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Example Designs Showing the Impact of Integrator Pole Location

Continuing with the R3 = R2 solution, the final component values to place into Figure 1 and the design
sequence are:
• R2 = 250Ω [selected to control noise using Equation 9]
• C2 = 180pF [set by targeting (1 / ωoR2C2) = Q(2AV +1) ]
• C1 = 1130pF [set using Equation 10]
• R3 = 250Ω [set using Equation B-17]
• R1 = 500Ω [set using Equation 2]
• DC Gain (AV) = 2.00V/V [from Equation 2]
• FO = 1MHz = F–3dB (if Q = 0.707) [from Equation 3]
• Q = 0.707 [from Equation 4]
The noise gain and phase can be computed using Equation 17 where CT = 3pF is used to emulate a
parasitic capacitance on the inverting op amp input. This noise gain and phase can be plotted along with
the open-loop gain and phase for the OPA820. Finally, the phase margin where this noise gain intersects
the open-loop response can be derived.
The example circuit developed here is shown as Figure 4.
500W

180pF

+5V

250W 250W
VI

1130pF OPA820 VO

100W
0.1mF 417W
- 5V

Figure 4. Initial Test Circuit using the OPA820 in a 1MHz, Butterworth Low-Pass Filter Configuration

This circuit gives the loop gain plot of Figure 5.

MFB OVERALL NOISE GAIN
90
OPA820 Open-Loop Gain
60
Noise-Gain Magnitude
Gain (dB) and Phase (°)

30

-30 Noise-Gain Phase

-60

-90

-120

-150 OPA820 Open-Loop Phase

-180 3 4 5 6 7 8 9
10 10 10 10 10 10 10
Frequency (Hz)

Figure 5. Noise Gain and Open-Loop Gain for Circuit in Figure 4

This plot transitions fairly smoothly from a noise gain of 20log(3) = 9.5dB to 0dB with only minor peaking
as a result of the noise gain zero at 707kHz. Phase margin for this circuit is 51 degrees, which is quite
stable.

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Example Designs Showing the Impact of Integrator Pole Location

In order to test the impact of setting the (1 / ωoR2C2) target far too high, set it to 10 and repeat the design
in this manner (still holding R2 = 250Ω):
• R2 = 250Ω [selected to control noise using Equation 9]
• C2 = 63.7pF [set by targeting (1 / ωoR2C2) = 10]
• C1 = 571pF [set using Equation 10]
• R3 = 1.39kΩ [set using Equation B-17]
• R1 = 2.79kΩ [set using Equation 2]
• DC Gain (AV) = 2.00V/V [from Equation 2]
• FO = 1MHz [from Equation 3]
• Q = 0.707 [from Equation 4]
Figure 6 shows the new design circuit with these more widely separated noise gain zeroes (these zeroes
are now at 268kHz and 10.7MHz, solving the numerator of Equation 19).
2.79kW

64pF

+5V

1.39kW 250W
VI

571pF OPA820 VO

100W
0.1mF 1.18kW
- 5V

Figure 6. New Design Circuit with Noise Gain Peaking

MFB OVERALL NOISE GAIN

90
OPA820 Open-Loop Gain
60
Noise-Gain Magnitude
Gain (dB) and Phase (°)

30

-30

-60 Noise-Gain Phase

-90

-120
OPA820 Open-Loop Phase
-150

-180 3 4 5 6 7 8 9
10 10 10 10 10 10 10
Frequency (Hz)

Figure 7. Noise Gain Plot for Figure 6

The loop phase margin is not impacted greatly, going to 54 degrees. This value is slightly better than the
previous one, and still very stable. The plot of Figure 7 clearly shows this lower zero in the phase
response. The noise gain phase curve peaks up much more as the zero comes in earlier and before the
two poles reverse it. More importantly, the noise gain peaks up slightly, reducing the available loop gain in
the passband.

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Example Designs Showing the Impact of Integrator Pole Location

Both design points give the same desired filter shape. Figure 8 shows the simulated small signal
frequency response for both sets of filter component values. Figure 8 shows the desired maximally flat
response with a 1MHz cutoff.
SMALL-SIGNAL AC RESPONSE
9

Figure 6
6

Gain (dB)
Figure 4

0 4 5 6 7
10 10 10 10
Frequency (Hz)

Figure 8. Simulated Small Signal Bandwidth for Figure 4 and Figure 6

Consider the impact of the different loop gains. Assume this circuit was intended for very low distortion
through 600kHz. The loop gain at 600kHz for Figure 5 is 42.8dB while that of Figure 7 is 37.4dB. The
5.4dB loss in loop gain as a result of noise peaking should show up directly in harmonic distortion.
Simulating each circuit for 3rd-harmonic (recognizing that harmonic is falling on the filter skirt at 1.8MHz)
gives the results shown in Table 2. This simulation was looking at the 3rd-harmonic since that term has
shown good correlation to measured data (while even-order terms do not correlate well from simulation to
bench measurements) . Also, a 100Ω load with a 2VPP output was intentionally used to bring the distortion
terms up from very low levels. A lighter load (such as an ADC input ) will have much lower distortion than
reported in this example.

Table 2. Results of 3rd-Harmonic Simulation at

600kHz, VO = 2VPP, RL = 100Ω
TEST CIRCUIT HD3 (dBc)
Figure 4 –83.9
Figure 6 –78.7

The different noise gain shapes have indeed produced a 5.2dB drop in distortion performance—very
nearly equal to the predicted 5.4dB drop from the difference in loop gains at 600kHz.
Figure 7, with the higher resistor values and peaked noise gain, also gives a higher output noise for the
circuit shown in Figure 6 as compared to that of Figure 4. Figure 9 plots the output spot noise over
frequency for both circuits. This simulation includes every noise source both inside the amplifier and the
external resistors. A portion of the low frequency noise (that is decreasing from a high value at 100Hz)
comes from the bias current cancellation resistor on the noninverting input pin. That noise is rolled off by
the 0.1µF capacitor to show the low frequency shape in Figure 9. Part of that higher low frequency noise
is also the 1/f noise modeled by the OPA820.

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MFB Filter Implemented with Non-Unity-Gain Stable Op Amps

OUTPUT SPOT NOISE VOLTAGE

35

30

Output Noise (nV/ÖHz)

25 R3 = 1.39kW Circuit
(Figure 6)
20

15

10
R3 = 250W Circuit
5 (Figure 4)

0
2 3 4 5 6 7
10 10 10 10 10 10
Frequency (Hz)

Figure 9. Output Spot Noise Comparison

As expected, the second design point with the peaked noise gain (and much higher R3 value) shows
significantly higher output noise and more peaking. This noise integrates to considerably higher output VPP
noise over the design of Figure 4.

5 MFB Filter Implemented with Non-Unity-Gain Stable Op Amps

Non-unity-gain stable VFB op amps offer numerous advantages for very high dynamic range applications.
Most of these devices offer lower noise, higher slew rate, and higher open-loop gain over similar
unity-gain stable compensated versions. For the very lowest distortion and noise, it would be desirable to
apply these devices in this MFB filter application. However, since the basic MFB circuit shapes the noise
gain to be a unity gain feedback at high frequencies, a bit of additional work is needed in order to take
advantage of the intrinsically higher dynamic range offered by these devices.
As an example, use the non-unity-gain stable OPA2614 (a dual) to implement a 3rd-order Bessel filter at
5MHz. The OPA2614 (290MHz gain bandwidth product, or GBW) has a unity-gain stable version, the
OPA2613 (125MHz GBW), that could also be used here. In this case, the noise numbers of the two
versions are identical, but the higher gain bandwidth will give 20Log(290/125) = 7.3dB more loop gain at
any frequency above the dominant open-loop pole. This design is working towards a single +5V supply,
differential-in-to-differential-out, gain of 2 interface that includes this 3rd-order linear phase filter. The real
pole is implemented as the RC filter that often appears between the amplifier and the ADC.
First, we must find the required pole locations for this filter. Setting up the design targets in FilterPro™
(Ref. 5) for a 3rd-order Bessell with 5MHz cutoff gives the following required pole location. (Note: FilterPro
also gives simplified circuit designs, but we are only using the pole calculation feature from FilterPro and
will use the circuit design tools developed in this application note to select component values.)
• Real pole at 5.76MHz
• Complex poles FO = 7.24MHz
• Q = 0.691
Stepping through the single amplifier design using the OPA2614 data, we first need a target R2 as shown
in Table 3.

Table 3. OPA2614 Calculations for Target R2

PART NO. GBW (MHz) en (nV/√Hz) AOL (V/V) in (pA/√Hz)
OPA2614 290 1.8 70,800 1.7
Suggested R2 = 195.59Ω This is solving for R2 noise less than op
amp noise using Equation 9.
We pick R2 = 200Ω Note: R2 could be greater than this, but
probably not too much in order to limit
output noise.

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MFB Filter Implemented with Non-Unity-Gain Stable Op Amps

Then we perform the calculation for the limits on the (1 / ωoR2C2) target:
• Minimum allowed ratio of Integrator pole/ωo is: 2.07
– This gives a solution for C1 = ∞
• Maximum value to get R3 = R2 is: 3.45
– This result sets R3 = R2 for noise control
Use the 3.45 target to get R3 = R2.
Then the completed design can be summarized with these component values:
• R2 = 200Ω [selected to control noise using Equation 9]
• C2 = 31.8pF [set by targeting (1 / ωoR2C2) = Q(2AV +1) ]
• C1 = 189pF [set using Equation 10]
• R3 = 201Ω [set using Equation B-17]
• R1 = 402Ω [set using Equation 2]
• DC Gain (AV) = 2.00V/V [from Equation 2]
• FO = 7.24MHz [from Equation 3]
• Q = 0.691 [from Equation 4]
The completed 3rd-order filter design is shown in Figure 14, where a differential implementation is
illustrated.
Lastly, going into the loop gain analysis with CT = 3pF initially gives noise gain zeroes at 5MHz and
28MHz, with the Bode plot for the open-loop and noise gain and phase shown in Figure 10.
MFB OVERALL NOISE GAIN
(with OPA2614 and CT = 3pF)
90
OPA2614 Open-Loop Gain
60
Noise-Gain Magnitude
Gain (dB) and Phase (°)

30

-30

-60
Noise-Gain Phase
-90

-120

-150 OPA2614 Open-Loop Phase

-180 3 4 5 6 7 8 9
10 10 10 10 10 10 10
Frequency (Hz)

Figure 10. Noise Gain Plot for Initial OPA2614 MFB Filter Design

This analysis shows a phase margin equal to 33 degrees. While this phase margin is still stable, some
peaking around 200MHz might be expected in the small signal response. Often, this low degree of phase
margin also has more part-to-part and temperature variation in that peaking. As noted earlier, the noise
gain can be raised at high frequencies by adding CT on the inverting node. Targeting a gain of 2 at high
frequencies requires CT = C2 = 31.8pF. Re-running the loop gain analysis with CT = 31.8pf gives noise
gain zeroes at 4.2MHz and 19MHz, with the Bode plot shown in Figure 11.

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MFB Filter Implemented with Non-Unity-Gain Stable Op Amps

MFB OVERALL NOISE GAIN

(with OPA2614 and CT = 31.8pF)
90
OPA2614 Open-Loop Gain
60
Noise-Gain Magnitude

Gain (dB) and Phase (°)

30

-30
Noise-Gain Phase
-60

-90

-120

-150 OPA2614 Open-Loop Phase

-180 3 4 5 6 7 8 9
10 10 10 10 10 10 10
Frequency (Hz)

Figure 11. Noise Gain with OPA2614 Open-Loop Gain for CT = 31.8pF

This plot clearly shows that the crossover (the point where the noise gain crosses the open-loop gain) has
dropped back to 100MHz. This results in an improved phase margin of 52 degrees—which is considerably
more design margin to avoid unnecessary peaking or oscillation.
The desired signal frequency response is achieved using either design. Figure 12 (CT = 3pF or 31.8pF)
illustrates the expanded plot around cutoff for either design, showing both the output pin response and the
final targeted response at CLOAD in Figure 14. Both designs hit the desired 5MHz cutoff.
3RD-ORDER BESSEL FILTER RESPONSE
9
Output Pin Response
6

3
Response at CLOAD
Gain (dB)

-3

-6

-9

-12
5 6 7
10 10 10
Frequency (Hz)

Figure 12. Frequency Response for the OPA2614 MFB Filter Design (Each 1/2 of Figure 14)

Expanding this plot to show the detail at 200MHz exposes the slight peaking caused by the low phase
margin in the CT = 3pF design (see Figure 13). Adding the CT = 31.8pF smooths this peaking out quite a
bit, with minimal change in the overall response. This basic technique is even more important if higher
minimum stable gain amplifiers are applied to this circuit (such as the OPA2846).

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Differential Version of 3rd-Order Design

3RD-ORDER BESSEL FILTER RESPONSE

6
0
-6
-12
-18 Output Pin Response
-24
-30

Gain (dB)
-36
-42
-48 CT = 3pF
-54
-60 Gain to CLOAD
-66
-72 CT = 31.8pF
-78
-84
-90
-96 6 7 8 9
10 10 10 10
Frequency (Hz)

Figure 13. Expanded View of 3rd-Order Filter Response (see Figure 14)

Figure 13 also shows one of the advantages of the MFB filter followed by a simple RC as part of a
3rd-order design. This approach gives very good stop band rejection to very high frequencies. Other filter
approaches (for example, the Sallen-Key) show an increasing gain at very high frequencies as a result of
2nd-order effects (Ref. 1).

6 Differential Version of 3rd-Order Design

One very useful application for the MFB filter design is providing a single-supply differential interface to
high-performance ADCs with very low distortion and noise. The OPA2614 design can be easily adapted to
this requirement. One new issue is to provide a midsupply DC bias at the noninverting input to keep the
signal swing centered between the supplies. Sometimes, this can be provided as the VCM from the ADC.
Alternatively, a voltage divider from the supply can be used. If the best output DC precision is desired, the
source impedance looking out of each noninverting input should again match the total DC impedance
looking out of the inverting input of each channel as described in Figure 2. Figure 14 shows the differential
implementation for the 3rd-order filter designed previously. Here, separate noninverting bias resistors from
VCM are used. If DC precision is a secondary concern, a single bias resistor (or resistor divider from the
supply) could also be used.

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Differential Version of 3rd-Order Design

401W

32pF

+5V

200W 200W

189pF 32pF 200W

1/2
OPA2614
332W
VCM

0.1mF CLOAD 138pF

VI VO

0.1mF
332W
VCM CLOAD 138pF

200W
189pF 32pF 1/2
OPA2614
200W 200W

5.76MHz Low Pass

32pF

401W

wo = 2p (7.24MHz)
Q = 0.691
2nd- Order Low Pass

Figure 14. Single-Supply Differential ADC Interface with 3rd-Order Bessel Filter (with f-3dB = 5MHz)

The overall filter shape is that shown in Figure 13—a 3rd-order Bessel with a 5MHz cutoff. One critical
implementation choice made in Figure 14 is to keep separate grounded capacitors on each side of the
differential circuit. The same differential frequency response would result if these grounded capacitors
were each replaced by a single differential capacitor across the two circuit halves at one-half the values
shown, eliminating the ground connection. There are advantages and drawbacks to each approach. One
of the attractions for the implementation of Figure 14 is that this circuit also acts to filter any
common-mode signal at high frequencies. Single capacitors across the two circuit halves, on the other
hand, will give a wideband, gain of 2 stage for any common-mode input signal or noise. Furthermore, the
noise gain shaping capacitors at the inverting inputs need to be grounded separately to correctly
implement that noise gain shaping for each amplifier.
This single 5V implementation only requires 10.5mA total supply current (53mW) and gives extremely low
distortion and noise. The total load for each amplifier is simply the feedback resistor. This 400Ω load
shows approximately 90dBc distortion levels for 2VPP in the datasheet plot duplicated in Figure 15.
(Ref. 6)

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Pole Sensitivity to Amplifier Gain Bandwidth Product

DIFFERENTIAL DISTORTION vs LOAD RESISTANCE

-60
GD = +8
VO = 2VPP
-70 f = 1MHz

Harmonic Distortion (dBc)

2nd-Harmonic

-80

-90
3rd-Harmonic

-100

-110
10 100 1k
Load Resistance (W)

Figure 15. OPA2614 Single +5V Distortion for Noninverting Differential Gain of 8

This distortion improves at the lower noise gain setting used in Figure 14. Going from 8 to 3 should give
an approximate 8.5dB improvement from the –95dBc levels shown above to –104dBc. This 2VPP
differential output is well within the available output voltage swing range. On a single +5V supply, the
OPA2614 has a typical 1V headroom requirement to each supply pin. With a 3VPP available output on
each side, using a +5V supply gives a maximum 6VPP differential swing capability. This non-rail-to-rail
output stage provides much lower distortion versus quiescent power than rail-to-rail output designs. For
higher frequencies and/or even lower distortion in this differential I/O interface, the 1.8GHz gain bandwidth
product OPA2846 should be considered.

7 Pole Sensitivity to Amplifier Gain Bandwidth Product

Numerous academic treatments of pole sensitivity functions to filter elements are available (see, for
example, Ref. 4). In general, the MFB filter is desirable in that the root loci, as amplifier gain bandwidth
reduces, is in the direction of more stability. Specifically, from a starting point of desired pole locations
using an infinite bandwidth op amp assumption, the root loci is in the direction of higher ωo and lower Q as
the finite bandwidth amplifiers are inserted into the analysis.
More generally, a single pole model for the op amp can be inserted into the filter transfer function analysis,
and then solved for actual pole locations. This process adds a pole to the analysis, making it a 3rd-order
transfer function. The general form for that transfer function is shown as Equation 25 with each of the
coefficients detailed in Equation 27 through Equation 31. Including the amplifier gain bandwidth product
(GBW) complicated the equation significantly in comparison with Equation 1, but essentially moved the
actual filter poles slightly and added a real pole at the GBW divided by the high frequency noise gain.
Here, no consideration of CT is being made, but that sets the high frequency real pole added by the real
amplifier GBW.
VO H

VI B3s 3
B2s 2
B 1s
B0 (25)
which uses an op amp single-pole model, given by:
A
o
A
s  OL
s

o (26)
Where

:
A OL
Open loop gain

 o
Dominant pole (Hz)
2

A o
 OL
Gain bandwidth product (Hz)
2

Detailed coefficients for Equation 25 are given below.

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Pole Sensitivity to Amplifier Gain Bandwidth Product

AOL
o
H

C 1C 2R 2R 3 (27)

B0 

a
C 1C 2R 1R 2
 R
A OL
1
1
R2

(28)

 
R1

B1 
AOL
a
R 2C 1
1
 R2
R3  R1

1
R
3
C 1C 2R 1R 2


a 1
1
R 2C 2 R 2C 1
1

R2

R 3  R1
(29)

B 2  AOL
1
a

a  1
1
R 2C 2 R 2C 1
1

R2
R3  R1

(30)
B3
1 (31)
As an example, use this analysis to achieve two different filters using an initial GBW op amp of 220MHz;
then step the GBW down in large steps to see the impact on the filter pole locations. Specifically, target a
lower frequency Butterworth design; then target a higher frequency, high-Q design. Table 4 steps through
the targets and then the actual complex pole locations.

Table 4. Actual Pole Locations vs. Amplifier GBW

Target 200kHz, Q = 0.707 Target 2MHz, Q = 3
OPA GBW (MHz) (1) FO (kHz) Q FO (MHz) Q
Infinite (ideal) 200 0.707 2 3
220 200 0.707 2 2.844
139 200 0.706 2 2.76
88 200 0.7055 2.001 2.64
55 200 0.7034 2.003 2.46
35 200 0.7013 2.007 2.23
22 200 0.698 2.017 1.93
14 200 0.693 2.046 1.58
8.8 200.1 0.6845 2.133 1.24

(1) Nominal Gain Bandwidth Product (GBW) = 220MHz.

The lower frequency, low-Q, design can obviously tolerate very slow amplifiers and still hit very near the
desired pole locations. The high-Q, higher FO, design shows very good control over FO but the Q
decreases rapidly with slower amplifiers. Even at 220MHz GBW (100 times over the target FO), the actual
Q is 5% lower than targeted. This is giving what looks like an almost constant ωo root loci with decreasing
angle to the complex poles as they move in a circular path in the s-plane.
Table 4 suggests that the MFB filter is very robust to amplifier bandwidth variations in lower-Q designs.
While even a 35MHz GBW does not move the 200kHz, Q = .707 poles very much, higher GBW amplifiers
give the higher loop gain discussed earlier, which should lead to lower distortion designs.
Table 4 also points out that higher-Q designs will be very sensitive to the amplifier bandwidth, and thus
quite a bit of GBW margin should be provided if a predictable filter response is desired. Additionally, it
suggests that to account for the amplifier GBW, simply targeting a higher Q is all that is needed, since the
ωo is not affected as much. Since R3 is an independent tune for Q (Equation 5), R3 can be used to tune in
the Q after a nominal design to account for the finite GBW of the amplifier. The Q equation has a positive
derivative to R3, so increasing R3 increases the Q if needed (while also decreasing the in-band signal
gain) without impacting the ωo.
For example, do a nominal design for FO = 5MHz and Q = 1.5 using a 280MHz typical GBW amplifier such
as the OPA820, delivering a low frequency gain of –2. Then, include the amplifier GBW in the analysis to
find the actual pole locations, re-target Q a bit higher, and re-design the circuit.

18 Design Methodology for MFB Filters in ADC Interface Applications SBOA114 – February 2006
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Pole Sensitivity to Amplifier Gain Bandwidth Product

Targeting an R2 = R3 design gives the following filter values, where R2 = 350Ω was selected for input
noise control:
• R2 = 350Ω [selected to control noise using Equation 9]
• C2 = 12.1pF [set by targeting (1 / ωoR2C2) = Q(2AV +1) ]
• C1 = 341pF [set using Equation 10]
• R3 = 349Ω [set using Equation B-17]
• R1 = 700Ω [set using Equation 2]
• DC Gain (AV) = 2.00V/V [from Equation 2]
• FO = 5MHz [from Equation 3]
• Q = 1.50 [from Equation 4]
Putting in the actual GBW adds a real pole at 280MHz (recall that the noise gain is 1 at the crossover
point for this simple design). We also get the actual complex poles falling at:
• FO at 5.0004MHz
• Angle = 69.4142°
• Q = 1.4220
The FO is clearly not affected very much by the amplifier bandwidth, but the Q is quite a bit off. Since the
actual Q vs. target Q was a (1.42 / 1.50) = 0.948 ratio, invert this ratio and target the Q at 1.056 times the
target.
Retargeting an initial design at Q = 1.58 gives the following solution. In this case, the Q adjustment occurs
in the capacitor values since we have separately targeted R2 = R3 using the analysis shown earlier.
• R2 = 350Ω [selected to control noise using Equation 9]
• C2 = 11.5pF [set by targeting (1 / ωoR2C2) = Q(2AV +1) ]
• C1 = 359pF [set using Equation 10]
• R3 = 349Ω [set using Equation B-17]
• R1 = 700Ω [set using Equation 2]
• DC Gain (AV) = 2.00V/V [from Equation 2]
• FO = 5MHz [from Equation 3]
• Q = 1.58 [from Equation 4]
Now, including the amplifier bandwidth gives the following complex pole locations (with the same real
pole):
• FO at 5.0004MHz
• Angle = 70.4450°
• Q = 1.4938
This result hits the desired Q very closely and retains the desired gain and FO targets. This technique is
only possible if the designer has a polynomial root finder available to use on the 3rd-order transfer function
shown earlier (Equation 25). Nevertheless, this solution does confirm the technique of targeting just a
slightly higher Q as the right path to correct pole placement when finite amplifier bandwidth is included in
the design. In practice, then, tuning R3 up slightly from the nominal design (while holding all other
components constant) also moves the filter poles towards the desired target (while reducing the gain as
well).

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Summary

8 Summary
The MFB filter is a very desirable filter where excellent stop band rejection is required in a relatively low-Q
stage. The methodology developed here gives a means to control the output noise and amplifier loop gain
in setting the component values. This approach starts by setting R2 in Figure 1 to give the same or lower
output noise contribution as the op amp itself. This initial step is not necessary for filter implementation,
and higher values can be used at the cost of higher output noise. The nature of the MFB filter usually
demands widely different capacitor values for implementation. Equal R on the two input resistors (R3 and
R2 in Figure 1) is, however, a very reasonable design point with the feedback R1 then set to achieve the
desired gain.
For lower-Q designs, setting R2 = R3 typically places the noise gain zeroes at or above the noise gain
poles—thereby limiting unnecessary peaking in the noise gain and its attendant reduction in output
dynamic range. Higher-Q designs will suffer from noise gain peaking, both from the zero locations and the
desired poles. This effect suggests that the higher-Q designs should be followed by a real pole (RC)
and/or set up to cut off well beyond the valid signal frequency range if the lowest distortion is desired. In
general, it seems that the MFB filter is more suited to lower-Q filter requirements.
Lower distortion in the MFB filter can be delivered by applying non-unity-gain stable wideband voltage
feedback op amps to the design. It is possible to hold the amplifier stable by adding a capacitor on the
inverting node in order to shape the noise gain at the crossover point to the needed minimum stable gain
value. This adjustment does not affect the desired filter shape, only the noise gain shape at frequencies
above the desired filter cutoff. Again, a post-RC filter would be desirable; in this case, to roll off the higher
broadband output noise that comes with a noise gain shaped up with frequency.
A design spreadsheet is available to apply the methodology described here using a selection of
high-performance op amps. This spreadsheet comprises five related worksheets:
1. MFBdesign: this sheet allows the user to select a part number, set target filter specifications, and
design the component values. This design sequence has been shown in the examples used in this
application note.
2. PartSelection: this worksheet contains the list of amplifiers with their required specifications and
allows the designer to select a part and then load the needed data in the MFBdesign sheet. The part
number must be entered in the MFBdesign sheet exactly as listed here (note: selection is case-
sensitive). Also, this sheet shows the resulting loop gain plots and final phase margin. This sheet is
where a CT value would be selected for noise gain control if a non-unity-gain stable amplifier is
selected.
3. NoiseGainPlot: the noise gain calculations are performed on this worksheet, with the plot replicated in
the PartTable sheet.
4. PartAolgain: each of the device open-loop gain over frequency values are tabulated
5. PartAolphase: each of the device open-loop phase values are tabulated

Note: Within the spreadsheet, designer data entry points are shaded cells with bold format. All
other result and data cells are locked to avoid inadvertent data or computation cell
changes.

9 References
1. Karki, J. Active low-pass filter design. Texas Instruments application note (SLOA049).
2. Stephens, R. (2004). Active filters using current-feedback amplifiers. Texas Instruments Analog
Applications Journal. 2004:3, 21-28.
3. Karki, J. Fully differential amplifiers. Texas Instruments application note (SLOA054).
4. Budak, A. (1974). Passive and active network analysis and synthesis. Boston: Houghton Mifflin. p. 351.
5. FilterPro active filter design application. Texas Instruments software (SBFA001).
6. OPA2614 product datasheet from Texas Instruments (SBOS305).
7. Steffes, M. Noise analysis for high-speed op amps. Texas Instruments application note (SBOA066).
To obtain a copy of the referenced datasheet, software and application reports, visit the Texas
Instruments web site at [Link].

20 Design Methodology for MFB Filters in ADC Interface Applications SBOA114 – February 2006
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Appendix A

Appendix A Output Noise Analysis

Equation A-1 through Equation A-14 develop the solution for the output noise using Figure A-1.
en

*
* in
eo
RP

4kTRP *
* in
R2

4kTR2 * 4kTR1
R1

*
R3

* 4kTR3

Figure A-1. Noise Analysis Circuit for MFB Filter

Gain for inverting current noise to output (by super-position):


e o  I n R 2 1
 
R1
R3

R1
(A-1)
Design constraint to get bias current error cancellation:
R P  R2
R 1  R 3 (A-2)
Total output noise by calculating the root mean square (RMS) of each term to the output and then
neglecting the RP terms (assuming it will be bypassed by a large capacitor):

eo   (e n) 
2 R
1
1
R3

2

4kTR2  R
1
1
R3

2

4kTR1  R
R3
2
  
R
1
1
i n R 2 1
1
R1
R3
 
2

(A-3)
Set the en term equal to the terms arising from R2 and R3 (this is dropping out the [in2R12] term):
2 2

 R
1
1
R3
 2 
e n  4kTR 2
inR 2 
2 R
1
1
R3
 
i n
2
2R 2R1 1
 
R1
R3
(A-4)
(and Equation 7 in the main text). Because we would like en to dominate, we then solve for a limit to R2:

 
2 2R 2R 1
 4kTR2
i nR 2
i n
2 2
en
1
R 
R1
3
(A-5)
Solving for equality:

2
e n 2  4kTR2
i n 2R 2R 1  R3
R 2
2
 (A-6)

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Appendix A
Isolating on R2 terms:
2
2 2

e n 2  in R 2
R 2 4kT
2in R 1  R 3 
(A-7)
Then solving for R2:

R 2
R2 4kT
2

in
2
 e

2 R 1  R 3  n
in
  
2
0
(A-8)
Let R3 = R2 to continue developing an initial limit for a maximum R2 value.

R 2
R2 4kT
2

in
2

2R 2R 1
R 2
R 1
e
 n
in
  
2
0
(A-9)
But:
2R 2R 1 2R 2 2R 2 2R2A V
  
R 2
R 1 1
2R 1
1 A V
1
R1 AV
(A-10)
R R
where 2
3
1 is used  magnitude only, sign not required for noise computations 
R1 R1 AV
.
Then, putting Equation A-10 into Equation A-9:

2
R 2
R2  in
2 A V
1 in

4kT
2R 2A V  e n  
2
0
(A-11)
Regrouping terms:
2
R2
2
 1

2A V
A V
1


R 2 4kT 2
(i n )
e
 n
in
  0
(A-12)
Putting into standard monic form:
2
2
R 2
R2 1
A V
1
3A V
 4kT  1
A V
2
(i n )

1
3A V
ei  n
n
0
(A-13)
Then, using the quadratic formula, the positive solution for R2 will be:

R2  1
A V
1
3A V
 2kT
2
(in )
 



1

1
3A V
1
A V
 en
2kT

2
1


 (A-14)
This equation (Equation 9 in the text) estimates a maximum R2 value that will limit the separate noise
power contributions of the resistors R2 and R3 at the output to approximately equal the op amp input noise
voltage contribution.
To achieve this, it assumes that R3 = R2 and RP is bypassed by a large capacitor in Figure A-1. In
practice, selecting R2 to be less than the value derived in Equation A-14 and R3 < R2 would be desirable.
For a background discussion of op amp noise calculations, see Ref. 7.

22 Design Methodology for MFB Filters in ADC Interface Applications SBOA114 – February 2006
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Appendix B

Appendix B Solution for R3 and C1

This appendix, with Equation B-1 through Equation B-21, develops the solution for R3 and C1 discussed in
this application report, starting from the full filter Laplace transfer function.
Vo 1 1
 ·
Vi C 1C 2R 2R 3
2 1
s
s C
1R 2R 3
R
R 1


R3
3 2
1
R1 R 1R 2C 1C 2
(B-1)

DC Gain s  0  

R1
R3
 define A V 
 RR  
1

3
 We only need gain magnitude for design 

o
R R 1C C
1 2 1 2
(B-2)

 C1
C2
Q
unitless
 R1
R2


R2
R1
R R

R1 2
3
(B-3)
R
Define
 1

R2


 C1
C2
Q 
 2





1

R2
R3
(B-4)
Simplifying

 R3
C1
C2
Q 
R 



3
1
R 

2

R 
C1
3 C2
Q 
R
R  

R  
2 3 3 
1

(B-5)
Isolating on R 3


QR 3 

1

QR 2

 R
3  C1
C2

R 3  C1
C3
Q 

 1
   QR2 

QR 2 
QR 2
R 3  
 C1
C2
Q 

 
1 
C1 1
· Q 1

1
C2 

 
(B-6)

SBOA114 – February 2006 Design Methodology for MFB Filters in ADC Interface Applications 23
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Appendix B
R1
Putting
 back into this :
R2
QR2 Q


R 3  
 ·C1
C2
R2
R1
R

Q 1
R2
1
  ·
C1
C2
1
R 1R 2
 Q 
R1R 2
(B-7)
Using 1

o to get 1

o C 1C2
R 1R2C 1C2 R 1R2 (B-8)
Substituting this result in


R 3 
Q  Q
 C1
C2

o C 1C 2
 Q 
R 1 R 2

oC 1
 Q 
R1R 2
(B-9)
Multiplying R 1  R2 through


R 3  R 1  R 2
Q

oR 1  R 2C 1
Q (B-10)
Replace R 1  AVR 3


R 3  A VR3  R2
Q

oA VR 3  R 2C1  Q
A VR3R 2 Q
R 3  ·
A VR3
R 2
oAVR 3R 2C1
A VR3
R 2
Q
(B-11)
Multiply
A VR3
R 2 through denominator 

A VR 3R 2Q
R 3 

oA VR 3R 2C 1  Q A VR 3
R 2 (B-12)
Now divide R3 out of the numerator to get the right side equal to 1, and then multiply the denominator
across:

oC1
A VR3R 2
QA VR3
QR 2  A VR2Q (B-13)
Isolate and solve for R3:
R 3

oC 1A VR2QA V  QR 2
AV
1 (B-14)
QR2
A V
1
R3   one solution for R3 once C 1 and R 2 are resolved

oC 1A VR2QA V (B-15)
Now, to get a second solution for R3:
Use
o2
1
1
R 1R 2C 1C 2 A V R 3R 2C 1C 2 (B-16)
With R 1
AVR 3 giving R 3
1
A V
o 2 R 2C 1C 2 (B-17)
as a second solution for R3 to eliminate it for now.
Set the two R3 equations (Equation B-15 and Equation B-17) equal:
1 QR 2
A V
1
R3  
A V
o 2 R 2C 1C 2
oC 1AVR 2QA V (B-18)

24 Design Methodology for MFB Filters in ADC Interface Applications SBOA114 – February 2006
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Appendix B
Cross−multiply 

2

oC1A VR2QA V  A V
o 2 R 2 C1C 2Q
A V
1 (B-19)
Isolate on C 1 

 2
QA V  C1
oA VR2A V
o2 R 2 C 2Q
AV
1 
(B-20)
Pull out ωo AVR2 and solve for C1:
QA V
C1 
AV
o R 2 1
oR 2C 2Q
AV
1 (B-21)
Q
solution for C 1
C1 

oR 2 1Q
o R 2C2A V
1   (B-22)
which is given as Equation 10 in the text.
With R2 estimated by the noise analysis, this isolates down to a question of setting the R2C2 product.
Once the product is set, C1 is uniquely resolved; then Equation B-15 (or Equation B-17) will give R3, and
then R1 will be set by the target AV.

SBOA114 – February 2006 Design Methodology for MFB Filters in ADC Interface Applications 25
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Appendix C

Appendix C Effect of an Equal C Target

This section, by means of Equation C-1 through Equation C-11, develops the solution for C1 = C2 and its
impact on achievable filter response.
Starting from Equation B-22 and constraining C1 = C2:
Q
C 1  C2 

oR 2 1R2C 2Q
o
1
AV

(C-1)
Q
C 2C22 R 2Q
o
1
AV 

oR 2 (C-2)
C 22C2 1
1 0
R 2Q
o
1
AV R
2
1
A 
2 o V (C-3)
Let: R 2
o 1
A V  x (C-4)
Then:
C 22C2 1
12  0
Qx 1
A V x
(C-5)
In quadratic form:
2
C 2
bC 2
c  0 (C-6)
which solves generally as:

C2   b
2
  1
1 4c2
b

(C-7)
Substituting b  1 and c  12 ,

Qx 1A V x

C2  1
1 x4 Q x (1A ) 
1
2Qx 1AV
2
2 2
V
(C-8)

C 
2
1
2Qx 1A
1
1 2Q  1A   2
V
V (C-9)
Substituting back in from x = R2ωo √1 + Av :

C2 
2QR
1A 
1
o
1
1 2Q  1A   2
V
2 V (C-10)
2
To get non-imaginary solutions for C2, (2Q) (1 + AV) < 1, letting AV = 1, this solves for 1 at Q = 0.357. At
this one solution:
C2  1 With A V  1, this produces 1
2QR2
o 1
A  V
4QR 2
o
(C-11)
Then, with Q = 0.357:
C2
1
C1 if AV
1 and Q
0.357 is the target 
1.43R2
o (C-12)
Letting AV < 1 will allow higher Q to be achieved and get C1 = C2, solving for the radical in Equation C-10,
but this is an unlikely design target for an active filter.

26 Design Methodology for MFB Filters in ADC Interface Applications SBOA114 – February 2006
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Appendix D

Appendix D Noise Gain Zeroes with C1 = ∞

Equation D-1 through Equation D-21 develop the solution for the noise gain zeroes discussed in this
application note.
Starting from Equation 18 for the MFB Filter Noise Gain:

s 2
s

 1
1
1 

 C R
1 C3R  R  1
C R

1 R2R 
1
R C C
2 2 2 1 3 1 2
1


 
s 2
s
1
1


R R 1C C
CR C1  R R
3  1 1 2 1 2 1 2
(D-1)
The denominator is the desired filter poles. Rewrite this noise gain transfer function in terms of the desired
filter shape.

1
Q
s 2
s  o
1
R 2C 2

1
AV o2

s 2
s  o
 o 2
Q (D-2)
to solve for the zero locations.


Define o
1  C


Q R 2C 2 QC (D-3)
and substitute:
o 1
AV 
C (D-4)
Then the zeroes will be given by the roots of:


s 2
s c

c 2  0
Qc (D-5)
For C1 = ∞, we know (from Equation 10):

o R 2C 2  1
Q
1
A V (D-6)
which gives a minimum limit on the Integrator pole:
1 
Q
1
A 
o V
R 2C 2 (D-7)
Solve for zero locations if this limit is used to set a boundary on where the zeroes can be placed.
As (1 / R2C2) is increased from this minimum value, the linear coefficient for the zeroes polynomial of
Equation D-2 will increase. This increase will have the effect of spreading the two zeroes farther apart.

SBOA114 – February 2006 Design Methodology for MFB Filters in ADC Interface Applications 27
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Appendix D
Solving Equation D-5 gives zeroes at:

Z 1,2 

C
2Q C

1
12Q   C
2

(D-8)

Let
C 
o 1
A V and setting Q C to have 1 
Q
1
A 

o V
R 2C 2


c
o 1
A V Q 1
A V
QC  


o
1 o


o Q 1
A V 1
Q 2 1
A V
Q R 2C 2 Q (D-9)
Substituting these into zero Equation D-8 gives:

o 1A V

Z 1,2 

2Q1A V
1Q 2 1A V

1



1
2Q 1A V 
2


1Q2 1A V 
(D-10)
Simplifying:


Z 1,2  

o 
2Q
1Q 2 1A V 1


 1
4 Q21A V
1Q 2 1A V
2
 (D-11)
Define x  Q 1
A V to substitute in temporarily. (D-12)
This gives zeroes at:

Z 1,2  

o 1x2
1
  1

4x 2

Q 2
1x 2 2
(D-13)

2
Distribute 1x through :
2

Z 1,2 
Q


o 1x2


2

 1x 2 x 2
2

2 

 (D-14)
Expand terms in the radical:

Z 1,2 
Q


o 1x2
2

14  x2  x4 x 
2 4 2

(D-15)

Z 1,2 
Q


o 1x2 1
2


2
12x 2x 4   

Q
1x2
o 2

1
2
x 1
2
2

(D-16)

Z 1,2 
Q 2 2


o 1 x2 2

x 1
2 2
 
(D-17)

28 Design Methodology for MFB Filters in ADC Interface Applications SBOA114 – February 2006
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Appendix D
Solving for each zero and substituting back in for x:

o  2  
o 2 
Z1  x  Q 1
A V  
o Q 1
A V
Q Q (D-18)


o  

o if Q  1,  Z 2  
o
Z2  1 
Q Q (D-19)
To get repeated real zeroes, set Z 1  Z 2 and solve :



o

o Q 1
A V
Q


or when: 1  Q 2 1
A V (D-20)
For instance, Q = 0.707 and AV = 1 will give repeated zeroes at:
Z  Z 

2
1 2 o (D-21)
This analysis shows that at the limit—where C1 solves for infinity by setting ( [1 / R2C2] =
ωoQ [1 + AV] )—and the very common filter target of a Butterworth filter at a gain of 1, this filter has noise
gain zeroes that are repeated and that fall at (√2 ωo) which is well beyond the filter poles. Moving the
Integrator pole up (1 / R2C2) to get real solutions for C1 will be splitting these two zeroes, with one coming
down in frequency and the other moving up in frequency.

SBOA114 – February 2006 Design Methodology for MFB Filters in ADC Interface Applications 29
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Appendix E

Appendix E Noise Gain Zeroes for R3 = R2 Targeted

Equation E-1 through Equation E-21 develop the solution for the noise gain zeroes if R3 = R2 is desired.
Start with the solution for R3 from Equation B-15.
QR 2 A V
1
R3 

o A VR2C 1QA V (E-1)
Substitute in for C1 from Equation B-22:
Q
C1 

o R 2 1Q
oR2C 2
A V
1 (E-2)
QR 2A V
1
R3 

o A V R 2Q
QA V

oR 21Q
oR2C 2A V
1
(E-3)
A
1
Pulling V out and cancelling Q, dividing
OR 2 out of the first denominator term :
AV



A V
1 R2
R3  1
AV 1
1Q
o R2C 2 AV
1 (E-4)
Multiplying the denominator term through :

R3 
A V
1
AV
R2
1Q
oR 2C 2 A V
1
11
Q
oR 2C 2 A V
1
A
1
 V
AV
R2 1
Q
o R 2C 2 A V
1
1  
(E-5)

R3  1
Q
o C 2A V
A
1
 V
AV
R2 
R2
Q
o R2C 2A V
R 2 1
1
AV
 
(E-6)
Set R3 = R2 and solve the resulting expression for ωoR2C2:

R 2  R2 Q
R1 C A
1
A1 
o 2 2 V V
(E-7)
1 1
1
1
Q
o R2C 2A V AV (E-8)

2 1 
1
A V Q
o R 2C 2

1 
(E-9)
then 2A V
1  1
Q
o R 2C 2 (E-10)

o R 2C 2  1
Q
2A V
1 (E-11)
or:
1  Q
2A V
1

o R 2C 2
Setting ωoR2C2 to this value in Equation E-2 will give a valid C1 solution. Now go on to solve for the zero
location if (1 / R2C2) = ωoQ(2AV + 1) in Equation D-2.

30 Design Methodology for MFB Filters in ADC Interface Applications SBOA114 – February 2006
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Appendix E
Now go back to the zero equation (from Equation D-8):

Z 1,2  

C
2Q C
1
12Q C

2
 where :
(E-12)

C 
o 1
A V


and

c
Q C 
o
Q

R 1C
2 2

Then, putting in 1 
Q
2A
1 :

o V
R 2C 2 (E-13)
which will be forcing R3 = R2,

o 1
A V Q 1
A V
QC  

o


oQ 2AV
1 1
Q 2
2A V
1
Q (E-14)
Then, going back to Z1,2 (Equation E-12) and substituting in:

Z 1,2 

o 1A V
2Q1A V
1Q22A V1

1



1
2Q 1AV 
2


1Q2 2AV1
(E-15)

Z 1,2   o 1Q 2 2A V1 1

2Q




1
2Q 1A V 
2


1Q2 2AV1
(E-16)
These will be noise gain zeroes with:
o R2C 2  1
Q
2A V
1 (E-17)

which will constrain: R 3
R2 (E-18)

So, in general: 1 
o RCC 2  1
Q
2A V
1 Q
A V
1 (E-19)
with 1 derived via R3  R 2 and 1 derived via C1  .
Q
2A V
1 Q
A V
1 (E-20)
It is a bit easier to write the constraint in inverted form. This becomes the ratio of the Integrator pole
(1 / R2C2) to the desired filter ωo.
1
Q(2AV + 1) ³ > Q(AV + 1)
woR2C2

R3 = R2 limit C1 = ¥ limit (E-21)

SBOA114 – February 2006 Design Methodology for MFB Filters in ADC Interface Applications 31
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