Short Circuit (SC) Current Computation through the Thevenin Theorem

An alternate method of computing short circuit currents is through the application of the Thevenin
theorem. This method is faster and easily adopted to systematic computation for large networks.
Consider a synchronous generator feeding a synchronous motor over a line. Following figure (a)
shows the circuit model of the system under conditions of steady load. Fault computations are to be
made for a fault at F, at the motor terminals. As a first step the circuit model is replaced by the one
shown in Fig. (b), wherein the synchronous machines are represented by their transient reactances (or
subtransient reactances if subtransient currents are of interest) in series with voltages behind transient
reactances. This change does not disturb the prefault current 𝐼 0 and prefault voltage 𝑉 0 (at 𝐹).
As seen from FG the Thevenin equivalent circuit of Fig. (b) is drawn in Fig. (c). It comprises
prefault voltage 𝑉 0 in series with the passive Thevenin impedance network. It is noticed that the
prefault current 𝐼 0 does not appear in the passive Thevenin impedance network. It is therefore to be
remembered that this current must be accounted for by superposition after the SC solution is obtained
through use of the Thevenin equivalent.
Consider a fault at 𝐹 through an impedance 𝑍𝑓 . Figure (d) shows the Thevenin equivalent of the
system feeding the fault impedance. It can be write

𝑉0
𝐼𝑓 = (1)
𝑗𝑋𝑇ℎ + 𝑍𝑓

Current caused by fault in generator circuit

′
𝑋𝑑𝑚
∆𝐼𝑔 = ′ ′
𝐼𝑓 (2)
(𝑋𝑑𝑔 +𝑋+ 𝑋𝑑𝑚 )

Current caused by fault in motor circuit

′
𝑋𝑑𝑔 +𝑋
∆𝐼𝑚 = ′ ′
𝐼𝑓 (3)
(𝑋𝑑𝑔 +𝑋+ 𝑋𝑑𝑚 )

Postfault currents and voltages are obtained as follows by super position

 𝑓
𝐼𝑔 = 𝐼 0 + ∆𝐼𝑔
(4)
𝑓
𝐼𝑚 = −𝐼 0 + ∆𝐼𝑚 (In the direction of ∆𝐼𝑚 )

Postfault voltage

𝑉 𝑓 = 𝑉 0 + (−𝑗𝑋𝑇ℎ 𝐼 𝑓 ) = 𝑉 0 + ∆𝑉 (In the direction of ∆𝐼𝑚 ) (5)

where ∆𝑉 = −𝑗𝑋𝑇ℎ 𝐼 𝑓 is the voltage of the fault point 𝐹 ′ on the Thevenin passive network (with
respect to the reference bus G) caused by the flow of fault current 𝐼 𝑓 .
An observation can be made here. Since the prefault current flowing out of fault point F is always
zero, the postfault current out of F is independent of load for a given prefault voltage at F.

The approach to SC computation is summarized in the following four steps:

Step 1: Obtain steady state solution of loaded system (load fl ow study).
Step 2: Replace reactances of synchronous machines by their subtransient/transient values. Short
circuit all emf sources. The result is the passive Thevenin network.
Step 3: Excite the passive network of step 2 at the fault point by negative of prefault voltage (see Fig.
(d)) in series with the fault impedance. Compute voltages and currents at all points of interest.
Step 4: Postfault currents and voltages are obtained by adding results of steps 1 and 3.
The following assumptions can be safely made in SC computations leading to considerable
computational simplification:
Assumption 1: All prefault voltage magnitudes are 1 pu.
Assumption 2: All prefault currents are zero.
The first assumption is quite close to actual conditions as under normal operation all voltages (pu)
are nearly unity.
The changes in current caused by short circuit are quite large, of the order of 10–20 pu and are
purely reactive; whereas the prefault load currents are almost purely real. Hence the total postfault
current which is the result of the two currents can be taken in magnitude equal to the larger component
(caused by the fault). This justifies assumption 2.
By using this approach, the results of Example 3 can be recalculated. The circuit model of the
system in Example 3 for computation of postfault condition is shown in the following figure.
 These results are the same (and should be) as calculated already in Example 3.

Selection of Circuit Breakers

Two of the circuit breaker ratings which require the computation of SC current are: rated
momentary current and rated symmetrical interrupting current. Symmetrical SC current is obtained
by using subtransient reactances for synchronous machines. Momentary current (rms) is then
calculated by multiplying the symmetrical momentary current by a factor of 1.6 to account for the
presence of DC off-set current.
Symmetrical current to be interrupted is computed by using subtransient reactances for
synchronous generators and transient reactances for synchronous motors—induction motors are
neglected. The DC off-set value to be added to obtain the current to be interrupted is accounted for by
multiplying the symmetrical SC current by a factor as tabulated below
 If SC MVA (explained below) is more than 500, the above multiplying factors are increased by 0.1
each. The multiplying factor for air breakers rated 600 V or lower is 1.25.
The current that a circuit breaker can interrupt is inversely proportional to the operating voltage
over a certain range, i.e.,

Of course, operating voltage cannot exceed the maximum design value. Also, no matter how low
the voltage is, the rated interrupting current cannot exceed the rated maximum interrupting current.
Over this range of voltages, the product of operating voltage and interrupting current is constant. It is
therefore logical as well as convenient to express the circuit breaker rating in terms of SC MVA that
can be interrupted, defined as

Thus, instead of computing the SC current to be interrupted, we compute three-phase SC MVA to

be interrupted, where

If voltage and current are in per unit values on a three-phase basis

SC MVA (3 − phase) = |𝑉|prefault × |𝐼|SC × (MVA)Base (6)

Obviously, rated MVA interrupting capacity of a circuit breaker is to be more than (or equal to)
the SC MVA required to be interrupted.
For the selection of a circuit breaker for a particular location, we must find the maximum possible
SC MVA to be interrupted with respect to type and location of fault and generating capacity (also
synchronous motor load) connected to the system. A three-phase fault though rare is generally the one
which gives the highest SC MVA and a circuit breaker must be capable of interrupting it.
In a simple system, the fault location which gives the highest SC MVA may be obvious but in a
large system various possible locations must be tried out to obtain the highest SC MVA, requiring
repeated SC computations.

Example 4: Three 6.6 kV generators A, B and C, each of 10% leakage reactance and MVA ratings
40, 50 and 25, respectively are interconnected electrically, as shown in the following figure, by a tie
bar through current limiting reactors, each of 12% reactance based upon the rating of the machine to
which it is connected. A three-phase feeder is supplied from the bus bar of generator A at a line voltage
of 6.6 kV. The feeder has a resistance of 0.06 Ω /phase and an inductive reactance of 0.12 Ω/phase.
Estimate the maximum MVA that can be fed into a symmetrical short circuit at the far end of the
feeder.

Solution: Choose as base 50 MVA, 6.6 kV

Assume no load prefault conditions, i.e., prefault currents are zero. Postfault currents can then be
calculated by the circuit model of Fig. (a). The circuit is easily reduced to that of Fig. (b), where
Example 5: Consider the four-bus system of the following figure. Buses 1 and 2 are generator buses
and 3 and 4 are load buses. The generators are rated 11 kV, 100 MVA, with transient reactance of
10% each. Both the transformers are 11/110 kV, 100 MVA with a leakage reactance of 5%. The
reactances of the lines to a base of 100 MVA, 110 kV are indicated on the figure. Obtain the short
circuit solution for a three-phase solid fault on bus 4 (load bus). Assume prefault voltages to be 1
pu and prefault currents to be zero.

Solution: Changes in voltages and currents caused by a short circuit can be calculated from the circuit
model of the following figure.

Fault current 𝐼 𝑓 is calculated by systematic network reduction as in the following figure.

From Fig. (e), the fault current can be obtained directly as
From Fig. (d), it is easy to see that

Let us now compute the voltage changes for buses 1, 2 and 3. From Fig. (b), we have
 It is obvious that the heuristic network reduction procedure adopted above is not practical for a real
power network of even moderate size. It is, therefore, essential to adopt a suitable algorithm for
carrying out short circuit study on a digital computer.

Algorithm for Short Circuit Studies

It is necessary to evolve a systematic general algorithm so that a digital computer can be used.
Consider an 𝑛-bus system shown schematically in the following figure operating at steady load.

The first step towards short circuit computation is to obtain prefault voltages at all buses and
currents in all lines through a load flow study.
Let the prefault bus voltage vector is calculated as

𝑉10
0
0
𝑉𝐵𝑈𝑆 = 𝑉2 (7)
⋮
[𝑉𝑛0 ]
 Let us assume that the 𝑟th bus is faulted through a fault impedance 𝑍𝑓 . The postfault bus voltage
vector will be given by
𝑓 0
𝑉𝐵𝑈𝑆 = 𝑉𝐵𝑈𝑆 + ∆𝑉 (8)

where ∆𝑉 is the vector of changes in bus voltages caused by the fault.

As per step 2, the passive Thevenin network of the system with generators is replaced by
transient/subtransient reactances with their emfs shorted.

As per step 3, excite the passive Thevenin network with – 𝑉𝑟0 in series with 𝑍𝑓 as in the above
figure.
The vector ∆𝑉 comprises the bus voltages of this network.

∆𝑉 = 𝑍𝐵𝑈𝑆 𝐽 𝑓 (9)

where 𝑍𝐵𝑈𝑆 is the bus impedance matrix of the passive Thevenin network
𝑍11 … 𝑍1𝑛
𝑍𝐵𝑈𝑆 =[ ⋮ ⋮ ] (10)
𝑍𝑛1 𝑍𝑛𝑛

and 𝐽 𝑓 is the bus current injection vector.

Since the network is injected with current −𝐼 𝑓 only at the 𝑟th bus, we have
0
0
⋮
𝐽𝑓 = 𝑓 (11)
𝐼𝑟 = −𝐼 𝑓
⋮
[ 0 ]

Substituting. (24) in (22), for the 𝑟th bus ∆𝑉𝑟 = −𝑍𝑟𝑟 𝐼 𝑓

By step 4, the voltage at the 𝑟th bus under fault is
𝑓
𝑉𝑟 = 𝑉𝑟0 + ∆𝑉𝑟0 = 𝑉𝑟0 − 𝑍𝑟𝑟 𝐼 𝑓 (12)

However, this voltage must equal

 𝑓
𝑉𝑟 = 𝑍𝑓 𝐼 𝑓 (13)

From (25) and (26),

𝑍𝑓 𝐼 𝑓 = 𝑉𝑟0 − 𝑍𝑟𝑟 𝐼 𝑓
or
(14)
𝑉𝑟0
𝐼𝑓 =
𝑍𝑟𝑟 + 𝑍𝑓

At the 𝑖th bus (from (22) and (24))

∆𝑉𝑖 = −𝑍𝑖𝑟 𝐼 𝑓
𝑓
𝑖 = 1, 2, … , 𝑛 (15)
𝑉𝑖 = 𝑉𝑖0 − 𝑍𝑖𝑟 𝐼 𝑓

Substituting 𝐼 𝑓 from (27), yields

𝑓 𝑍𝑖𝑟
𝑉𝑖 = 𝑉𝑖0 − 𝑓
𝑉𝑟0 (16)
𝑍𝑟𝑟 + 𝑍

For 𝑖 = 𝑟 in (29)

𝑓 𝑍𝑓
𝑉𝑟 = 𝑉0 (17)
𝑍𝑟𝑟 + 𝑍𝑓 𝑟

In the above relationship 𝑉𝑖0 s, the prefault bus voltages, are assumed to be known from a load flow
study.
It should be observed here that the SC study network of the above figure is different from the
corresponding load flow study network by the fact that the shunt branches corresponding to the
generator reactances do not appear in the load flow study network. Further, in formulating the SC
study network, the load impedances are ignored, these being very much larger than the impedances of
lines and generators. Of course, synchronous motors must be included in 𝑍𝐵𝑈𝑆 formulation for the SC
study.
Postfault currents in lines are given by
𝑓 𝑓 𝑓
𝐼𝑖𝑗 = 𝑌𝑖𝑗 (𝑉𝑖 − 𝑉𝑗 ) (18)

For calculation of postfault generator current, examine the following figure (a) and (b).
From the load flow study (Fig. (a))
Prefault generator output = 𝑃𝐺𝑖 + 𝑗𝑄𝐺𝑖

0 𝑃𝐺𝑖 − 𝑗𝑄𝐺𝑖
∴ 𝐼𝐺𝑖 = (19)
𝑉𝑖0

′ ′ 0
𝐸𝐺𝑖 = 𝑉𝑖 + 𝑗𝑋𝐺𝑖 𝐼𝐺𝑖 (20)

𝑓
From the SC study, 𝑉𝑖 is obtained. It then follows from Fig. (b) that
′ 𝑓
𝑓 𝐸𝐺𝑖 − 𝑉𝑖
𝐼𝐺𝑖 = ′
(21)
𝑗𝑋𝐺𝑖

Example 6: Compute the short circuit solution of Example 5 by using the algorithm for Short Circuit
Studies.
Solution: First of all, the bus admittance matrix for the network of the following figure is formed as
follows:
By inversion 𝑌𝐵𝑈𝑆 yields

Now, the postfault bus voltages can be obtained using (29) as

 The prefault condition being no load, 𝑉10 = 𝑉20 = 𝑉30 = 𝑉40 = 1 pu

Using (27) the fault current can be obtained as

These values agree with those obtained earlier in Example 5. Let us also calculate the short circuit
current in lines 1–3, 1–2, 1–4, 2–4 and 2–3.

For the example on hand this method may appear more involved compared to the heuristic network
reduction method employed in Example 5. This, however, is a systematic method and can be easily
adopted on the digital computer for practical networks of large size. Further, another important feature
of the method is that having computed 𝑍𝐵𝑈𝑆 , all the required short circuit data for a fault on any bus
can be obtained. For example, in this particular system, the fault current for a fault on bus 1 (or bus 2)
will be
𝒁𝑩𝑼𝑺 Formulation
1. Inverting 𝑌𝐵𝑈𝑆

𝑉𝐵𝑈𝑆 = [𝑌𝐵𝑈𝑆 ]−1 𝐽𝐵𝑈𝑆 = 𝑍𝐵𝑈𝑆 𝐽𝐵𝑈𝑆 (22)

2. Current Injection Technique

Equation (35) can be written in the expanded form
𝑉1 = 𝑍11 𝐼1 + 𝑍12 𝐼2 + ⋯ + 𝑍1𝑛 𝐼𝑛
𝑉2 = 𝑍21 𝐼1 + 𝑍22 𝐼2 + ⋯ + 𝑍2𝑛 𝐼𝑛
(23)
…………………………………….
𝑉𝑛 = 𝑍𝑛1 𝐼1 + 𝑍𝑛2 𝐼2 + ⋯ + 𝑍𝑛𝑛 𝐼𝑛

It immediately follows from (36) that

𝑉𝑖
𝑍𝑖𝑗 = | (24)
𝐼𝑖 𝐼1 =𝐼2=⋯=𝐼𝑛 =0
𝐼𝑗 ≠0

Also 𝑍𝑖𝑗 = 𝑍𝑗𝑖 ; (𝑍𝐵𝑈𝑆 is a symmetrical matrix).

As per (37) if a unit current is injected at bus (node) 𝑗, while the other buses are kept open circuited,
the bus voltages yield the values of the 𝑗th column of 𝑍𝐵𝑈𝑆 .
Example 7: Consider the network of the following figure (a) with three buses one of which is a
reference. Evaluate 𝑍𝐵𝑈𝑆

Solution: Inject a unit current at bus 1 keeping bus 2 open circuit, i.e., 𝐼1 = 1 and 𝐼2 = 0 as in Fig.
(b).
Calculating voltages at buses 1 and 2, yields
 Because of the above computational procedure, the 𝑍𝐵𝑈𝑆 matrix is referred to as the ‘open-circuit
impedance matrix’.

3. 𝒁𝑩𝑼𝑺 Building Algorithm

𝑍𝐵𝑈𝑆 building algorithm is a step-by-step programmable technique which proceeds branch by
branch. It has the advantage that any modification of the network does not require complete rebuilding
of 𝑍𝐵𝑈𝑆 .
Consider that 𝑍𝐵𝑈𝑆 has been formulated upto a certain stage and another branch is now added.
𝑍𝑏 =𝑏𝑟𝑎𝑛𝑐ℎ 𝑖𝑚𝑒𝑑𝑎𝑛𝑐𝑒
𝑍𝐵𝑈𝑆 (old) → 𝑍𝐵𝑈𝑆 (new)
Upon adding a new branch, one of the following modification types is used.
1. Type-1 modification: 𝑍𝑏 is added from a new bus to the reference bus (i.e., a new branch is
added and the dimension of 𝑍𝐵𝑈𝑆 goes up by one).
2. Type-2 modification: 𝑍𝑏 is added from a new bus to an old bus (i.e., a new branch is added and
the dimension of 𝑍𝐵𝑈𝑆 goes up by one).
3. Type-3 modification: 𝑍𝑏 is added from a new bus to the reference branch (i.e., a new loop is
formed but the dimension of 𝑍𝐵𝑈𝑆 does not change).
4. Type-4 modification: 𝑍𝑏 connects two old buses (i.e., new loop is formed but the dimension of
𝑍𝐵𝑈𝑆 does not change).
4. Type-5 modification: 𝑍𝑏 connects two new buses (𝑍𝐵𝑈𝑆 remains unaffected in this case).
Assume 𝑖 and 𝑗 are old buses, and 𝑟 and 𝑘 are reference bus and new bus respectively.

Type-1 Modification
Following figure shows a passive (linear) 𝑛-bus network in which branch with impedance 𝑍𝑏 is
added to the new bus 𝑘 and the reference bus 𝑟.
𝑉𝑘 = 𝑍𝑏 𝐼𝑘
𝑍𝑘𝑖 = 𝑍𝑖𝑘 = 0; 𝑖 = 1, 2, … , 𝑛
𝑍𝑘𝑘 = 𝑍𝑏
0
𝑍𝐵𝑈𝑆 (old) |⋮
𝑍𝐵𝑈𝑆 (new) = [ ] (25)
0
̅̅̅̅̅̅̅̅̅̅̅̅
0 … 0 ̅̅̅̅
|𝑍𝑏

Type-2 Modification
𝑍𝑏 is added from new bus 𝑘 to the old bus 𝑗.

Rearranging, yields

Hence

𝑍1𝑗
𝑍𝐵𝑈𝑆 (old) | ⋮
𝑍𝐵𝑈𝑆 (new) = 𝑍𝑛𝑗 (26)
̅̅̅̅̅̅̅̅̅̅̅
[̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑍𝑗1 … 𝑍𝑗𝑛 |𝑍𝑗𝑗 + 𝑍𝑏 ]

Type-3 Modification
 𝑍𝑏 connects an old bus (𝑗) to the reference bus (𝑟).

𝑍1𝑗
1
𝑍𝐵𝑈𝑆 (new) = 𝑍𝐵𝑈𝑆 (old) − [ ⋮ ] [𝑍𝑗1 … 𝑍𝑗𝑛 ] (27)
𝑍𝑗𝑗 + 𝑍𝑏 𝑍
𝑛𝑗

Type-4 Modification
𝑍𝑏 connects two old buses.

𝑍𝐵𝑈𝑆 (new) = 𝑍𝐵𝑈𝑆 (old)

𝑍1𝑖 − 𝑍1𝑗 (28)
1
− [ ⋮ ] [(𝑍1𝑖 − 𝑍𝑗1 ) … (𝑍𝑖𝑛 − 𝑍𝑗𝑛 )]
𝑍𝑏 + 𝑍𝑖𝑖 + 𝑍𝑗𝑗 − 2𝑍𝑖𝑗 𝑍 − 𝑍
𝑛𝑖 𝑛𝑗

Example 8: For the three-bus network shown in the following figure, build 𝑍𝐵𝑈𝑆 .
Solution:

Step 1: Add branch 𝑍1𝑟 = 0.25 (from bus 1 (new) to bus 𝑟)

 𝑍𝐵𝑈𝑆 = [0.25] (i)

Step 2: Add branch 𝑍21 = 0.1 (from bus 2 (new) to bus 1 (old)); type-2 modification.
0.25 0.25
𝑍𝐵𝑈𝑆 = [ ] (i)
0.25 0.35
Step 3: Add branch 𝑍13 = 0.1 (from bus 3 (new) to bus 1 (old)); type-2 modification.
0.25 0.25 0.25
𝑍𝐵𝑈𝑆 = [0.25 0.35 0.25] (i)
0.25 0.25 0.35
Step 4: Add branch 𝑍2𝑟 (from bus 2 (old) to bus 𝑟); type-3 modification.
0.25 0.25 0.25 1 0.25
𝑍𝐵𝑈𝑆 = [0.25 0.35 0.25] − [0.35] [0.25 0.35 0.25]
0.35 + 0.25
0.25 0.25 0.35 0.25
(i)
0.1458 0.1042 0.1458
= [ 0.1042 0.1458 0.1042]
0.1458 0.1042 0.2458
Step 5: Add branch 𝑍23 = 0.1 (from bus 2 (old) to bus 3 (old)); type-4 modification.

𝑍𝐵𝑈𝑆
0.1458 0.1042 0.1458
= [ 0.1042 0.1458 0.1042]
0.1458 0.1042 0.2458
1 −0.0417 (i)
− [ 0.0417 ] [−0.0417 0.0417 −0.1417]
0.1 + 0.1458 + 0.2458 − 2 × 0.1042
−0.1417
0.1397 0.1103 0.1250
= [ 0.1103 0.1397 0.1250]
0.1250 0.1250 0.1750
Opening a line (line 3-2): This is equivalent to connecting an impedance – 0.1 between bus 3 (old)
and bus 2 (old) i.e., type-4 modification.
 𝑍𝐵𝑈𝑆
0.1397 0.1103 0.1250
= [ 0.1103 0.1397 0.1250]
0.1250 0.1250 0.1750
1 0.0147 (i)
− [−0.0147] [0.0147 −0.0147 0.0500]
(−0.1) + 0.175 + 0.1397 − 2 × 0.125
0.0500
0.1458 0.1042 0.1458
= [ 0.1042 0.1458 0.1042]
0.1458 0.1042 0.2458
(same as in step 4)

Example 9: For the power system shown in the following figure, the pu reactance are shown therein.
For a solid three-phase fault on bus 3, calculate
(a) Fault current
𝑓
(b) 𝑉1 and 𝑉 𝑓
𝑓 𝑓 𝑓
(c) 𝐼12 , 𝐼13 and 𝐼23
𝑓 𝑓
(d) 𝐼𝐺−1 and 𝐼𝐺2
Assume prefault voltage to be 1 pu.

Solution: The Thevenin passive network for this system is drawn in Example 8. Its 𝑍𝐵𝑈𝑆 given in Eq.
(iv) of Example 8.
(a) As per (27),

(b) As per (28),

 The two voltages are equal because of the symmetry of the given power network.
(c) From (31),

(d) As per (34)