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Data Flow Modelling in VHDL

This document provides an introduction to data flow modeling in VHDL. It discusses continuous assignments which describe combinational logic using assignment statements rather than gates. Continuous assignments can be regular or implicit. Delays are also discussed, including regular assignment delay, implicit continuous assignment delay, and net declaration delay. Expressions use operators and operands to model logic functions. An example of a 4-to-1 multiplexer is provided to demonstrate data flow modeling.

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33 views12 pages

Data Flow Modelling in VHDL

This document provides an introduction to data flow modeling in VHDL. It discusses continuous assignments which describe combinational logic using assignment statements rather than gates. Continuous assignments can be regular or implicit. Delays are also discussed, including regular assignment delay, implicit continuous assignment delay, and net declaration delay. Expressions use operators and operands to model logic functions. An example of a 4-to-1 multiplexer is provided to demonstrate data flow modeling.

Uploaded by

Yvanne Esquia Cureg
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Data Flow Modelling

Data Flow Modelling


Module 3

Amacdalino2020 SY 2020- 2021 CompEng 314 – Introduction to HDL


Data Flow Modelling

Table of Contents
Introduction ............................................................................................................................................... 1
Learning Outcome ................................................................................................................................... 1
Learning Content...................................................................................................................................... 1
Data Flow Modelling ............................................................................................................................. 2
A. Continuous Assignments .......................................................................................................... 2
Implicit Continuous Assignment.................................................................................................... 2
B. Delays ......................................................................................................................................... 3
Regular Assignment Delay ............................................................................................................ 3
Implicit Continuous Assignment Delay ........................................................................................ 4
Net Declaration Delay................................................................................................................... 5
C. Expressions, Operators, and Operands .................................................................................. 6
Expressions ...................................................................................................................................... 6
Operands ........................................................................................................................................ 7
Operators ........................................................................................................................................ 7
D. Example ..................................................................................................................................... 8
Dataflow 4-to-1 Multiplexer (Using Logic Equations) .................................................................. 8
Teaching and Learning Activities.......................................................................................................... 10
Recommended Learning Materials and Resources ........................................................................... 10
Assessment Task ...................................................................................................................................... 10

i
Data Flow Modelling

Module 3 - Data Flow Modelling


Introduction
This module introduces VHDL programming using the Data Flow Model. It presents
continuous assignments including different types of delays, expressions, operators and
operands. Examples are also provided.

Learning Outcome
At the end of the lesson, you are expected to:

• Describe the continuous assignment (assign) statement, restrictions on the assign


statement, and the implicit continuous assignment statement.
• Explain assignment delay, implicit assignment delay, and net declaration delay for
continuous assignment statements.
• Define expressions, operators, and operands.
• List operator types for all possible operations-arithmetic, logical, relational, equality,
bitwise, reduction, shift, concatenation, and conditional.
• Use dataflow constructs to model practical digital circuits in Verilog.

Learning Content

Data Flow Modelling


A. Continuous Assignments
Implicit Continuous Assignment

B. Delays
Regular Assignment Delay
Implicit Continuous Assignment Delay
Net Declaration Delay

C. Expressions, Operators, and Operands


Expressions
Operands
Operators

D. Example
Dataflow 4-to-1 Multiplexer (Using Logic Equations) 8

1
Data Flow Modelling

Data Flow Modelling


• provides the means of describing combinational circuits by their function rather than
by their gate structure
• describes hardware in terms of the flow of data from input to output
• provides a powerful way to implement a design
• uses a number of operators that act on operands to produce the desired results
• Example description of AND gate using dataflow:
module and_gate(a,b,out);
input a,b;
output out;

assign out = a&b;


endmodule
• In the above code, we executed the functionality of the AND gate with the help of
the AND (&) operator. That is what dataflow modeling is about. It utilizes operators
that act on operands and gives the desired relationship between output and input.

A. Continuous Assignments
• the most basic statement in dataflow modeling, used to drive a value onto a net
• replaces gates in the description of the circuit and describes the circuit at a higher
level of abstraction.
• A continuous assignment statement starts with the keyword assign.

//Syntax of assign statement in the simplest form

< continuous_assign >

: : = assign < drive_strength > ? < delay > ? < list_of_assignments > ;

Example of Continuous Assignment


Continuous assign out is a
net. i1 and i2 are nets. assign out = i1 & i2 ;

Concatenation. Left-hand side


assign { c_out , sum[ 3 : 0 ] } = a [ 3 : 0 ] + b [ 3 :
is a concatenation of a scalar net
0 ] + c_in ;
and a vector net

Implicit Continuous Assignment


Instead of declaring a net and then writing a continuous assignment on the net.
Verilog provides a shortcut by which a continuous assignment can be placed on a
net when it is declared. There can be only one implicit declaration assignment per
net because a net is declared only once.

2
Data Flow Modelling

Example of Implicit Continuous Assignment


Regular continuous
assignment wire out ;

assign out = in1 & in2 ;

Same effect is achieved by an


Implicit continuous assignment
wire out = in1 & in2 ;

B. Delays
Delay value control the time between the change in a right-hand-side operand and
when the new value is assigned to the left-hand-side.

Regular Assignment Delay


The first method is to assign a delay value in a continuous assignment statement.
The delay value is specified after the keyword assign.

Ex1. Regular Assignment Delay program

1. This example shows inertial delay. The waveform is generated by simulating


the assign statement. It shows the delay on signal out. Note the following
changes. When signal in1 and in2 go high at time 20, out goes to a high
10-time units later (time = 30).
2. When in1 goes to low at 60, out changes to low at 70.
3. However, in1 changes to high at 100, but it goes down to low before10
time units have elapsed.
4. Hence, at the time of recompilation, 10 units after time 100, in1 is 0. Thus,
out gets the value 0. A pulse of width less than the specified assignment
delay is not propagated to the output.
i. Verilog Code

Declaration
module regular_delay (out, in1, in2);
I/O port
output out;
input in1, in2;

Delay in a continuous
assign #10 out = in1 & in2;
endmodule

3
Data Flow Modelling

ii. Test Stimulus Code module stimulus;

wire OUT;
reg IN1, IN2;

initial
begin
Input test value IN1 = 0; IN2= 0;
#20 IN1=1; IN2= 1;
#40 IN1 = 0;
#40 IN1 = 1;
#5 IN1 = 0;
#150 $stop;
end

initial
Shown the result $monitor("out", OUT, "in1", IN1, "in2",
IN2);

Call regular_delay module regular_delay rd1(OUT, IN1, IN2);

endmodule

iii. Simulation Waveform

Implicit Continuous Assignment Delay


An equivalent method is using an implicit continuous assignment to specify
both a delay and an assignment on the net.

Ex2. Implicit Continuous Assignment

i. Verilog Code
module implicit_delay (out, in1, in2);

output out;
Delay in a continuous assign
input in1, in2;

wire #10 out = in1 & in2;

endmodule

4
Data Flow Modelling

ii. Test Stimulus Code

module stimulus;

wire OUT;
reg IN1, IN2;

Input test value initial


begin
IN1 = 0; IN2= 0;
#20 IN1=1; IN2= 1;
#40 IN1 = 0;
#40 IN1 = 1;
#5 IN1 = 0;
#150 $stop;
end
Shown the result
initial
$monitor("out", OUT, "in1", IN1, "in2",
IN2);
Call regular_delay module

implicit_delay rd1(OUT, IN1, IN2);

endmodule
iii. Simulation Waveform

Net Declaration Delay


A delay can be specified on a net when it is declared without putting a continuous
assignment on the net. If a delay is specified on a net out, then any value change
applied to the net out is delayed accordingly. Net declaration delays can also be
used in gate-level modeling.
Ex3. Net Declaration Delay Program

i. Verilog Code module implicit_delay (out, in1, in2);

output out;

input in1, in2;

No Delay in a assign out = in1 & in2;


continuous
assignment endmodule

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Data Flow Modelling

ii. Test Stimulus Code

Declare the delay module stimulus;


on the net.
wire #10 OUT;
reg IN1, IN2;

initial
Input test value begin
IN1 = 0; IN2= 0;
#20 IN1=1; IN2= 1;
#40 IN1 = 0;
#40 IN1 = 1;
#5 IN1 = 0;
#150 $stop;
end

Shown the result initial


$monitor("out", OUT, "in1", IN1, "in2",
IN2);
Call net_declare module
net_delare rd1(OUT, IN1, IN2);

endmodule

iii. Simulation Waveform

C. Expressions, Operators, and Operands


Dataflow modeling describes the design in terms of expressions instead of primitive
gates. expressions, operators, and operands form the basis of dataflow modeling.

Expressions
Expressions are constructs that combine operators and operands to produce a result.

//Examples of expressions . Combine operators and operands a ^ b

addr1[20:17] + addr2[20:17]

in1 | in2

6
Data Flow Modelling

Operands
Operands can be any one of the data types. Some constructs will take only certain
types of operands.

integer count , final_count ;


count is an
integer operand final_count = count + 1 ;

a and b are real a , b , c ;


real operands
c=a–b;

Operators
The operator act on the operands to produce desired results. Verilog provides
various types of operators.

Operator Operator Operation Number of


Type Symbol Performed Operands
Arithmetic * Multiply Two
/ Divide Two
+ Add Two
- Subtract Two
% Modulus Two
Logical ! Logical Negation One
&& Logical AND Two
|| Logical OR Two
Relational > Greater Than Two
< Less Than Two
>= Greater Than or Equal Two
<= Less Than or Equal Two
Equality == Equality Two
!= Inequality Two
=== Case Equality Two
!== Case Inequality Two
Bitwise ~ Bitwise Negation One
& Bitwise AND Two
| Bitwise OR Two
^ Bitwise XOR Two
^~ or ~^ Bitwise XNOR Two
Reduction & Reduction AND One
~& Reduction NAND One
| Reduction OR One
~| Reduction NOR One
^ Reduction XOR One
^~ or ~^ Reduction XNOR One
Shift >> Right Shift Two
<< Left Shift Two
Concatenation { } Concatenation Any Number
Replication {{}} Replication Any Number
Conditional ?: Condition Three

7
Data Flow Modelling

D. Example

Dataflow 4-to-1 Multiplexer (Using Logic Equations)


i. Verilog Code
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);

Port declarations from the


output out;
I/O diagram
input i0, i1, i2, i3;

input s1, s0;


Set assignment function

assign out = (~s1 & ~s0 & i0) |

(~s1 & s0 & i1) |

(s1 & ~s0 & i2) |

(s1 & s0 & i3) ;

endmodule

ii. Test Stimulus Code

Define the stimulus module module stimulus;


(no ports)
reg IN0, IN1, IN2, IN3;
Declare variables to be reg S1, S0;
Connected to the inputs
wire OUTPUT;
Declare the output wire
mux4_to_1 mymux(OUTPUT, IN0, IN1, IN2, IN3, S1,
Instantiated the S0);
multiplexer
initial
begin
Stimulate the inputs
IN0 = 1; IN1 = 0; IN2 = 1; IN3 = 0;
#1 $display("IN0= %b, IN1= %b, IN2= %b,
Set input lines IN3= %b\n",IN0,IN1,IN2,IN3);

S1 = 0; S0 = 0;
#1 $display("S1 = %b, S0 = %b, OUTPUT =
Choose IN0 %b \n", S1, S0, OUTPUT);

S1 = 0; S0 = 1;
#1 $display("S1 = %b, S0 = %b, OUTPUT =
Choose IN1
%b \n", S1, S0, OUTPUT);

S1 = 1; S0 = 1;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n",
S1, S0, OUTPUT); 8
Data Flow Modelling

Choose IN2 S1 = 1; S0 = 0;
#1 $display("S1 = %b, S0 = %b, OUTPUT =
%b \n", S1, S0, OUTPUT);

Choose IN3
S1 = 1; S0 = 1;
#1 $display("S1 = %b, S0 = %b, OUTPUT =
%b \n", S1, S0, OUTPUT);

end

endmodule

iii. Simulation Waveform

iv. Simulation Result

Other examples will be uploaded.

9
Data Flow Modelling

Teaching and Learning Activities

• What is data flow modelling?


• What are continuous assignments?
• Define the different types of delays.
• Define expressions, operators, and operands.
• What are the nine types of operators? Differentiate each.

Recommended Learning Materials and Resources


• Digital Design with An Introduction to the Verilog HDL Fifth Edition by M. Morris Mano
and Michael D. Ciletti
• [Link]
documents/53e0c6cbe413016f23443704_INFIEP_33/5/LM/33-5-LM-V1-
S1__dataflowmodelingchep4.pdf
• [Link]

Assessment Task
***To be uploaded separately.

10

Common questions

Powered by AI

Operators in Verilog are categorized based on their functional roles: arithmetic operators (+, -, *, /, %) manipulate numerical values; logical operators (&&, ||, !) handle Boolean logic; relational operators (>, <, >=, <=) compare values; equality operators (==, !=, ===, !==) check for equality; bitwise operators (&, |, ^, ~) perform operations on binary digits; reduction operators (&, |, ^) reduce multiple bits to a single bit; shift operators (<<, >>) move bits left or right; and conditional operators ( ? : ) act as inline if-else statements . Each type serves specific computational and logic manipulation purposes.

Expressions in Verilog are constructs formed by combining operators and operands to produce a result that defines circuit behavior . Operators perform various operations such as arithmetic, logical, and bitwise, while operands are the data items on which these operations are performed . Together, they enable data flow modeling to describe how data moves and is processed in a digital circuit, emphasizing the functional aspect rather than the structural.

In Verilog's data flow modeling, operators act on operands to produce outputs that match the desired circuit behavior. This modeling style expresses circuit functionality through continuous assignments and logical expressions rather than describing interconnections using gates . Operators such as arithmetic, logical, relational, and bitwise operate on operands (variables or constants) to form expressions that dictate the data flow between inputs and outputs . This abstraction allows for a higher-level description of digital circuits.

Regular assignment delay in Verilog involves specifying a delay value in a continuous assignment statement, affecting when the output changes relative to the input . For example, if the delay is set to 10 time units, the output will not change until 10 time units after the input changes. Implicit continuous assignment delay achieves the same effect but involves declaring the delay alongside the assignment in a wire declaration . The implicit method simplifies the syntax by avoiding the need to separate declaration and delay specification.

Data flow modeling in Verilog offers advantages over gate-level modeling by allowing a higher level of abstraction where the emphasis is on functional behavior rather than the physical implementation of gates . This abstraction simplifies complex designs, makes them easier to read and maintain, and accelerates the design process by focusing on data transformations instead of gate connections. It also facilitates the modeling of more complex logic by providing constructs that describe the desired relationships between inputs and outputs directly.

Understanding implicit continuous assignments in Verilog is important because they provide syntactic convenience by allowing both net declaration and assignment in a single line . This reduces code verbosity and enhances readability, which is particularly beneficial in complex designs where numerous nets are involved. Implicit assignments also enforce a single assignment per net, which helps avoid potential conflicts or errors in signal assignment, ensuring that design intentions are clear and maintainable.

Continuous assignments in Verilog enhance the abstraction by describing the output of a net as a function of its inputs through high-level expressions rather than detailing the gate-level connections . This abstraction allows for a more intuitive representation of the circuit's behavior, making the design process more efficient by reducing the complexity involved in specifying detailed component interconnections. By using 'assign' statements, designers can directly implement complex logic functions, streamlining both the design and verification phases.

Data flow modeling simplifies the implementation of a 4-to-1 multiplexer in Verilog by using logical expressions to define output behavior based on inputs and selection lines . Through the use of 'assign' statements and operators like AND, OR, and NOT, data flow modeling allows a concise expression of the multiplexer's logic function. This approach reduces the need for describing the multiplexer's function through explicit gate-level interconnections, thus streamlining the coding process and making the design more understandable.

Net declaration delay allows a delay to be applied directly to a net when it is declared, without requiring a continuous assignment. This feature of Verilog enhances data flow modeling by enabling designers to introduce precise timing delays in the simulation of circuits, which is useful for mimicking real-world propagation delays . By specifying delays at the net level, circuits can effectively model the effects of signal propagation, ensuring that simulation results are more representative of the actual hardware behavior.

Verilog's data flow modeling components contribute to teaching digital design concepts effectively by allowing students to focus on functional behavior rather than detailed hardware descriptions . Providing tools such as continuous assignments, expressions, and operators, encourages students to understand circuit behavior through logical relationships and data transformations. This high-level abstraction helps in grasping complex digital concepts without getting bogged down by physical gate layouts, thus fostering a deeper understanding of digital logic and circuit design principles.

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