EE 120 LECTURE NOTES CHAPTE R 5: SEQUENTIAL LOGIC CIRCUITS 5.
Chapter Objectives:
This chapter aims to help the student to:
differentiate the two types of sequential circuits
identify the different flip-flops used in sequential circuits
determine how flip-flops are used for data storage and transfer as well as other applications
relate the Schmitt-trigger inverter to the standard inverter
classify the types of monostable multivibrators
analyze and design sequential circuits
I. TERMS AND DEFINITIONS
flip-flop – a memory element with two stable states, known more formally as a bistable multivibrator
– a device that can be triggered so that its output remains high (one stable state) or triggered again so
that its output remains low (the other state).
– serves as a storage device in digital systems
– also called a bistable
latch – a type of memory storage device that has two stable states and is normally placed in a category separate
from flip-flops (although this is the simplest type of flip-flop)
– main difference from a flip-flop circuit is the method used for changing states.
triggering – momentary change at the input that switches state of the flip-flop
state transition diagram – circles drawn to show how the states of the flip-flops change with each applied clock
pulse
mod number – number that indicates the number of states in the counting sequence of a counter
– also indicates the frequency division obtained from the last flip-flop
II. GENERAL DIGITAL SYSTEM
recalling from chapter 1 definitions:
combinational logic circuits – logic circuits whose output only depends on the state of its inputs at a given
time; output does not depend on previous output states.
sequential circuits – logic circuits whose output state depends on the inputs and state of memory elements;
next state of memory elements is a function of the state of the previous output
EE 120 LECTURE NOTES CHAPTE R 5: SEQUENTIAL LOGIC CIRCUITS 5.2
III. TYPES OF SEQUENTIAL CIRCUITS
1. SYNCHRONOUS SEQUENTIAL CIRCUIT
- system whose behavior can be defined from the knowledge of its signals at discrete instances of time
- clocked sequential circuit that changes state at the clock pulse transition
2. ASYNCHRONOUS SEQUENTIAL CIRCUIT
- system that depends upon the order in which its input signals change and can be affected anytime
- faster but is more complicated and prone to malfunction
IV. FLIP-FLOP CIRCUITS
1. GENERAL DESCRIPTION
output states:
SET – also called HIGH or 1 state wherein
RESET – also called LOW or 0 state wherein
2. RS LATCH (SR LATCH OR SC LATCH)
logic symbol truth table (active high)
R S
0 0 no change
0 1 1 0
1 0 0 1
1 1 invalid
a) NOR-Gate Latch
logic diagram truth table
S R
1 0 1 0
0 0 1 0
0 1 0 1
0 0 0 1
1 1 0 0
EE 120 LECTURE NOTES CHAPTE R 5: SEQUENTIAL LOGIC CIRCUITS 5.3
b) NAND-Gate Latch
logic diagram truth table
S R
1 0 0 1
1 1 0 1
0 1 1 0
1 1 1 0
0 0 1 1
c) Latch Waveforms:
NOR-gate latch waveforms: NAND-gate latch waveforms:
NAND-gate latch is active low whereas the NOR-gate latch is active high.
d) Alternate representation of NAND-gate latch:
logic diagram
block diagram
EE 120 LECTURE NOTES CHAPTE R 5: SEQUENTIAL LOGIC CIRCUITS 5.4
e) Applications:
(1) switch debouncing circuit using NAND latch
mechanical switch
switch debouncing circuit
(2) light beam interruption detector alarm using NOR latch
EE 120 LECTURE NOTES CHAPTE R 5: SEQUENTIAL LOGIC CIRCUITS 5.5
3. CLOCK SIGNAL
– used to control change of states of flip-flops in synchronous systems
a) Modes of Triggering
(1) Level Triggering
- flip-flops change during pulse duration
(a) Positive-Level Triggering
- accepts an input at logic 1 of the clock pulse
(b) Negative Level Triggering
- accepts an input at logic 0 of the clock pulse
(2) Edge Triggering
- flip-flops change during pulse transition
(a) Positive-Edge Triggering
- accepts an input during the positive-going edge
- also called “positive-going transition” or PGT
(b) Negative-Edge Triggering
- accepts an input during the negative-going edge
- also called “negative-going transition” or NGT
4. CLOCKED (GATED) FLIP-FLOPS
PGT activated FF
NGT activated FF
EE 120 LECTURE NOTES CHAPTE R 5: SEQUENTIAL LOGIC CIRCUITS 5.6
a) Clocked SR flip-flop
- modified SR latch providing control input that determines when the state of the circuit is to be changed.
block diagram logic diagram
NAND gates 1 & 2 represent a NAND latch
and NAND gates 3 & 4 represent the pulse
steering circuit
truth tables
S R CLK
0 0 No change
0 1 0
1 0 1
1 1 invalid
alternate representation of an edge-triggered SR flip-flop
Edge detector circuit:
PGT NGT
EE 120 LECTURE NOTES CHAPTE R 5: SEQUENTIAL LOGIC CIRCUITS 5.7
b) Clocked JK flip-flop
- controls the flip-flop in the same way that the SR flip-flop does, with the exception that it does not
produce an ambiguous output when both inputs are high.
block diagram logic diagram
truth tables
J K CLK
0 0 No change
0 1 0
1 0 1
1 1 toggle
alternate representation of an edge-triggered SR flip-flop
NAND gates 1 & 2 represent a NAND latch and NAND
gates 3 & 4 represent the pulse steering circuit
EE 120 LECTURE NOTES CHAPTE R 5: SEQUENTIAL LOGIC CIRCUITS 5.8
c) Clocked D flip-flop
- eliminates undesirable condition brought about by the indeterminate state (R=S=1) by ensuring that R
and S are never high at the same time.
block diagram truth tables
logic diagram
D CLK
0 0
1 1
D FF implemented using SC FF D FF implemented using JK FF
d) Clocked T flip-flop
-single input version of the JK flip-flop
- designation „T‟ comes from the ability of the flip-flop to „toggle‟
block diagram
truth tables
T CLK
0 no change
1 toggle
logic diagram
EE 120 LECTURE NOTES CHAPTE R 5: SEQUENTIAL LOGIC CIRCUITS 5.9
clocked FF waveforms:
5. ASYNCHRONOUS INPUTS
- operates independently from synchronous inputs (S, R, J, K, D, T) and clock input
- overrides synchronous inputs
- designations for asynchronous inputs: DC SET and DC CLEAR
– DC SET, DIRECT SET (SD) or PRESET (PRE): sets flip-flop
– DC CLEAR, DIRECT RESET (RD) or CLEAR (CLR): resets flip-flop
SET CLR FF RESPONSE
0 0 not used
0 1 Q=1
1 0 Q=0
1 1 Clocked operation
Q will respond to J, K and CLK if
SET=CLEAR=1
EE 120 LECTURE NOTES CHAPTE R 5: SEQUENTIAL LOGIC CIRCUITS 5.10
asynchronous FF waveforms:
6. MASTER-SLAVE FLIP-FLOP (PULSE-TRIGGERED)
- data is entered into the flip-flop at the leading edge of the clock pulses, but the output does not reflect the
input state until the trailing edge
- does not allow data to change while the clock pulse is active
- has largely been replaced by edge-triggered devices
EE 120 LECTURE NOTES CHAPTE R 5: SEQUENTIAL LOGIC CIRCUITS 5.11
V. DATA STORAGE AND TRANSFER
1. SYNCHRONOUS DATA TRANSFER
2. ASYNCHRONOUS DATA TRANSFER
3. PARALLEL DATA TRANSFER
Parallel Data Transfer from Register X to Register Y
EE 120 LECTURE NOTES CHAPTE R 5: SEQUENTIAL LOGIC CIRCUITS 5.12
4. SERIAL DATA TRANSFER: SHIFT REGISTERS
Four-Bit Shift Register
Serial Data Transfer Between Registers
X2 X1 X0 Y 2 Y 1 Y 0 Data is transferred one bit at a time for
1 0 1 0 0 0 every clock pulse.
0 1 0 1 0 0
0 0 1 0 1 0
0 0 0 1 0 1
EE 120 LECTURE NOTES CHAPTE R 5: SEQUENTIAL LOGIC CIRCUITS 5.13
5. MICROCOMPUTER APPLICATION
VI. FREQUENCY DIVISION AND COUNTING
JK flip-flop wired as a 3-bit Binary Counter