Verilog HDL
ICARUS VERILOG
1
Icarus Verilog
◦ A Verilog simulation and synthesis tool.
◦ Operates as a compiler that compiles source code written in Verilog into some
target format.
◦ For simulation, the compiler can generate an intermediate form called vvp
assembly.
◦ For synthesis, the compiler generates netlists.
More info @ [Link]
2
Integrated Circuit Design Processes
Formal and precise description of a complex circuit in
an abstract level
Automated analysis and simulation
Automated synthesis into a netlist (specification of
electronic component and how they are connected)
Automated placing of electronic components and
routing of wires to be sent for fabrication
How we do?
Formal and precise description of a Write the Verilog source code in a text
complex circuit in an abstract level
editor
Automated analysis and simulation Using the Icarus Verilog
Automated synthesis into a netlist
(specification of electronic component and Using the Icarus Verilog
how they are connected)
(not done in this course)
Automated placing of electronic
components and routing of wires to be
sent for fabrication
4
Using Icarus Verilog for Simulation
Verilog source code
( filename.v)
iverilog -o [Link] file.v
vvp assembly
([Link])
vvp [Link]
Simulation output
5
Installing Icarus Verilog
In Ubuntu based Linux :
◦ sudo apt-get install Verilog
For Windows :
◦ Install the setup at [Link]
◦ Set the path environmental variable if not automatically set.
A full guide for all operating systems :
◦ [Link]