MICROPROCESSOR 49 IMPORTANT MCQ [Link].

in

Q.1 If the crystal oscillator is operating at 15 MHz, the PCLK output of 8284 is
(A) 2.5 MHz. (B) 5 MHz.
(C) 7.5 MHz. (D) 10 MHz.

Ans: (A)

Q.2 In which T-state does the CPU sends the address to memory or I/O and the ALE signal
for demultiplexing
(A) T1. (B) T2.
(C) T3. (D) T4.

Ans, During the first clocking period in a bus cycle, which is called T1, the address of
the memory or I/O location is sent out and the control signals ALE, DT/R’ and IO/M’
are also output. Hence answer is (A).

Q.3 If a 1M ×1 DRAM requires 4 ms for a refresh and has 256 rows to be refreshed, no
more than _ of time must pass before another row is refreshed.
(A) 64 ms. (B) 4 ns.
(C) 0.5 ns. (D) 15.625 µs .

Ans Answer is (B)

Q.4 In a DMA write operation the data is transferred

(A) from I/O to memory. (B) from memory to I/O.
(C) from memory to memory. (D) from I/O to I/O.

Ans A DMA writes operation transfers data from an I/O device to memory. Hence
answer is (A).
Q.5 Which type of JMP instruction assembles if the distance is 0020 h bytes
(A) near. (B) far.
(C) short. (D) none of the above.

Ans The three byte near jump allows a branch or jump within ± 32K bytes. Hence
answer is (A).

Q.6 A certain SRAM has CS = 0 , WE = 0 and OE = 1. In which of the following

modes this SRAM is operating

(A) Read (B) Write

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(C) Stand by (D) None of the above

[Link]
Ans For CS’=WE’=0, write operation. Hence answer is (B).

Q.7 Which of the following is true with respect to EEPROM?

(A) contents can be erased byte wise only.
(B) contents of full memory can be erased together.
(C) contents can be erased using ultra violet rays
(D) contents can not be erased

Ans Answer is (C).

Q.8 Pseudo instructions are basically

(A) false instructions.
(B) instructions that are ignored by the microprocessor.
(C) assembler directives.
(D) instructions that are treated like comments.

Ans Pseudo-instructions are commands to the assembler. All pseudo-operations start

with a period. Pseudo-instructions are composed of a pseudo-operation which may be
followed by one or more expressions. Hence answer is (C).

Q.9 Number of the times the instruction sequence below will loop before coming out of
loop is
MOV AL, 00h
A1: INC AL
JNZ A1
(A) 00 (B) 01
(C) 255 (D) 256

Ans Answer is (D)

Q.10 What will be the contents of register AL after the following has been executed
MOV BL, 8C
MOV AL, 7E
ADD AL, BL
(A) 0A and carry flag is set (B) 0A and carry flag is reset
(C) 6A and carry flag is set (D) 6A and carry flag is reset

Ans, Result is 1,0A. Hence answer is (A).

Q.11 Direction flag is used with

(A) String instructions. (B) Stack instructions.
(C) Arithmetic instructions. (D) Branch instructions.

Ans The direction flag is used only with the string instructions. Hence answer is (A).

Q.12 Ready pin of a microprocessor is used

(A) to indicate that the microprocessor is ready to receive inputs.
(B) to indicate that the microprocessor is ready to receive outputs.
(C) to introduce wait states.
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(D) to provide direct memory access.

[Link]
Ans This input is controlled to insert wait states into the timing of the microprocessor.
Hence answer is (C).

Q.13 These are two ways in which a microprocessor can come out of Halt state.
(A) When hold line is a logical 1.
(B) When interrupt occurs and the interrupt system has been enabled.
(C) When both (A) and (B) are true.
(D) When either (A) or (B) are true.

Ans Answer is (A)

Q.14 In the instruction FADD, F stands for

(A) Far. (B) Floppy.
(C) Floating. (D) File.

Ans Adds two floating point numbers. Hence answer is (C).

Q.15 SD RAM refers to

(A) Synchronous DRAM (B) Static DRAM
(C) Semi DRAM (D) Second DRAM

Ans, Answer is (A)

Q.16 In case of DVD, the speed is referred in terms of n X (for example 32 X). Here, X
refers to
(A) 150 KB/s (B) 300 KB/s
(C) 1.38 MB/s (D) 2.4 MB/s

Ans Answer is (C).

Q.17 Itanium processor of Intel is a

(A) 32 bit microprocessor. (B) 64 bit microprocessor.
(C) 128 bit microprocessor. (D) 256 bit microprocessor.

Ans The Itanium is a 64-bit architecture microprocessor. Hence answer is (B).

Q.18 LOCK prefix is used most often

(A) during normal execution. (B) during DMA accesses
(C) during interrupt servicing. (D) during memory accesses.

Ans LOCK is a prefix which is used to make an instruction of 8086 non-interruptable.

Hence answer is (C).

Q.19 The Pentium microprocessor has execution units.

(A) 1 (B) 2
(C) 3 (D) 4

Ans The Pentium microprocessor is organized with three execution units. One
executes floating-point instructions, and the other two (U-pipe and V-pipe) execute
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integer instructions. Hence answer is (C).

[Link]
Q.20 EPROM is generally erased by using
(A) Ultraviolet rays (B) infrared rays
(C) 12 V electrical pulse (D) 24 V electrical pulse

Ans The EPROM is erasable if exposed to high-intensity ultraviolet light for about 20
minutes or less. Hence answer is (A)

Q.21 Signal voltage ranges for a logic high and for a logic low in RS-232C standard are
(A) Low = 0 volt to 1.8 volt, high = 2.0 volt to 5 volt
(B) Low =-15 volt to –3 vol, high = +3 volt to +15 volt
(D) Low = +3 volt to +15 volt, high = -3 volt to -15 volt
(E) Low = 2 volt to 5.0 volt, high = 0 volt to 1.8 volt

Ans Answer is (B)

Q.22 The PCI bus is the important bus found in all the new Pentium systems because
(A) It has plug and play characteristics
(B) It has ability to function with a 64 bit data bus
(C) Any Microprocessor can be interfaced to it with PCI controller or bridge
(D) All of the above

Ans, Answer is (D).

Q.23 Which of the following statement is true?
(A) The group of machine cycle is called a state.
(B) A machine cycle consists of one or more instruction cycle.
(C) An instruction cycle is made up of machine cycles and a machine cycle is
made up of number of states.
(D) None of the above

Ans An instruction cycle consists of several machine cycles. Hence Answer is (B).

Q.24 8251 is a
(A) UART
(B) USART
(C) Programmable Interrupt controller
(D) Programmable interval timer/counter

Ans The Intel 8251 is a programmable communication interface. It is USART.

Q.25 8088 microprocessor has

(A) 16 bit data bus (B) 4 byte pre-fetch queue

(C) 6 byte pre-fetch queue (D) 16 bit address bus

Ans The 8088 is a 16-bit microprocessor with an 8-bit data bus. The 16-bit address
bus. Hence answer is (D).

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Q.26 By what factor does the 8284A clock generator divide the crystal oscillator’s output
frequency? [Link]
(A) One (B) Two
(C) Three (D) Four

Ans When F/C’ is at logic 0; The oscillator output is steered through to the divide- by-
3 counter. Hence answer is (c).

Q.27 The memory data bus width in Pentium is

(A) 16 bit (B) 32 bit
(C) 64 bit (D) None of these

Ans The Data bus width is 64 bits. Hence answer is (C).

Q.28 When the 82C55 is reset, its I/O ports are all initializes as
(A) output port using mode 0 (B) Input port using mode 1
(C) output port using mode 1 (D) Input port using mode 0

Ans A RESET input to the 82C55 causes all ports to be set up as simple input ports
using mode 0 operations. Hence answer is (D).

Q.29 Which microprocessor pins are used to request and acknowledge a DMA transfer?
(A) reset and ready (B) ready and wait
(C) HOLD and HLDA (D) None o these

Ans, The HOLD pin is an input that is used request a DMA action and the HLDA
pin is an output that that acknowledges the DMA action. Hence answer is (C).

Q.30 Which of the following statement is false?

(A) RTOS performs tasks in predictable amount of time
(B) Windows 98 is RTOS
(C) Interrupts are used to develop RTOS
(D) Kernel is the one of component of any OS

Ans Operating systems, like Windows, defer many tasks and do not guarantee their
execution in predictable time. Hence answer is (B).

Q.31 The VESA local bus operates at

(A) 8 MHz (B) 33 MHz
(C) 16 MHz (D) None of these

Ans The VESA local bus operates at 33 MHz. Hence answer is (B).

Q.32 The first modern computer was called .

(A) FLOW-MATIC (B) UNIVAC-I
(C) ENIAC (D) INTEL

Ans, ENIAC (Electronic Numerical Integrator And Computer) was the first general-
purpose electronic computer. It was a Turing-complete, digital computer capable of
being reprogrammed to solve a full range of computing problems. ENIAC was

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designed to calculate artillery firing tables for the U.S. Army's Ballistic Research
Laboratory. Hence answer is (c). [Link]
Q.33 Software command CLEAR MASK REGISTER in DMA
(A) Disables all channels.
(B) Enables all channels.
(C) None.
(D) Clears first/last flip-flop within 8237.

Ans Enables all four DMA channels. Hence answer is (B).

Q.34 The first task of DOS operating system after loading into the memory is to use the file
called .
(A) [Link] (B) [Link]
(C) [Link] (D) [Link]

Ans, The first task of the DOS operating system, after loading into memory, is to
use a file called the [Link] file. This file specifies various drivers that load
into the memory, setting up or configuring the machine for operation under DOS.

Q.35 If the programmable counter timer 8254 is set in mode 1 and is to be used to count
six events, the output will remain at logic 0 for number of counts
(A) 5 (B) 6
(C) 0 (D) All of the above

Ans. OUT continues for the total length of the count. Hence answer is (B).

Q.36 The flash memory is programmed in the system by 12 V programming pulse.

(A) TRUE (B) FALSE

Ans The flash memory device requires a 12V programming voltage to erase and write
new data. Hence answer is (A).

Q.37 A plug and play (PnP) interface is one that contains a memory that holds
configuration information of the system.
(A) TRUE (B) FALSE

Ans Answer is (A)

Q.38 The accelerated graphics port (AGP) allows virtually any microprocessor to be
interfaced with PCI bus via the use of bridge interface.
(A) TRUE (B) FALSE

Ans, this port probably will never be used for any devices other than the video card.
Hence answer is (B).

Q.39 A Bus cycle is equal to how many clocking periods

(A) Two (B) Three
(C) Four (D) Six

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Ans Typically, the bus-cycle of the 8086 and 8088 processors consist of four clock
cycles or pulses. Thus, duration of a bus-cycle is = ‘4*T’. Hence Answer is (C). [Link]
Q.40 The time required to refresh a typical DRAM is
(A) 2 – 4 us (B) 2 – 4 ns
(C) 2 – 4 ms (D) 2 – 4 ps

Ans The capacitor Cs discharges through the internal resistance of the NMOS transistor
T1. Typically Cs = 0.2 pF and the internal resistance Rin = 1010 ohms, so:
Cs x Rin = 0.2 x 10-12 x 1010 x 103 ms = 2 ms
So the typical refresh time interval is 2 ms. Hence Answer is (C).

Q.41 The no. of address lines required to address a memory of size 32 K is

(A) 15 lines (B) 16 lines
(C) 18 lines (D) 14 lines
5 10 15
Ans 32K = 32 X 1024 bits = 2 X 2 =2 Hence answer is ( A).

Q.42 The no. of wait states required to interface 8279 to 8086 with 8MHz clock are
(A) Two (B) Three
(C) One (D) None

Ans Two wait states used so that device can function with an 8 MHz. Hence answers is
( A).

Q.43 NMI input is

(A) Edge sensitive (B) Level sensitive
(C) Both edge and level triggered (D) edge triggered and level sensitive

Ans Non-maskable interrupt (NMI) is an edge –triggered input that requests an

interrupt on the positive edge (0 to 1 transition).

Q.44 Data rate available for use on USB is

(A) 12 Mbits per second (B) 1.5 Mbits per second
(C) Both (A) and (B) (D) No restriction

Ans Data transfer speeds are 12 Mbps for full speed operation and 1.5 Mbps for slow
speed operation. Hence answer is (c).
Q.45 In 80186, the timer which connects to the system clock is
(A) timer 0 (B) timer 1
(C) timer 2 (D) Any one can be connected

Ans. Timer 2 is internal and clocked by the master clock. Hence answer is (c).

Q.46 Conversion of the +1000 decimal number into signed binary word results
(A) 0000 0011 1110 1000 (B) 1111 1100 0001 1000
(C) 1000 0011 1110 1000 (D) 0111 1100 0001 1000

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Ans
[Link]
1000 /2 =>500 €0
500/2=>250€0
250/2=>125€0
125/2=>62€1
62/2=>31€0
31/2=>15€1
15/2=>7€1
7/2=>3€1
3/2=>1€1
16 bit signed number is 1000,0011,1110,1000
Hence Answer is (C).

Q.47 What do the symbols [ ] indicate?

(A) Direct addressing (B) Register Addressing
(C) Indirect addressing (D) None of the above

Ans Answer is (C).

Q.48 SDRAM refers to

(A) static DRAM (B) synchronous DRAM
(C) sequential DRAM (D) semi DRAM

Ans, Answer is (B)

Q.49 Which pins are general purpose I/O pins during mode-2 operation of the 82C55?
(A) PA0 – PA7 (B) PB0-PB7
(C) PC3-PC7 (D) PC0-PC2

Ans In mode 2 Port-A can be programmed to operate as bidirectional port. The mode-2
operation is only for Port-A. Hence Answer is (A)

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Microprocessor

1) A microprocessor is the heart of the microcomputer.

a) Receiving input
b) Performing computations.
c) Storing data & instructions
d) All of the above.

Ans:d)All of the above

2) A device, which enables a microcomputer to perform the first of the above-

mentioned tasks is known as the input device.
a) Keyboard
b) Mouse
c) Toggle
d) All of the above.

Ans:d)All of the above

3) The task of displaying the result computed by the microprocessor is

performed by an output device, some of the commonly used output device.
a) Cathode Ray Tube(CRT)
b) Light-Emitting diodes(LED’S)
c) Laser printer
d) All of the above.

Ans:d)All of the above

4) n instruction essentially consists of an

a) Operation code
b) Address of the data
c) Instruction operates
d) None of the above.

Ans:a)Operating code

5) The 8085A has interrupt pins:-

a) TRAP, RST7.5
b) RST6.5, RST5.5
c) TNTR(pin 10)
d) All of the above.
 [Link]

Ans:d)All of the above

6) 8085A has 8 unidirectional signal lines:-

a) MSB
b) HOLD,HALT
c) RESET mode
d) None of the above.

Ans:a)MSB

7) Every microprocessor is provided with a set of registers :

a) Temporary storage
b) Instruction Execution
c) All of these
d) None of the above.

Ans:a)Temporary storage

8) Registers available for the temporary storage of operands or address affects

the following:-
a) Memory space occupied by the program.
b) Time of execution of the program.
c) Ease of programming.
d) All of the above.

Ans:d)All of the above

9) The registers available to the user can be further classified into:-

a) General purpose register
b) Special-purpose register
c) None of these
d) All of the above.

Ans:d)All of the above

10) In the 8085A microprocessor, the data size is 8-bit and the address size is 16-
bit.
a) B-C pair
b) D-E pair
c) H-L pair
d) All of the above.
 [Link]

Ans:d)All of the above

11) Set of registers provided for some special applications.

a) Accumulator
b) Memory space
c) All of the above
d) None of the above.

Ans:Accumulator

12) A microprocessor to execute a program, the CPU has to do the following

operations:
a) Fetch the opcode
b) Read a memory location for the data.
c) Perform the required operation
d) All of the above.

Ans:d)All of the above

13) An instruction cycle can be defined as the sum of an instruction fetch time and
the instruction execution time.
a) Instruction cycle=Instruction fetch + Instruction execute.
b) Memory location and deposited in the CPU’s
c) Both of these
d) None of the above.

Ans:a)Instruction cycle=Instruction fetch + Instruction execute

14) 8085 has 5 addressing mode and are:-

a) Immediate, inherent
b) Direct
c) Register and register indirect
d) All of the above.

Ans: d)All of the above

30) The part of 8255 can be programmed for any other mode by writing a single
control word into the
a) Port
 [Link]

b) Control Logic
c) Set/Reset
d) Register.

Ans:d)Regiter

15) One of the following addressing modes is not possible in 8085.

a) Indexed addressing
b) Indirect addressing
c) Direct addressing
d) Indirect register address.

Ans:a)Indexed addressing

16) 8085 has

a) One 16-bit register
b) Two 16-bit register
c) Three 16-bit register
d) Four 16-bit register.

Ans:b)Two 16-bit register

17) The speed of a microprocessor is usually measured by the

a) Microprocessor’s throughput.
b) Speed with which it performs I/P and O/P operations.
c) Time required to execute basic instruction.
d) Time required to process a small operation.

Ans:c)Time required to execute basic instruction

18) Interrupts can be generally classified :

a) Hardware interrupts
b) Software interrupts
c) Both of above
d) All of the above.

Ans:d)All of the above

19) 8085 microprocessor has 5 hardware interrupts :

a) TRAP, RST6.5
b) RST7.5, RST5.5
c) INTR
d) None of the above.
 [Link]

Ans:b)RST7.5, RST5.5

20) The data which a microprocessor needs to process, comes from devices such
as a keyboard.
a) Switch
b) Analog-to-digital
c) Digital-to-analog
d) All of the above.

Ans: d)All of the above

21) The 8085 can respond to four externally initiated operation.

a) Reset, Interrupt b) Ready hold c) Memory-mapped I/O d) Memory chip
a) c, d, both
b) a, b, both
c) None of the above.
d) All of the above

Ans: a,b, both

22) To interconnect peripherals with the 8085 MPU, additional logic circuit, called
interfacing devices. These circuits include a device such as
a) buffer
b) Decoder
c) Encoder, latches
d) All of the above.

Ans: d)All of the above

23) The 8085 flag register has five flags.

1) Carry flag, Sign flag 2) Zero flag, Parity flag 3) Auxilliary Carry
a) 1, 2 both
b) 1, 3 both
c) 2, 3 both
d) All of the above.

Ans: 1, 2 both

24) Counters and time delays can be designed using.

a) Software
b) CPI
 [Link]

c) Instruction
d) All of the above.

Ans: a)Software

25) The 8085 code can be assembled by using a program called a :

a) Cross-assembler
b) Cross-compiler
c) Cross-interpret
d) All of the above.

Ans:a)Cross-assembler

26) The 8085 microprocessor has two pins available for I/O communication.
(1) HOLD, HOLDA (2) HOLDAB, HOLDB
a) 1, 2 both
b) 1 only
c) 2 only.
d) All of these

Ans: b)

27) The ___ is a program that allows then used to test and debug the object file.
a) Assembler
b) Loader
c) Debugger
d) None of the above.

Ans:c)

28) It is a program that takes the object file generated by the assembler program.
a) Loading
b) Loader
c) Debugger
d) All of the above.

Ans:b)

30) Intel’s 8086 and 80286, Motorola’s M 68000 and Zilog’s Z8000 are some of the
most powerful-16-bit microprocessor are not available today. (T/F)
Ans. False
 [Link]

31) A microprocessor is a multipurpose, programmable, clock driven, register-based

electronic device. (T/F)
Ans. True

32) Read instructions from a storage device called memory. (T/F)

Ans. False

33) A typical programmable machine can be represented with 4 component:

microprocessor, memory, Input/Output device, application. (T/F)
Ans. False

34) The physical components of this system are called the hardware. (T/F)
Ans. True

35) A set of instructions written for the microprocessor to perform a task is called an
application. (T/F)
Ans. False

37) The microprocessor applications are classified primarily into 3 categories: re-
programmable system and embedded system. (T/F)
Ans. True

38) The first microprocessor was introduced by Intel Corporation in 1971. (T/F)
Ans. True

39) 4-bit microprocessor (Intel) introduced were ROCKWELL International‘s (PPS4).

(T/F)
Ans. True

40) In 8087 ___ executes all the instructions including arithmetic, logical,
transcendental, and data transfer instructions.
A) Arithmetic and logical unit
B) Control Unit
C) Numeric Execution Unit
D) None of the above

Ans:c)

41) A group of ___ bits is called byte.

A) 2
B) 4
C) 6
D) 8
 [Link]

Ans:A)

42) The single IC which consists of ALU, control section, and register section is
called___.
A) Microprocessor
B) Microcontroller
C) Register
D) Computer

Ans:A)

43) A system bus which carries, only the control and timing signals then it is called as
____
A) Address bus
B) Data bus
C) Control bus
D) None of the above

Ans:C)

44) Physical devices and circuitry of the computer are also known as ___ .
A) Hardware
B) Software
C) System Software
D) Application Software

Ans: A)

45) Intel developed first processor 4004 in 1974 which was a ___ bit processor.
A) 1
B) 2
C) 3
D) 4

Ans:D)

46) Intel introduced the ___ 16 bit microprocessor in 1978.

A) 8085
B) 8086
C) 8080
D) 80386

Ans:B)
 [Link]

47) The ____ family was introduced as a part of Intel Centrino Technology.
A) Pentium M
B) Pentium I
C) Pentium II
D) Dual core

Ans:A)

48) AMD stand for___

A) Advanced Macro Devices
B) Advanced Micro Devices
C) Analog Macro Devices
D) Analog Micro Devices

Ans:B)

49) 16 bit microprocessor has ___ bit data bus and ___ bit address bus.
A) 16, 20
B) 8,16
C) 4, 16
D) 8,20

Ans:A)

50) 8086 operates in ___ modes.

A) Four
B) Three
C) Two
D) One

Ans:C)

51) BIU Stands for___.

A) Binary Interactive Unit
B) Bus Interactive Unit
C) Bus Interface Unit
D) Binary Interface Unit

Ans:C)

52) Assembler is a type of translator that translates ___ language into machine
level language.
A) High Level
B) Assembly level
 [Link]

C) Both A and B
D) None of the above

Ans: B)

53) The addressing modes of 8086 can be categorized into ___ categories.
A) One
B) Two
C) Three
D) Four

Ans: D)

54) In ___ addressing mode the operands are specified in the instruction itself.
A) Immediate
B) Register
C) Direct
D) Indirect

Ans: A)

55) ___ instructions are used in such cases when some instructions are needed to be
executed number of times to perform certain tasks.
A) Jump
B) Loop
C) Shift
D) Rotate

Ans: B)

56) ___ instruction stops the execution of microprocessor and force microprocessor
to enter into wait state
A) WAIT
B) LOCK
C) ESC(Escape)
D) HALT

Ans: D)

57) A series of data byte available in memory at consecutive locations is called as___.
A) Bit String
B) Byte String
C) Word
D) None of these
 [Link]

Ans:B)

58) ___loads a byte from a string in memory into AL.

A) LOD SB
B) LOD SW
C) STO SB
D) STO SW

Ans:A)

59) CMPS stands for___.

A) Compare string byte
B) Compare string bit
C) Concatenate string byte
D) Concatenate string bit

Ans:B

60) ___ is a Prgrammable Interrupt Controller.

A) 8259A
B) 8086
C) 8085
D) 8255

Ans:A

61) ___ is used by 8259 A to Decipher various Commnad Words the CPU writes.
A) INT
B) INTA
C) A0
D) RD

Ans:C)

62) The length of a bus cycle in 8086 system is of ___ clock cycles.
A) One
B) Two
C) Three
D) Four

Ans:D

63) PIC stands for___

A) Process Interface Controller
 [Link]

B) Process Interrupt Controller

C) Programmable Interface Controller
D) Pragrammable Interrupt Controller

Ans:D

64) Data bus buffer is a ___ state bidirectional ___ bit buffer that is used to interface
8259A to the system Data Bus.
A) 3,8
B) 2,8
C) 3,16
D) 2,16

Ans:A

65) RAM is ___ memory.

A) read only
B) Write only
C) Read/write
D) None of the above

Ans:C

66) In ___ cell the capacitor is used to store the charge as a representation of data.
A) Static RAM
B) ROM
C) Dynamic RAM
D) None of the above

Ans:C

67) In context of 8255 BSR stands for___.

A) Bit Set Register
B) Bit-Set Reset
C) Binary Set Register
D) Binary Set-Reset

Ans:B

68) In 8255-PPI ___ mode is used as two simple 8 bit I/O ports and port C as two 4-
bit I/O ports.
A) Mode 0
B) Mode 1
 [Link]

C) Mode 2
D) Mode 3

Ans:A

69) ___ is an Intel’s general purpose keyboard display controller.

A) 8255
B) 8279
C) 8085
D) 8088

Ans:B

70) ___ is a programmable interval timer/counter designed for use with Intel
Microprocessor system.
A) 8255
B) 8279
C) 8251
D) 8254

Ans:D

71) 8254 has powerful READ BACK command which allows the user to check the
count value, programmed mode, current mode and current status of counter
A) True
B) False

A)True

72) USART stands for ___

A) Universal Synchronous Asynchronous Receiver Transmitter
B) Universal Standard Analog Receiver Transmitter
C) Universal Synchronous Analog Radiator Transmitter
D) Universal Standard Asynchronous Radiator Transmitter

Ans:A
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Date-16/06/2021
Subject Name-KCS-403-Microprocessor_CSE-Semester 4
UNIT-1

1. In 8085 microprocessor, the RST6 instruction transfer programme execution

to following location

a. 0030H

b. 0024H

c. 0048H

d. 0060H

Answer: (a).0030H

2. HLT opcode means

a. load data to accumulator

b. store result in memory

c. load accumulator with contents of register

d. end of program

Answer: (d).end of program

3. What is SIM?

a. Select interrupt mask

b. Sorting interrupt mask

c. Set interrupt mask

d. None of these
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Answer: (c).Set interrupt mask

4. The ROM programmed during manufacturing process itself is called

a. MROM

b. PROM

c. EPROM

d. EEPROM

Answer: (a).MROM

5. A field programmable ROM is called

a. MROM

b. PROM

c. FROM

d. FPROM

Answer: (b).PROM

6. The operations executed by two or more control units are referred as

a. Micro-operations

b. Macro-operations

c. Multi-operations

d. Bi control-operations

Answer: (b).Macro-operations
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7. Program counter in a digital computer

a. Counts the numbers of programs run in the machine.

b. Counts the number of times a subroutine is called.

c. Counts the number of times the loops are executed.

d. Points the memory address of the next instruction to be fetched.

Answer: (d).Points the memory address of the next instruction to be fetched.

8. At the beginning of a fetch cycle, the contents of the program

counter are

a. incremented by one.

b. transferred to address bus.

c. transferred to memory address register.

d. transferred to memory data register.

Answer: (c).transferred to memory address register.

9. Which components are NOT found on chip in a microprocessor but may be

found on chip in a micro-controller?

a. SRAM & USART

b. EPROM & PORTS

c. EPROM, USART & PORTS

d. SRAM, EPROM & PORTS

Answer: (c).EPROM, USART & PORTS

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10. For the purpose of data processing an efficient assembly language

programmer makes use of the general purpose registers rather than
memory. The reason is

a. the set of instructions for data processing with memory is limited

b. data processing becomes easier when register are used

c. more memory related instructions are required

d. data processing with registers takes fewer cycles than that with memory

Answer: (d).data processing with registers takes fewer cycles than that with memory

11. The first machine cycle of an instruction is always

a. A memory read cycle

b. A fetch cycle

c. An I/O read cycle

d. A memory write cycle

Answer: (b).A fetch cycle

12. The output data lines of microprocessor and memories are usually tristated
because

a. More than one device can transmit information over the data bus by enabling
only one device at a time

b. More than one device can transmit over the data bus at the same time

c. The data line can be multiplexed for both input and output

d. It increases the speed of data transfer over the data bus

Answer: (a).More than one device can transmit information over the data bus by
enabling only one device at a time
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13. The correct sequence of steps in the instruction cycle of a basic computer is

a. Fetch, Execute, Decode and Read effective address.

b. Read effective address,Decode,Fetch and Execute.

c. Fetch, Decode, Read effective address and ,Execute.

d. Fetch, Read effective address, Decode and Execute.

Answer: (c).Fetch, Decode, Read effective address and ,Execute.

14. The register which holds the information about the nature of results of
arithmetic and logic operations is called as

a. Accumulator

b. Condition code register

c. Flag register

d. Process status register

Answer: (c).Flag register

15. Consider the following statements:

Arithmetic Logic Unit (ALU)
[Link] arithmetic operations
[Link] comparisons.
[Link] with I/O devices
[Link] watch on the system
Which of these statements are correct?

a. 1, 2, 3 and 4

b. 1, 2 and 3

c. 1 and 2 only
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d. 3 and 4 only

Answer: (c).1 and 2 only

16. Ready pin of microprocessor is used

a. to indicate that microprocessor is ready to receive inputs

b. to indicate that microprocessor is ready to receive outputs

c. to introduce wait state

d. to provide direct memory access

Answer: (c).to introduce wait state

17. Both the ALU and control section of CPU employ which special purpose
storage location?

a. Buffers

b. Decoders

c. Accumulators

d. Registers

Answer: (c).Accumulators

18. A high on RESET OUT signifies that

a. all the registers of the CPU are being reset

b. all the registers and counters are being reset

c. all the registers and counters are being reset and this signal can be used to
reset external support chip
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d. processing can begin when this signal goes high

Answer: (c).all the registers and counters are being reset and this signal can be
used to reset external support chip

19. In a vector interrupt

a. the branch address is assigned to a fixed location in memory

b. the interrupting source supplies the branch information to the processor

through an interrupt vector

c. the branch address is obtained from a register in the processor

d. none of the above

Answer: (a).the branch address is assigned to a fixed location in memory

20. The content of the A15-A8 (higher order address lines) while executing “IN
8-bit port address” instruction are

a. same as the content of A7-A0

b. irrelevant

c. all bits reset (i.e. 00H)

d. all bits set (i.e. FFH)

Answer: (a).same as the content of A7-A0

21. Which one of the following interrupt is only level triggering?

a. TRAP

b. RST 7.5

c. RST 6.5 and RST 5.5

d. RST 6.5
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Answer: (c).RST 6.5 and RST 5.5

22. Which one of the following instruction may be used to clear the
accumulator content irrespective of its initial value?

a. CLR A

b. ORA A

c. SUB A

d. MOV A, 00H

Answer: (c).SUB A

23. ___________ signal prevent the microprocessor from reading the same data
more than one.

a. pipelining

b. handshaking

c. controlling

d. signaling

Answer: (b).handshaking

24. Data transfer between the microprocessor for peripheral takes place
through __________.

a. I/O port

b. input port

c. output port
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d. multi port

Answer: (a).I/O port

25. 8255A operates with ________ power supply.

a. +5V

b. -5V

c. -10V

d. +10V

Answer: (a).+5V

26. The _______ allow data transfer between memory and peripherals.

a. DMA technique

b. Microprocessor

c. Register

d. Decoder

Answer: (a).DMA technique

27. Expansion of SPGA is _________.

a. Staggered Pin Grid-Array package

b. Staggered Point Grid-Array package

c. Staggered Plus Grid-Array package

d. Staggered per grid-Array package

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Answer: (a).Staggered Pin Grid-Array package

28. Pentium-pro processor design implements________ micro architecture.

a. P2

b. P4

c. P6

d. P8

Answer: (c).P6

29. The number of hardware chips needed for multiple digit display can be
minimized by using the technique called ______.

a. interfacing

b. multiplexing

c. demultiplexing

d. multiprocessing

Answer: (b).multiplexing

30. An RS-232 interface is ____________.

a. a parallel interface

b. a serial interface

c. printer interface

d. a modem interface
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Answer: (b).a serial interface

31. Expansion for DTE is ______.

a. data terminal equipment

b. data trap equipment

c. data text equipment

d. data terminal extension

Answer: (a).data terminal equipment

32. Compared with RS-232, USB is faster and uses___________.

a. medium voltage

b. higher voltage

c. lower voltage

d. None of the above

Answer: (c).lower voltage

33. Expansion for HMOS technology is _______.

a. high level mode oxygen semiconductor

b. high level metal oxygen semiconductor

c. high performance medium oxide semiconductor

d. high performance metal oxide semiconductor

Answer: (d).high performance metal oxide semiconductor

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34. RIM is used to check whether, the ___________.

a. write operation is done or not

b. interrupt is Masked or not

c. interrupt is Masked

d. interrupt is not Masked

Answer: (b).interrupt is Masked or not

35. What does microprocessor speed depends on?

a. clock

b. data bus width

c. address bus width

d. signal bus

Answer: (c).address bus width

36. The advantage of memory mapped I/O over I/O mapped I/O is _________

a. faster operation

b. many instructions supporting memory mapped I/O

c. require a bigger address decoder

d. all the above

Answer: (d).all the above

37. In 8279 Status Word, data is read when ________ pins are low, and write to
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the display RAM with ____________ are low.

a. A0, CS, RD & A0, WR, CS

b. CS, WR, A0 & A0, CS, RD

c. A0, RD & WR, CS

d. CS, RD & A0, CS

Answer: (a).A0, CS, RD & A0, WR, CS

38. In 8279, the keyboard entries are de bounced and stored in an _________,
that is further accessed by the CPU to read the key codes.

a. 8-bit FIFO

b. 8-byte FIFO

c. 16 byte FIFO

d. 16 bit FIFO

Answer: (b).8-byte FIFO

39. For the most Static RAM the write pulse width should be at least

a. 10 ns

b. 60 ns

c. 300 ns

d. 350 ns

Answer: (b).60 ns
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40. Pentium-I, Pentium-II, Pentium-III and Pentium-IV are recently

introduced microprocessor by__________.

a. Motorala

b. Intel

c. Stephen Mors

d. HCL

Answer: (b).Intel

41. The address bus flow in __________.

a. bidirection

b. unidirection

c. mulidirection

d. circular

Answer: (b).unidirection

42. The 8085 microprocessor is based in a ________ pin DIP.

a. 40

b. 45

c. 20

d. 35

Answer: (a).40
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43. The 8085 Microprocessor uses__________ power supply.

a. +5V

b. -5V

c. +12V

d. -12V

Answer: (a).+5V

44. Which is used to store critical pieces of data during subroutines and
interrupts ?

a. Stack

b. Queue

c. Accumulator

d. Data register

Answer: (a).Stack

45. The data in the stack is called

a. Pushing data

b. Pushed

c. Pulling

d. None of these

Answer: (a).Pushing data

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46. The external system bus architecture is created using from ______
architecture.

a. Pascal

b. Dennis Ritchie

c. Charles Babbage

d. Von Neumann

Answer: (d).Von Neumann

47. Secondary memory can store____.

a. Program store code

b. Compiler

c. Operating system

d. All of these

Answer: (d).All of these

48. Secondary memory is also called____.

a. Auxiliary

b. Backup store

c. Both A and B

d. None of these

Answer: (c).Both A and B

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49. The lower red curvy arrow show that CPU places the address extracted
from the memory location on the_____.

a. Address bus

b. System bus

c. Control bus

d. Data bus

Answer: (a).Address bus

50. The CPU sends out a ____ signal to indicate that valid data is available on
the data bus.

a. Read

b. Write

c. Both a and b

d. None of these

Answer: (b).Write

UNIT-2
1. In 8085 microprocessor, how many interrupts are maskable.
a. Two
b. Three
c. Four
d. Five
Answer. c
2. Which stack is used in 8085 microprocessors?
a. FIFO
b. FILO
c. LIFO
d. LILO
Answer. c
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3. In the instruction of the 8085 microprocessor, how many bytes are present?
a. One or two
b. One, two or three
c. One only
d. Two or three
Answer. b
4. Which one of the following addressing technique is not used in 8085
microprocessor?
a. Register
b. Immediate
c. Register indirect
d. Relative
Answer. d
5. Which one of the following register of 8085 microprocessor is not a part of the
programming model?
a. Instruction register
b. Memory address register
c. Status register
d. Temporary data register
Answer. c
6. The program counter in 8085 microprocessor is a 16-bit register, because
a. It counts 16 bits at a time
b. There are 16 address times
c. It facilitates the users storing 16-bit data temporarily
d. It has to fetch two 8-bit data at a time.
Answer. b
7. A direct memory access (DMA) transfer replies
a. Direct transfer of data between memory and accumulator
b. Direct transfer of data between memory and I/O devices without the use of
microprocessor
c. Transfer of data exclusively within microprocessor registers
d. A fast transfer of data between microprocessor and I/O devices
Answer. b
8. Handshaking mode of data transfer is
a. Synchronous data transfer
b. asynchronous data transfer
c. interrupt driven data transfer
d. level Mode of DMA data transfer
Answer. a
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9. In a Microprocessor, the address of the new next instruction to be executed is

stored in
a. Stack pointer
b. address latch
c. Program counter
d. General purpose register
Answer. c
10. In how many different modes a universal shift register operates?
a. 2
b. 3
c. 4
d. 5
Answer. c
11. The insruction RET executes with the following series of machine cycle
a. Fetch, read, write
b. Fetch, write, write
c. Fetch, read, read
d. Fetch, read
Answer. c
12. Which one of the following statements is correct regarding the instruction
CMP A ?
a. compare accumulator with register A
b. compare accumulator with memory
c. compare accumulator with register H
d. This instruction does not exist
Answer. a
13. The instruction JNC 16-bit refers to jump to 16-bit address if ?
a. sign flag is set
b. carry flag is reset
c. zero flag is set
d. parity flag is reset
Answer. b
14. Among the given instructions, the one which affects the maximum number of
flags is ?
a. RAL
b. POP PSW
c. XRA A
d. DCR A
Answer. c
15. XCHG instruction of 8085 exchanges the content of ?
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a. top of stack with contents of register pair

b. BC and DE register pairs
c. HL and DE register pairs
d. None of the above
Answer. c
16. Direction flag is used with
a. string instructions
b. stack instructions
c. arithmetic instructions
d. branch instructions
Answer. a
17. The number of output pins of a 8085 microprocessor are
a. 40
b. 27
c. 21
d. 19
Answer. b
18. Following is a 16-bit register for 8085 microprocessor
a. Stack pointer
b. Accumulator
c. Register B
d. Register C
Answer. a
19. The register which holds the information about the nature of results of
arithmetic of logic operations is called as
a. Accumulator
b. Condition code register
c. Flag register
d. Process status registers
Answer. c
20. When referring to instruction words, a mnemonic is
a. a short abbreviation for the operand address.
b. a short abbreviation for the operation to be performed.
c. a short abbreviation for the data word stored at the operand address.
d. Shorthand for machine language.
Answer. b
21. While using a frequency counter for measuring frequency, two modes of
measurement are possible.
1. Period mode
2. Frequency mode
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There is a ‘cross-over frequency’ below which the period mode is preferred.

Assuming the crystal oscillator frequency to be 4 MHz the crossover frequency is
given by
a. 8 MHz
b. 2 MHz
c. 2 kHz
d. 1 kHz
Answer. b
22. In a 8085 microprocessor system with memory-mapped I/O, which of the
following is true?
a. Devices have 8-bit‘address line
b. Devices are accessed using IN and OUT instructions
c. There can be maximum of 256 input devices and 256 output devices
d. Arithmetic and logic operations can be directly performed with the I/O data
Answer. d
23. Consider the following statements:
Arithmetic Logic Unit (ALU)
1 . Performs arithmetic operations.
2. Performs comparisons.
3. Communicates with I/O devices.
4. Keeps watch on the system.
Which of these statements are correct?
a. 1, 2, 3 and 4
b. 1,2 and 3 only
c. 1 and 2 only
d. 3 and 4 only
Answer. c
24. Ready pin 0f microprocessor is used
a. to indicate that the microprocessor is ready to receive inputs
b. to indicate that the microprocessor is ready to receive outputs
c. to introduce wait state
d. to provide direct memory access
Answer. c
25. A bus connected between the CPU and the main memory that permits transfer
of information between main memory and the CPU is known as
a. DMA bus
b. Memory bus
c. Address bus
d. Control bus
Answer. b
26. The operations executed by two or more control units are referred as
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a. Micro-operations
b. Macro-operations
c. Multi-operations
d. Bi control-operations
Answer. c
27. Consider the following registers:
1. Accumulator and flag register
2. B and C registers
3. D and E registers
4. H and L registers
Which of these 8-bit registers of 8085 μP can be paired together to make a 16-bit
register?
a. (a) 1, 3 and 4
b. 2, 3 and 4
c. 1, 2 and 3
d. 1, 2 and 4
Answer. b
28. The first microprocessor to include virtual memory in the Intel
microprocessor family is
a. 80286
b. 80386
c. 80486
d. Pentium
Answer. a
29. Program counter in a digital computer
a. counts the numbers of programs run in the machine ,
b. counts the number of times a subroutine is called
c. counts the number of times the loops are executed
d. points the memory address of the current or the next instruction to be
executed
Answer
Answer. d
30. Assuming LSB is at position 0 and MSB at position 7, which bit positions are
not used (undefined) in Flag Register of an 8085 microprocessor?
a. 1, 3, 5
b. 2, 3, 5
c. 1, 2, 5
d. 1, 3, 4
Answer. a
31. At the beginning of a fetch cycle, the contents of the program counter are
a. incremented by one
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b. transferred to address bus

c. transferred to memory address register
d. transferred to memory data register
Answer. c
32. Each instruction in an assembly language program has the following fields
1. Label field
2. Mnemonic field
3. Operand field
4. Comment field
What is the correct sequence of these fields?
a. 1, 2, 3 and 4
b. 2, 1, 4 and 3
c. 1,3, 2 and 4
d. 2, 4, 1 and 3
Answer. a
33. The relation among IC (lnstruction Cycle), FC (Fetch Cycle) and EC (Execute
Cycle) is
a. IC = FC − EC
b. IC = FC+ EC
c. IC= FC + 2EC
d. EC = IC+FC
Answer. b
34. When a peripheral is connected to the microprocessor in input/output mode,
the data transfer takes place between
a. any register and I/O device
b. memory and I/O device
c. accumulator and I/O device
d. HL registerand I/O device.
Answer. c
35. While execution of I/O instruction takes place, the 8-bit address of the port is
placed on
a. lower address bus
b. higher address bus
c. data bus
d. lower as well as higher-order address bus
Answer. d
36. The length of a bus cycle in 8086/8088 is four clock cycles, T1, T2, T3, T4 and
an indeterminate number of wait state clock cycles denoted by TW. The wait
states are always inserted between
a. T1 and T2
b. T2 and T3
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c. T3 and T4
d. T4 and T1
Answer. c
37. Which one of the following circuits transmits two messages simultaneously in
one direction?
a. Duplex
b. Diplex
c. Simplex
d. Quadruplex
Answer. b
38. A microprocessor is ALU
a. and control unit on a single chip
b. and memory on a single chip
c. register unit and I/O device on a single chip
d. register unit and control unit on a single chip
Answer. d
39. In Intel 8085 microprocessor, ALE signal is made high to
a. Enable the data bus to be used as low order address bus
b. To latch data D0— D7 from the data bus
c. To disable data bus
d. To achieve all the functions listed above
Answer. a
40. Output of the assembler in machine codes is referred to as
a. Object program
b. Source program
c. Macro instruction
d. Symbolic addressing
Answer. a
41. Which one of the following statements for Intel 8085 is correct?
a. Program counter (PC) specifies the address of the instruction last executed
b. PC specifies the address of the instruction being executed
c. PC specifies the address of the instruction be executed
d. PC specifies the number of instruction executed so far
Answer. c
42. The instruction RET executes with the following series of machine cycle
a. Fetch, read, write
b. Fetch, write, write
c. Fetch, read, read
d. Fetch, read
Answer. c
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43. Which one of the following statements is correct regarding the instruction
CMP A?
a. Compare accumulator with register A
b. Compare accumulator with memory
c. Compare accumulator with register H
d. This instruction does not exist
Answer. a
44. The instruction JNC 16-bit refers to jump to 16-bit address if
a. Sign flag is set
b. Carry flag is reset
c. Zero flag is set
d. Parity flag is reset
Answer. b
45. Consider the following interrupts for 8085 microprocessor:
1. INTR
2. RST 5.5
3. RST 6.5
4. RST 7.5
5. TRAP
If the interrupt is to be vectored to any memory location then which of the above
interrupt is/are correct?
a. 1 and 2 only
b. 1, 2, 3 and 4
c. 5 only
d. 1 only
Answer. d
46. Consider the following statements:
1. Auxiliary carry flag is used only by the DAA and DAS instruction.
2. Zero flag is set to 1 if the two operands compared are equal.
3. All conditional jumps are long type jumps.
Which of the above statements are correct?
a. 1, 2 and 3 only
b. 1 and 2 only
c. 1 and 3 only
d. 2 and 3 only
Answer. b
47. Among the given instructions, the one which affects maximum number of
flags is
a. RAL
b. POP PSW
c. XRA A
d. DCR A
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Answer. c
48. XCHG instruction of 8085 exchanges the content of
a. top of stack with contents of register pair
b. BC and DE register pairs
c. HL and DE register pairs
d. None of the above
Answer. c
49. Direction flag is used with
a. String instructions
b. Stack instructions
c. Arithmetic instructions
d. Branch instructions
Answer. a
50. What will be the contents of DE and HL register pairs respectively after the
execution of the following instructions?
LXIH, 2500 H
LXID, 0200 H
DAD D
XCHG
a. 0200 H, 2500 H
b. 0200 H, 2700 H
c. 2500 H, 0200 H
d. 2700 H, 0200 H
Answer. d

UNIT-3
51. In 8085 microprocessor, the address for ‘TRAP’ interrupt is
a. 0024 H
b. 002C H
c. 0034 H
d. 003C H
Answer. a
52. A ‘DAD H” instruction is the same as shifting each bit by one position to the
a. left
b. right
c. left with a zero inserted in LSB position
d. right with a zero inserted in LSB position
Answer. c
53. When a program is being executed in an 8085 microprocessor, its program
counter contains
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a.
the memory address as the instruction that is to be executed next.
b.
the memory address of the instruction that is being currently matched.
c.
the total number of instructions in the program being executed.
d.
the number of instructions in the current program that have already been
executed.
Answer. a
54. Which of the following data transfer is not possible in microprocessor?
a. Memory to accumulator
b. Accumulator to memory
c. Memory to memory
d. I/O device to accumulator
Answer. c
55. LOADER is a program that
a. loads the memories and generates a hex file
b. loads the hex file and converts to the executable file
c. loads the COM file and generates the binary code
d. loads English like command and generates the binary code
Answer. b
56. Which of the following instructions is closest match to the instruction POP
PC?
a. RET
b. PCHL
c. POP PSW
d. DAD SP
Answer. a
57. How many machine cycles are required by STA instruction?
a. 2
b. 3
c. 4
d. 5
Answer. c
58. Which of the following 8085 instruction will require maximum T-states for
execution?
a. XRI byte
b. STA address
c. CALL address
d. JMP address
Answer. c
59. In 8085 microprocessor, which mode of addressing does the instruction CMP
M use?
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a. Direct addressing
b. Register addressing
c. Indirect addressing
d. Immediate addressing
Answer. c
60. With reference to 8085 microprocessor, which of the following statements
are correct?
1. INR is 1 byte instruction
2. OUT is 2 byte instruction
3. STA is 3 byte instruction
a. 1 and 2 only
b. 2 and 3 only
c. 1 and 3 only
d. 1, 2 and 3
Answer. d
61. Assume that the accumulator and the register C of 8085 microprocessor
contain respectively F0 H
and OF H initially. What will be the content of accumulator after execution of
instruction ADD C?
a. 00 H
b. FF H
c. EF H
d. FE H
Answer. b
62. It is desired to multiply the numbers 0A H by OB H and store the result in the
accumulator. The numbers are available in registers B and C respectively. A part
of the 8085 program for this purpose is given below:
MVI A, OO H
Loop; ………..
………..
………..
HLT END
The sequence of instruction to complete the program would be
a. JNZ LOOP; ADD B, DCR C

b. ADD B; JNZ LOOP; DCR C

c. DCR C; JNZ LOOP; ADD B

d. ADD B; DCR C; JNZ LOOP

Answer. d
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63. Find the content of the accumulator after the execution of the following
program:
MVI A, F0 H
ORI FF H
XRI F0 H
a. 00 H
b. F0 H
c. 0F H
d. FF H
Answer. c
64. The following program starts at location 0100 H
LXI SP, 00FF
LXI H, 0701 H
MVI A, 20 H
SUB M
The content of accumulator when the program counter reaches 0107 H is
a. 20 H
b. 02 H
c. 00 H
d. FF H
Answer. c
65. The difference between 8085 instructions RST n and PCHL is
a. RST n is equivalent to a sub-routine call while PCHL is equivalent to
unconditional branch.
b. RST n uses direct addressing while PCHL uses register indirect addressing.
c. RST n is a software interrupt while PCHL simulates a hardware interrupt
d. RST n resets the processor while PCHL restarts the processor.
Answer. a
66. The content of accumulator are 70 H. Initially all flags are zero. What will be
values of CY and S after executing instruction RLC?
a. CY = 0 and S = 0
b. CY = 1 and S = 1
c. CY = 1 and S = 0
d. CY = 0 and S = 1
Answer. d
67. A software delay subroutine is written as given below:
DELAY: MVI H, 255D H
MVI L, 255D H
LOOP: DCR L
JNZ LOOP
DCR H
JNZ LOOP
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How many times DCR instruction will be executed?

a. 255
b. 510
c. 65025
d. 65279
Answer. d
68. What is content of accumulator of 8085 microprocessor after the execution of
XRI F0 H instruction?
a. Only the upper nibble of accumulator is complemented
b. Only the lower nibble is complemented
c. Only the upper nibble is reset to zero
d. Only the lower nibble is reset to zero
Answer. a
69. The 8085 programming manual says that it takes seven T states to fetch and
execute the MOV instruction. If the system clock has a frequency of 2.5 MHz, how
long is an instruction Cycle?

a. 2.8 s
b. 2.5ns
c. 2.8 ns
d. 2.8 μs
Answer. d
70. The instruction PCHL, in 8085 is used for

a. Load PC with contents of HL.

b. Load HL with contents of memory location pointed by PC.
c. Load HL with contents of PC
d. Load PC with the contents of memory location pointed by HL pair.
Answer. a
71. The following instruction copies a byte of data from the accumulator into the
memory address given in the instruction

a. STA address
b. LDAX B
c. LHLD address
d. LDA address
Answer. a
72. The instruction that exchanges top of stack with HL pair is

a. XTHL
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b. SPHL
c. PUSH H
d. POP H
Answer. a
73. In 8085 microprocessor, during PUSH PSW Operation, Stack pointer is

a. Decremented by one
b. Decremented by two
c. Incremented by one
d. Incremented by two
Answer. b
74. While a program is being executed in an Intel 8085 microprocessor, the
program counter of the microprocessor contains:
a. The memory address of the instruction that is being currently executed.
b. The memory address of the instruction that is to be executed next.
c. The number of instructions that have already been executed.
d. The total number of instructions in the current program still to be
executed.
Answer. b
75. The description of a program counter (PC) in 8085 microprocessor is
a. An up/down counter
b. An 8-bit register
c. Initialized automatically by microprocessor
d. Used to point to stack memory area
Answer. c
76. If the status of the control lines SI and SO is LOW, then 8085 microprocessor
is performing
a. Reset operation
b. HOLD operation
c. Halt operation
d. Interrupt acknowledge
Answer. c
77. LXI SP, 7FFF H
MVI A, 25 H
XRI 02 H
PUSH PSW
POP H
MOV A,L
ORI 10 H
HLT
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What are the contents of A, H, L, SP and PSW registers after executing the above
set of instructions? Assume undefined flags always remain clear.
a. 10H, 25H, 00H, 7FFFH, 00H respectively
b. 14H, 27H, 04H, 7FFFH, 04H respectively
c. 14H, 25H, 00H. 7FFFH, 04H respectively
d. 10H, 27H, 04H, 7FFFH, 00H respectively
Answer. b
78. The content of the programme counter of an 8085 microprocessor is
a. the total number of instructions in the program already executed.

b. the total number of times a subroutine is called.

c. the memory address of the instruction that is being currently executed.
d. the memory address of the instruction that is to be executed next.
Answer. d
79. The opcode for the instruction “Add Immediately to Accumulator with carry”
in 8085 microprocessor is

a. ADI
b. ACI
c. ADC
d. ADD
Answer. b
80. MVI A, AA H
ORI FFH
RRC
RRC
CMC
INR A
What are the contents of A and PSW registers after executing the above set of
instructions in sequence?
a. AAH and 00H
b. FFH and 66H
c. 00H and 54H
d. 00H and 00H
Answer. c
81. For which one of the following, the instruction XRA A in 8085 microprocessor
can be used?
a. Set the carry flag
b. Set the zero flag
c. Reset the carry flag and clear the accumulator
d. Transfer FFH to the accumulator
Answer. b
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82. An 8085 microprocessor is executing the programme as follows:

MVI A, 20H
MVI B, 10H
BACK: NOP
ADD B
RLC
JNC BACK
HLT
How many times the instruction NOP will be executed?
a. 4
b. 3
c. 2
d. 1
Answer. b
83. The stack pointer of an 8085 microprocessor is ABCD H. At the end of
execution of the sequence of instructions, what will be the content of the stack
pointer?
PUSH PSW
XTHL
PUSH D
JMP FC70 H
a. ABCB H
b. ABCA H
c. ABC9 H
d. ABC8 H
Answer. c
84. What is the correct 8085 assembly language instruction that stores the
contents of H and L registers into the memory locations 1080 H and 1081 H
respectively?
a. SPHL 1080 H
b. SHLD 1080 H
c. STAX 1080 H
d. SPHL 1081 H

Answer. b
85. When the operand requires for instruction is stored inside the processor, then
What this addressing mode is called?
a. Direct
b. Register
c. Implicit
d. Immediate
Answer. b
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86. Which one of the following addressing technique is not used in 8085
microprocessor?

a. Register
b. Immediate
c. Register indirect
d. Relative
Answer. d
87. In an instruction of 8085 microprocessor, how many bytes are present?

a. One or two
b. One, two or three
c. One only
d. Two or three
Answer. b
88. Which one is the indirect addressing mode in the following instructions?

a. LXI H 2050 H
b. MOV A, B
c. LDAX B
d. LDA 2050 H
Answer. c
89. The addressing mode used in the instruction JMP F347 H in case of an Intel
8085A microprocessor is which one of the following?

a. Direct
b. Register—indirect
c. Implicit
d. Immediate
Answer. d
90. Carry flag is not affected after the execution of

a. ADD B
b. SBB B
c. INR B
d. ORA B
Answer. c
91. The contents of the Program Counter (PC), when the microprocessor is
reading from 2FFF H memory location, will be

a. 2FFE H
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b. 2FFF H
c. 3000 H
d. 3001 H
Answer. c
92. If the HLT instruction of an Intel 8085A microprocessor is executed

a. the microprocessor is disconnected from the system bus till the RESET is
pressed.
b. the microprocessor halts the execution of the program and returns to the
monitor.
c. the microprocessor enters into a HALT state and the buses are tri-stated.
d. the microprocessor reloads the program counter from the locations 0024 H
and 0025 H.
Answer. c
93. The stack pointer of an 8085 A microprocessor contains ABCD H.

PUSH PSW
XTHL
PUSH D
JMP EC75 H
At the end of the execution of the above instructions, what would be the content
of the stack pointer?

a. ABCB H
b. ABCA H
c. ABC9 H
d. ABC8 H
Answer. c
94. In an Intel 8085 A, what is the content of the Instruction Register (IR)?

a. Op-code for the instruction being executed

b. Operand for the instruction being executed
c. Op-code for the instruction to be executed next
d. Operand for the instruction to be executed next
Answer. a
95. The content of the Program Counter of an intel 8085A microprocessor
specifies which one of the following?

a. The address of the instruction being executed

b. The address of the instruction executed earlier
c. The address of the next instruction to be executed
d. The number of instructions executed so far
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Answer. c
96. Which one of the following statement does not describe
property/characteristic of a stack pointer register in 8085 microprocessor?

a. It points to the top of the stack.

b. It is UP/DOWN counter
c. It is automatically initialized to 0000 H on power-on
d. It is a 16-bit register
Answer. c
97. Which one of the following instructions is a 3-byte instruction?

a. MVI A
b. LDAX B
c. JMP 2050 H
d. MOV A,M
Answer. c
98. In 8085, the DAA instruction is used for

a. Direct Address Accumulator

b. Double Add Accumulator
c. Decimal Adjust Accumulator
d. Direct Access Accumulator
Answer. c
99. When an 8086 executes an INT type instruction, it?

a. Resets both IF and TF flags

b. Resets all flags
c. Sets both IF and TF
d. Resets the CF and TF
Answer. a
100. When an 8086 executes an INT type instruction, it?

a. Resets both IF and TF flags

b. Resets all flags
c. Sets both IF and TF
d. Resets the CF and TF
Answer. a
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UNIT-4

ASSEMBLY LANGUAGE PROGRAMMING Multiple Choice Questions :-

1) Assembly language programs are written using
A) Hex code
B) Mnenonics
C) ASCII code
D) None of these View

ANS: B

2) For execution of an interrupt applied at INTR, number of states required by

8085 Microprocessor are
A) 4
B) 6
C) 12
D) 18

ANS: C

3) In 8085 which is/are the 16 bit registers?

A) Program Counter
B) Stack Pointer
C) Both A) & B)
D) None of the above

ANS: C

4) How many memory locations are required to store the instruction LXIH,
0800H in an 8085 assembly language program?
A) 1
B) 2
C) 3
D) 4

ANS: B

5) The instruction DEC N inform the assembler to....

A) Decrement the content of N
B) Decrement the data addressed by N
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C) Convert signed decimal number to binary

D) None of the above

ANS: A

6) In 8085 microprocessor, the value of the most significant bit of the result
following the execution of any arithmetic or Boolean instruction is stored in
the
A) carry status flag
B) auxiliary carry status flag
C) sign status flag
D) zero status flag

ANS: C

7) Instructions performing actions in assembly language are called

A) imperative statements
B) declarative statements
C) directive statements
D) none of the above
ANS: A

8) What is the content of Stack Pointer ?

A) Address of the current instruction
B) Address of the next instruction
C) Address of the top element of the stack
D) None of the above
ANS: C

9) Which of the following interrupt has highest Priority?

A) INTR
B) TRAP
C) RST 7.5
D) RST 6.5

ANS: B

10) Number of machine cycles required for RET instruction in 8085

microprocessor is
A) 1
B) 2
C) 3
D) 5
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ANS: C

11) __________ converts the programs written in assembly language into

machine instructions.
a) Machine compiler
b) Interpreter
c) Assembler
d) Converter

Answer: c
Clarification: An assembler is a software used to convert the programs into
machine instructions.
12) The instructions like MOV or ADD are called as ______
a) OP-Code
b) Operators
c) Commands
d) None of the mentioned

Answer: a
Clarification: This OP – codes tell the system what operation to perform on the
operands.
13) The alternate way of writing the instruction, ADD #5,R1 is ______
a) ADD [5],[R1];
b) ADDI 5,R1;
c) ADDIME 5,[R1];
d) There is no other way

Answer: b
Clarification: The ADDI instruction, means the addition is in immediate
addressing mode.
14) Instructions which won’t appear in the object program are called as
_____
a) Redundant instructions
b) Exceptions
c) Comments
d) Assembler Directives

Answer: d
Clarification: The directives help the program in getting compiled and hence
won’t be there in the object code.
15) The assembler directive EQU, when used in the instruction: Sum EQU
200 does ________
a) Finds the first occurrence of Sum and assigns value 200 to it
b) Replaces every occurrence of Sum with 200
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c) Re-assigns the address of Sum by adding 200 to its original address

d) Assigns 200 bytes of memory starting the location of Sum

Answer: b
Clarification: This basically is used to replace the variable with a constant value.
16) The purpose of the ORIGIN directive is __________
a) To indicate the starting position in memory, where the program block is
to be stored
b) To indicate the starting of the computation code
c) To indicate the purpose of the code
d) To list the locations of all the registers used

Answer: a
Clarification: This does the function similar to the main statement.
17) The directive used to perform initialization before the execution of
the code is ______
a) Reserve
b) Store
c) Dataword
d) EQU

Answer: c
Clarification: None.
18) _____ directive is used to specify and assign the memory required for
the block of code.
a) Allocate
b) Assign
c) Set
d) Reserve

Answer: d
Clarification: This instruction is used to allocate a block of memory and to store
the object code of the program there.
19) _____ directive specifies the end of execution of a program.
a) End
b) Return
c) Stop
d) Terminate

Answer: b
Clarification: This instruction directive is used to terminate the program
execution.
20) The last statement of the source program should be _______
a) Stop
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b) Return
c) OP
d) End

Answer: d
Clarification: This enables the processor to load some other process.
21) When dealing with the branching code the assembler ___________
a) Replaces the target with its address
b) Does not replace until the test condition is satisfied
c) Finds the Branch offset and replaces the Branch target with it
d) Replaces the target with the value specified by the DATAWORD directive

Answer: c
Clarification: When the assembler comes across the branch code, it immediately
finds the branch offset and replaces it with it.
22) The assembler stores all the names and their corresponding values in
______
a) Special purpose Register
b) Symbol Table
c) Value map Set
d) None of the mentioned

Answer: b
Clarification: The table where the assembler stores the variable names along with
their corresponding memory locations and values.
23) The assembler stores the object code in ______
a) Main memory
b) Cache
c) RAM
d) Magnetic disk

Answer: d
Clarification: After compiling the object code, the assembler stores it in the
magnetic disk and waits for further execution.
24) The utility program used to bring the object code into memory for
execution is ______
a) Loader
b) Fetcher
c) Extractor
d) Linker

Answer: a
Clarification: The program is used to load the program into memory.
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25) To overcome the problems of the assembler in dealing with

branching code we use _____
a) Interpreter
b) Debugger
c) Op-Assembler
d) Two-pass assembler

Answer: d
Clarification: This creates entries into the symbol table first and then creates the
object code.
26) In 8085 microprocessor, the address for ‘TRAP’ interrupt is
a. 0024 H
b. 002C H
c. 0034 H
d. 003C H
Answer. a
27) A ‘DAD H” instruction is the same as shifting each bit by one position
to the
a. left
b. right
c. left with a zero inserted in LSB position
d. right with a zero inserted in LSB position
Answer. c
28) When a program is being executed in an 8085 microprocessor, its
program counter contains
a. the memory address as the instruction that is to be executed next.
b. the memory address of the instruction that is being currently matched.
c. the total number of instructions in the program being executed.
d. the number of instructions in the current program that have already been
executed.
Answer. a
29) Which of the following data transfer is not possible in
microprocessor?
a. Memory to accumulator
b. Accumulator to memory
c. Memory to memory
d. I/O device to accumulator
Answer. c
30) LOADER is a program that
a. loads the memories and generates a hex file
b. loads the hex file and converts to the executable file
c. loads the COM file and generates the binary code
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d. loads English like command and generates the binary code

Answer. b
31) Which of the following instructions is closest match to the
instruction POP PC?
a. RET
b. PCHL
c. POP PSW
d. DAD SP
Answer. a
32) How many machine cycles are required by STA instruction?
a. 2
b. 3
c. 4
d. 5
Answer. c
33) Which of the following 8085 instruction will require maximum T-
states for execution?
a. XRI byte
b. STA address
c. CALL address
d. JMP address
Answer. c
34) In 8085 microprocessor, which mode of addressing does the
instruction CMP M use?
a. Direct addressing
b. Register addressing
c. Indirect addressing
d. Immediate addressing
Answer. c
35) With reference to 8085 microprocessor, which of the following
statements are correct?
1. INR is 1 byte instruction
2. OUT is 2 byte instruction
3. STA is 3 byte instruction
a. 1 and 2 only
b. 2 and 3 only
c. 1 and 3 only
d. 1, 2 and 3
Answer. d
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36) Assume that the accumulator and the register C of 8085

microprocessor contain respectively F0 H
and OF H initially. What will be the content of accumulator after execution
of instruction ADD C?
a. 00 H
b. FF H
c. EF H
d. FE H
Answer. b
37) It is desired to multiply the numbers 0A H by OB H and store the
result in the accumulator. The numbers are available in registers B and C
respectively. A part of the 8085 program for this purpose is given below:
MVI A, OO H
Loop; ………..
………..
………..
HLT END
The sequence of instruction to complete the program would be
a. JNZ LOOP; ADD B, DCR C

b. ADD B; JNZ LOOP; DCR C

c. DCR C; JNZ LOOP; ADD B

d. ADD B; DCR C; JNZ LOOP

Answer. d
38) Find the content of the accumulator after the execution of the
following program:
MVI A, F0 H
ORI FF H
XRI F0 H
a. 00 H
b. F0 H
c. 0F H
d. FF H
Answer. c
39) The following program starts at location 0100 H
LXI SP, 00FF
LXI H, 0701 H
MVI A, 20 H
SUB M
The content of accumulator when the program counter reaches 0107 H is
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a. 20 H
b. 02 H
c. 00 H
d. FF H
Answer. c
40) The difference between 8085 instructions RST n and PCHL is
a. RST n is equivalent to a sub-routine call while PCHL is equivalent to
unconditional branch.
b. RST n uses direct addressing while PCHL uses register indirect addressing.
c. RST n is a software interrupt while PCHL simulates a hardware interrupt
d. RST n resets the processor while PCHL restarts the processor.
Answer. a
41) The content of accumulator are 70 H. Initially all flags are zero. What
will be values of CY and S after executing instruction RLC?
a. CY = 0 and S = 0
b. CY = 1 and S = 1
c. CY = 1 and S = 0
d. CY = 0 and S = 1
Answer. d
42) A software delay subroutine is written as given below:
DELAY: MVI H, 255D H
MVI L, 255D H
LOOP: DCR L
JNZ LOOP
DCR H
JNZ LOOP
How many times DCR instruction will be executed?

a. 255
b. 510
c. 65025
d. 65279
Answer. d
43) What is content of accumulator of 8085 microprocessor after the
execution of XRI F0 H instruction?
a. Only the upper nibble of accumulator is complemented
b. Only the lower nibble is complemented
c. Only the upper nibble is reset to zero
d. Only the lower nibble is reset to zero
Answer. a
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44) The 8085 programming manual says that it takes seven T states to
fetch and execute the MOV instruction. If the system clock has a frequency
of 2.5 MHz, how long is an instruction Cycle?

a. 2.8 s
b. 2.5ns
c. 2.8 ns
d. 2.8 μs
Answer. d
45) The instruction PCHL, in 8085 is used for

a. Load PC with contents of HL.

b. Load HL with contents of memory location pointed by PC.
c. Load HL with contents of PC
d. Load PC with the contents of memory location pointed by HL pair.
Answer. a
46) The following instruction copies a byte of data from the accumulator
into the memory address given in the instruction

a. STA address
b. LDAX B
c. LHLD address
d. LDA address
Answer. a
47) The instruction that exchanges top of stack with HL pair is

a. XTHL
b. SPHL
c. PUSH H
d. POP H
Answer. a
48) In 8085 microprocessor, during PUSH PSW Operation, Stack pointer
is

a. Decremented by one
b. Decremented by two
c. Incremented by one
d. Incremented by two
Answer. b
49) While a program is being executed in an Intel 8085 microprocessor,
the program counter of the microprocessor contains:
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[Link] memory address of the instruction that is being currently executed.

[Link] memory address of the instruction that is to be executed next.
[Link] number of instructions that have already been executed.
[Link] total number of instructions in the current program still to be
executed.
Answer. b
50) The description of a program counter (PC) in 8085 microprocessor is
a. An up/down counter
b. An 8-bit register
c. Initialized automatically by microprocessor
d. Used to point to stack memory area
Answer. c

UNIT-5

Microprocessors Questions and Answers – Programmable DMA Interface

8237 (Part-1)

1. The block of 8237 that decodes the various commands given to the 8237 by the
CPU is
a) timing and control block
b) program command control block
c) priority block
d) none of the mentioned

Answer: b
Explanation: The program control block decodes various commands given to the
8237 by the CPU before servicing a DMA request.

2. The priority between the DMA channels requesting the services can be
resolved by
a) timing and control block
b) program command control block
c) priority block
d) none of the mentioned

Answer: c
Explanation: The priority encoder block resolves the priority between the DMA
channels requesting the services.
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3. The register that holds the current memory address is

a) current word register
b) current address register
c) base address register
d) command register

Answer: b
Explanation: The current address register holds the current memory address. The
current address register is accessed during the DMA transfer.

4. The register that holds the data byte transfers to be carried out is
a) current word register
b) current address register
c) base address register
d) command register

Answer: a
Explanation: The current word register is a 16-bit register that holds the data
transfers. The word count is decremented after each transfer, and the new value
is stored again in the register.

5. When the count becomes zero in the current word register then
a) Input signal is enabled
b) Output signal is enabled
c) EOP (end of process) is generated
d) Start of process is generated

Answer: c
Explanation: When the count becomes zero, the EOP signal is generated. This can
be written in successive bytes by the CPU, in program mode.

6. The current address register is programmed by the CPU as

a) bit-wise
b) byte-wise
c) bit-wise and byte-wise
d) none of the mentioned
View Answer
Explanation: The current address register is byte-wise programmed by the CPU,
i.e. lower byte first and the higher byte later.

7. Which of these register’s contents is used for auto-initialization (internally)?

a) current word register
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b) current address register

c) base address register
d) command register

Answer: c
Explanation: The contents of base address register cannot be read by the CPU.
These contents are used internally for auto-initialization.

8. The register that maintains an original copy of the respective initial current
address register and current word register is
a) mode register
b) base address register
c) command register
d) mask register

Answer: b
Explanation: The base address register maintains an original copy of the current
address register and current word register, before incrementing or
decrementing.

9. The register that can be automatically incremented or decremented, after each

DMA transfer is
a) mask register
b) mode register
c) command register
d) current address register

Answer: d
Explanation: The address is automatically incremented or decremented after
each DMA transfer, and the resulting address value is again stored in the current
address register.

10. Which of the following is a type of DMA transfer?

a) memory read
b) memory write
c) verify transfer
d) all of the mentioned

Answer: d
Explanation: Memory read, memory write and verify transfer are the three types
of DMA transfer.
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Microprocessors Questions and Answers – 8255 programmable peripheral

interface-(Part-2)

Question 1: How many pins does the 8255 PPI IC contains?

a. 24
b. 20
c. 32
d. 40

Answer: d. 40

Question 2: In which mode do all the Ports of the 8255 PPI work as Input-Output
units for data transfer?

a. BSR mode
b. Mode 0 of I/O mode
c. Mode 1 of I/O mode
d. Mode 2 of I/O mode

Answer: b. Mode 0 of I/O mode

Question 3: Which of the following pins are responsible for handling the on the
Read Write control logic unit of the 8255 PPI?

a. CS'
b. RD'
c. WR'
d. ALL of the above

Answer: d. All of the above

Question 4: In which of the following modes is the 8255 PPI capable of

transferring data while handshaking with the interfaced device?

a. BSR mode
b. Mode 0 of I/O mode
c. Mode 1 of I/O mode
d. Mode 2 of I/O mode

Answer: c. Mode 1 of I/O mode

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Question 5: How many bits of data can be transferred between the 8255 PPI and
the interfaced device at a time? or What is the size of internal bus of the 8255
PPI?

a. 16 bits
b. 12 bits
c. 8 bits
d. None of the above

Answer: c. 8 bits

Question 6: Which port of the 8255 PPI is capable of performing the handshaking
function with the interfaced devices?

a. Port A
b. Port B
c. Port C
d. All of the above

Answer: c. Port C

Question 7: In which of the following modes of the 8255 PPI, only port C is taken
into consideration?

a. BSR mode
b. Mode 0 of I/O mode
c. Mode 1 of I/O mode
d. Mode 2 of I/O mode

Answer: a. BSR mode

Question 8: In mode 2 of I/O mode, which of the following ports are capable of
transferring the data in both the directions?

a. Port A
b. Port B
c. Port C
d. All of the above

Answer: a. Port A

Question 9: In which of the following modes we do not consider the D6, D5 and
D4 bits of the control word?

a. BSR mode
b. Mode 0 of I/O mode
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c. Mode 1 of I/O mode

d. Mode 2 of I/O mode

Answer: a. BSR mode

Question 10: How many data lines in total are there in the 8255 PPI IC?

a. 8 data lines
b. 32 data lines
c. 24 data lines
d. None of the above

Answer: c. 24 data lines

Microprocessors Questions and Answers – 8253/8254programmable

timer/counter-(Part-3)

1. The number of counters that are present in the programmable timer device
8254 is
a) 1
b) 2
c) 3
d) 4

Answer: c
Explanation: There are three counters that can be used as either counters or
delay generators.

2. The operation that can be performed on control word register is

a) read operation
b) write operation
c) read and write operations
d) none

Answer: b
Explanation: The control word register can only be written and cannot be read.

3. The mode that is used to interrupt the processor by setting a suitable terminal
count is
a) mode 0
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b) mode 1
c) mode 2
d) mode 3

Answer: a
Explanation: Mode 0 is also called as an interrupt on the terminal count.

4. In mode 2, if N is loaded as the count value, then after (N-1) cycles, the output
becomes low for
a) 1 clock cycle
b) 2 clock cycles
c) 3 clock cycles
d) 4 clock cycles

Answer: a
Explanation: After (N-1) cycles, the output becomes low for only 1 clockcycle. If
the count N is reloaded and again the output becomes high and remains so for (N-
1) clock pulses.

5. The generation of a square wave is possible in the mode

a) mode 1
b) mode 2
c) mode 3
d) mode 4

Answer: c
Explanation: When the count N loaded is even, then for half of the count, the
output remains high and for the remaining half it remains low. If the count loaded
is odd, the first clock pulse decrements it by 1 resulting in an even count value.

6. In control word register, if SC1=0 and SC0=1, then the counter selected is
a) counter 0
b) counter 1
c) counter 2
d) none

Answer: b
Explanation: SC denotes select counter.
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7. In control word format, if RL1=1, RL0=1 then the operation performed is

a) read/load least significant byte only
b) read/load most significant byte only
c) read/load LSB first and then MSB
d) read/load MSB first and then LSB

Answer: c
Explanation: To access 16 bit, first LSB is loaded first, and then MSB.

8. If BCD=0, then the operation is

a) decimal count
b) hexadecimal count
c) binary count
d) octal count

Answer: b
Explanation: If BCD=0 then hexadecimal count. If BCD=1, then the operation is
BCD count.

9. The counter starts counting only if

a) GATE signal is low
b) GATE signal is high
c) CLK signal is low
d) CLK signal is high

Answer: b
Explanation: If the GATE signal is enabled, then the counter starts counting.

10. The control word register contents are used for

a) initializing the operating modes
b) selection of counters
c) choosing binary/BCD counters
d) all of the mentioned

Answer: d
Explanation: The control word register contents are used for
i) initializing the operating modes (mode 0-mode 4)
ii) selection of counters (counter0-counter2)
iii) choosing binary or BCD counters
iv) loading of the counter registers.
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Microprocessors Questions and Answers – 8259 programmable interrupt

controller-(Part-4)

1. The number of hardware interrupts that the processor 8085 consists of is

a) 1
b) 3
c) 5
d) 7
View Answer

Answer: c
Explanation: The processor 8085 has five hardware interrupt pins. Out of these
five, four pins were alloted fixed vector addresses but the pin INTR was not
alloted by vector address, rather an external device was supposed to hand over
the type of the interrupt to the microprocessor.

2. The register that stores all the interrupt requests in it in order to serve them
one by one on a priority basis is
a) Interrupt Request Register
b) In-Service Register
c) Priority resolver
d) Interrupt Mask Register

Answer: a
Explanation: The interrupts at IRQ input lines are handled by Interrupt Request
Register internally.

3. The register that stores the bits required to mask the interrupt inputs is
a) In-service register
b) Priority resolver
c) Interrupt Mask register
d) None

Answer: c
Explanation: Also, Interrupt Mask Register operates on IRR(Interrupt Request
Register) at the direction of the Priority Resolver.
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4. The interrupt control logic

a) manages interrupts
b) manages interrupt acknowledge signals
c) accepts interrupt acknowledge signal
d) all of the mentioned

Answer: d
Explanation: The interrupt control logic performs all the operations that are
involved within the interrupts like accepting and managing interrupt
acknowledge signals, interrupts.

5. In a cascaded mode, the number of vectored interrupts provided by 8259A is

a) 4
b) 8
c) 16
d) 64

Answer: d
Explanation: A single 8259A provides 8 vectored interrupts. In cascade mode, 64
vectored interrupts can be provided.

6. When the PS(active low)/EN(active low) pin of 8259A used in buffered mode,
then it can be used as a
a) input to designate chip is master or slave
b) buffer enable
c) buffer disable
d) none

Answer: b
Explanation: When the pin is used in buffered mode, then it can be used as a
buffer enable to control buffer transreceivers. If it is not used in buffered mode,
then the pin is used as input to designate whether the chip is used as a master or
a slave.

7. Once the ICW1 is loaded, then the initialization procedure involves

a) edge sense circuit is reset
b) IMR is cleared
c) slave mode address is set to 7
d) all of the mentioned

Answer: d
Explanation: The initialization procedure involves
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i) edge sense circuit is reset.

ii) IMR is cleared.
iii) IR7 input is assigned the lowest priority.
iv) slave mode address is set to 7
v) special mask mode is cleared and the status read is set to IRR.

8. When non-specific EOI command is issued to 8259A it will automatically

a) set the ISR
b) reset the ISR
c) set the INTR
d) reset the INTR

Answer: b
Explanation: When non-specific EOI command is issued to 8259A it will
automatically reset the highest ISR.

9. In the application where all the interrupting devices are of equal priority, the
mode used is
a) Automatic rotation
b) Automatic EOI mode
c) Specific rotation
d) EOI

Answer: a
Explanation: The automatic rotation is used in the applications where all the
interrupting devices are of equal priority.

Microprocessors Questions and Answers – 8251 USART and

RS232C- (Part-5)

1. Which of the following is not a mode of data transmission?

a) simplex
b) duplex
c) semi duplex
d) half duplex

Answer: c
Explanation: Basically, there are three modes of data transmission. simplex,
duplex and half duplex.
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2. If the data is transmitted only in one direction over a single communication

channel, then it is of
a) simplex mode
b) duplex mode
c) semi duplex mode
d) half duplex mode

Answer: a
Explanation: In simplex mode, the data transmission is unidirectional. For
example, a CPU may transmit data for a CRT display unit in this mode.

3. If the data transmission takes place in either direction, but at a time data may
be transmitted only in one direction then, it is of
a) simplex mode
b) duplex mode
c) semi duplex mode
d) half duplex mode

Answer: d
Explanation: In half duplex mode, data transmission is bidirectional but not at a
time. For example, Walkie-Talkie.

4. In 8251A, the pin that controls the rate at which the character is to be
transmitted is
a) TXC(active low)
b) TXC(active high)
c) TXD(active low)
d) RXC(active low)

Answer: a
Explanation: Transmitter Clock Input (TXC(active low)) is a pin that controls the
rate at which the character is to be transmitted.

5. TXD(Transmitted Data Output) pin carries serial stream of the transmitted

data bits along with
a) start bit
b) stop bit
c) parity bit
d) all of the mentioned

Answer: d
Explanation: Transmitted Data Output pin carries a serial stream of the
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transmitted data bits along with other information like start bits, stop bits and
parity bits etc.

6. The signal that may be used either to interrupt the CPU or polled by the CPU is
a) TXRDY(Transmitter ready)
b) RXRDY(Receiver ready output)
c) DSR(active low)
d) DTR(active low)

Answer: b
Explanation: RXRDY(Receiver ready output) may be used either to interrupt the
CPU or polled by the CPU.

7. The disadvantage of RS-232C is

a) limited speed of communication
b) high-voltage level signaling
c) big-size communication adapters
d) all of the mentioned

Answer: d
Explanation: RS232C has been used for long and has a few disadvantages like
limited speed of communication, high-voltage level signaling and big-size
communication adapters.

8. The USB supports the signaling rate of

a) full-speed USB 1.0 at rate of 12 Mbps
b) high-speed USB 2.0 at rate of 480 Mbps
c) super-speed USB 3.0 at rate of 596 Mbps
d) all of the mentioned

Answer: d
Explanation: The USB standards support the signaling rates. Also, USB signaling is
implemented in a differential in low- and full-speed options.

9. The bit packet that commands the device either to receive data or transmit
data in transmission of USB asynchronous communication is
a) Handshake packet
b) Token packet
c) PRE packet
d) Data packet