ST7263BDx ST7263BHx

ST7263BKx ST7263BE
Low speed USB 8-bit MCU family with up to 32K Flash/ROM,
DFU capability, 8-bit ADC, WDG, timer, SCI & I²C

■ Memories
– 4, 8, 16 or 32 Kbytes program memory: high
density Flash (HDFlash), FastROM or ROM
with Read-Out and Write protection
– In-application programming (IAP) and in-cir- PSDIP32 LQFP48 (7x7)
cuit programming (ICP)
– 384, 512 or 1024 bytes RAM memory (128-
byte stack)
■ Clock, reset and supply management
– Run, Wait, Slow and Halt CPU modes
– 12 or 24 MHz oscillator SO34(Shrink) SO24 QFN40 (6x6)
– RAM Retention mode
■ 2 timers
– Optional low voltage detector (LVD)
■ USB (universal serial bus) Interface – Programmable watchdog
– DMA for low speed applications compliant – 16-bit timer with 2 Input Captures, 2 Output
with USB 1.5 Mbs (version 2.0) and HID spec- Compares, PWM output and clock input
ifications (version 1.0) ■ 2 communication Interfaces
– Integrated 3.3 V voltage regulator and trans- – Asynchronous serial communications Inter-
ceivers face
– Supports USB DFU class specification – I²C multimaster Interface up to 400 kHz
– Suspend and Resume operations ■ Instruction Set
– 3 endpoints with programmable Input/Output – 63 basic instructions
configuration – 17 main addressing modes
■ Up to 27 I/O ports – 8 x 8 unsigned multiply instruction
– Up to 8 high sink I/Os (10 mA at 1.3 V) – True bit manipulation
– 2 very high sink true open drain I/Os (25 mA ■ Development tools
at 1.5 V) – Versatile development tools (under Windows)
– Up to 8 lines individually programmable as in- including assembler, linker, C-compiler, ar-
terrupt inputs chiver, source level debugger, software li-
■ 1 analog peripheral brary, hardware emulator, programming
– 8-bit A/D converter with 8 or 12 channels boards and gang programmers, HID and DFU
software layers
Table 1. Device summary
ST7263BH2, ST7263BK1, ST7263BK2, ST7263BK4, ST7263BE1, ST7263BE2,
Features ST7263BD6
ST7263BH6 ST7263BK6 ST7263BE4, ST7263BE6
Program memory
32K 16K 8K 32K 32K 16K 8K 4K 32K 16K 8K 4K
(Flash / ROM) - bytes
1024 512 384 1024 1024 512 384 384 1024 512 384 384
RAM (stack) - bytes
(128) (128) (128) (128) (128) (128) (128) (128) (128) (128) (128) (128)
Standard peripherals Watchdog timer, 16-bit timer, USB
Other peripherals SCI, I²C, ADC SCI, ADC ADC SCI, I²C
I/Os (high current) 27 (10) 19 (10) 14 (6)
Operating supply 4.0 V to 5.5 V
CPU frequency 8 MHz (with 24 MHz oscillator) or 4 MHz (with 12 MHz oscillator)
Operating temp. 0 °C to +70 °C
QFN40 SDIP32/ QFN40
Packages LQFP48 (7x7) SDIP32/SO34 SO24
(6x6) SO34 (6x6)

Rev. 7.0

August 2007 1/145

1
 Table of Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2.1 Read-Out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4 ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.5 IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.6 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5 Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6 CPU registers (Cont’d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7 Reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1.1 Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1.2 Watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1.3 External reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.2 Clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.2.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.2.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.1 Interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.2 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.3 Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.4 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.3 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.3.1 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.3.2 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.3.3 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10.3.4 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10.3.5 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11 Miscellaneous register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 .... 41
12 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
12.1 Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

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12.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
12.1.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
12.1.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
12.1.4 Software Watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
12.1.5 Hardware Watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
12.1.6 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
12.1.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
12.1.8 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12.2 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12.2.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12.2.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12.2.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
12.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
12.2.6 Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
12.2.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
12.3 Serial communications interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
12.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
12.3.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
12.3.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
12.3.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.3.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
12.3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
12.3.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
12.4 USB interface (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
12.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
12.4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
12.4.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
12.4.4 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
12.4.5 Programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
12.5 I²C bus interface (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
12.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
12.5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
12.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
12.5.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
12.5.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.5.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.6 8-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.6.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.6.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.6.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
13 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
. . . 102
13.1 ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
13.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

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13.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
13.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
13.2 insTruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
14 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
14.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
14.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
14.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
14.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
14.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
14.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
14.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
14.2.1 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
14.2.2 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
14.2.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
14.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
14.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
14.3.2 Operating conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . 110
14.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
14.5 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
14.5.1 General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
14.5.2 Control timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
14.5.3 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
14.6 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
14.6.1 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
14.6.2 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
14.7 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
14.7.1 Functional EMS (Electromagnetic susceptibility) . . . . . . . . . . . . . . . . . . . . . . . . . 115
14.7.2 Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
14.7.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . . . . . . . . 116
14.8 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
14.8.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
14.8.2 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
14.9 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
14.9.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
14.10Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
14.10.1 USB - universal bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
14.10.2 SCI - serial communication interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
14.10.3 I2C - Inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
14.118-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
15 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
15.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145. . . 128
15.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

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15.3 Soldering and glueability information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
16 Device configuration and ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
16.1 Option Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
16.2 Device ordering information and transfer of customer code . . . . . . . . . . . . . . . . . . . . . . . 134
16.3 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
16.3.1 Evaluation tools and starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
16.3.2 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
16.3.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
16.3.4 Order codes for ST7263B development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
16.4 ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
17 Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
17.1 PA2 limitation with OCMP1 enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
17.2 Unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
17.3 USB behavior with LVD disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
17.4 I2C multimaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
17.5 Halt mode power consumption with ADC on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
17.6 SCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

145

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1 Introduction
The ST7263B microcontrollers form a sub-family regulator and transceivers (no external compo-
of the ST7 MCUs dedicated to USB applications. nents are needed).
The devices are based on an industry-standard 8- – 8-bit analog-to-digital converter (ADC) with 12
bit core and feature an enhanced instruction set. multiplexed analog inputs
They operate at a 24 MHz or 12 MHz oscillator fre-
quency. Under software control, the ST7263B – Industry standard asynchronous SCI serial inter-
MCUs may be placed in either Wait or Halt modes, face
thus reducing power consumption. The enhanced – Watchdog
instruction set and addressing modes afford real
– 16-bit timer featuring an external clock input, 2
programming potential. In addition to standard 8-
Input Captures, 2 Output Compares with Pulse
bit data management, the ST7263B MCUs feature Generator capabilities
true bit manipulation, 8x8 unsigned multiplication
and indirect addressing modes. The devices in- – Fast I²C multimaster interface
clude an ST7 Core, up to 32Kbytes of program – Low voltage reset (LVD) ensuring proper power-
memory, up to 1024 bytes of RAM, 27 I/O lines on or power-off of the device
and the following on-chip peripherals:
The ST72F63B devices are Flash versions. They
– USB low speed interface with 3 endpoints with support programming in IAP mode (in-application
programmable in/out configuration using the programming) via the on-chip USB interface.
DMA architecture with embedded 3.3V voltage
Figure 1. General block diagram
INTERNAL
CLOCK
OSCIN OSC/3
OSCILLATOR
OSCOUT
I²C
OSC/4 or OSC/2
for USB2)
VDD PA[7:0]
POWER PORT A
(8 bits)
VSS SUPPLY
16-BIT TIMER

WATCHDOG
PORT B
ADDRESS AND DATA BUS

PB[7:0]
RESET CONTROL (8 bits)
ADC1)
8-BIT CORE PD[7:0]
ALU (8 bits)
PORT D
LVD

USB DMA PORT C

SCI PC[2:0]
VPP/TEST PROGRAM (3 bits)
(UART)
MEMORY
VDDA (32K bytes)
USB SIE USBDP
VSSA RAM USBDM
(1024 bytes) USBVCC

1) ADC channels:
12 on 48-pin devices (Port B and Port D[3:0])
8 on 34 and 32-pin devices (Port B)
None on 24-pin devices
2) 12 or 24 MHz OSCIN frequency required to generate 6 MHz USB clock.
3) The drive from USBVCC is sufficient to only drive an external pull-up in additoin to the internal transceiver

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2 Pin description
Figure 2. 48-pin LQFP package pinout

PA1(25mA)/SDA/ICCDATA

PA2(25mA)/SCL/ICCCLK
PD3/AIN11
PD2/AIN10
PA0/MCO

PD1/AIN9
PD0/AIN8
PD7
PD6
PD5
PD4

NC
48 47 46 45 44 43 42 41 40 39 38 37
VSSA 1 36 PA3/EXTCLK
USBDP 2 35 PA4/ICAP1/IT1
USBDM 3 34 PA5/ICAP2/IT2
USBVCC 4 33 PA6/OCMP1/IT3
VDDA 5 32 PA7/OCMP2/IT4
VDD 6 31 PB0(10mA)/AIN0
OSCOUT 7 30 PB1(10mA)/AIN1
OSCIN 8 29 PB2(10mA)/AIN2
VSS 9 28 PB3(10mA)/AIN3
USBOE/PC2 10 27 PB4(10mA)/AIN4/IT5
NC 11 26 PB5(10mA)/AIN5/IT6
NC 12 25 VPP/TEST
13 14 15 16 17 18 19 20 21 22 23 24
RESET

AIN6/IT7/PB6(10mA)
TDO/PC1
RDI/PC0

NC
NC
NC
NC
NC
NC
NC
AIN7/IT8/PB7(10mA)

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Figure 3. 40-lead QFN package pinout

PA1(25mA)/SDA/ICCDATA

PA2(25mA)/SCL/ICCCLK
PD31)/AIN11
PD21)/AIN10
PD11)/AIN9
PD01)/AIN8
PD71)
PD61)
PD51)
PD41)
40 39 38 37 36 35 34 33 32 31
PA0/MCO 1 30 PA3/EXTCLK
VSSA 2 29 PA4/ICAP1/IT1
USBDP 3 28 PA5/ICAP2/IT2
USBDM 4 27 PA6/OCMP1/IT3
USBVCC 5 26 PA7/OCMP2/IT4
VDDA 6 25 PB0(10mA)/AIN0
VDD 7 24 PB1(10mA)/AIN1
OSCOUT 8 23 PB2(10mA)/AIN2
OSCIN 9 22 PB3(10mA)/AIN3
VSS 10 21 PB4(10mA)/AIN4/IT5
11 12 13 14 15 16 17 18 19 20
VPP/TEST
IT6/AIN5/PB5(10mA)
IT7/AIN6/PB6(10mA)
USBOE/PC2

RDI/PC0
TDO/PC1

NC
NC
RESET

IT8/AIN7/PB7(10mA)

Note:
1. Port D functions are not available on the 8K version of the QFN40 package (ST7263BK2)
and should not be connected.

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Pin description (Cont’d)

Figure 4. 34-pin SO package pinout

VDD 34 VDDA
1
OSCOUT 33 USBVCC
2
OSCIN 32 USBDM
3
VSS 4 31 USBDP
PC2/USBOE 5 30 VSSA
PC1/TDO 6 29 PA0/MCO

PC0/RDI 7 28 PA1(25mA)/SDA/ICCDATA
RESET 8 27 NC
NC 9 26 NC
AIN7/IT8/PB7(10mA) 10 25 NC
AIN6/PB6/IT7(10mA) 11 24 PA2(25mA)/SCL/ICCCLK
VPP/TEST 12 23 PA3/EXTCLK
AIN5/IT6/PB5(10mA) 13 22 PA4/ICAP1/IT1
AIN4/IT5/PB4(10mA) 14 21 PA5/ICAP2/IT2
AIN3/PB3(10mA) 15 20 PA6/OCMP1/IT3
AIN2/PB2(10mA) 16 19 PA7/OCMP2/IT4
AIN1/PB1(10mA) 17 18 PB0(10mA)/AIN0

Figure 5. 32-pin SDIP package pinout

VDD 1 VDDA
32
OSCOUT 2 31 USBVCC
OSCIN 3 30 USBDM
VSS 4 29 USBDP
PC2/USBOE 5 28 VSSA
PC1/TDO 6 27 PA0/MCO
PC0/RDI 7 26 PA1(25mA)/SDA/ICCDATA
RESET 8 25 NC
AIN7/IT8/PB7(10mA) 9 24 NC
AIN6/IT7/PB6(10mA) 10 23 PA2(25mA)/SCL/ICCCLK
VPP/TEST 11 22 PA3/EXTCLK
AIN5/IT6/PB5(10mA) 12 21 PA4/ICAP1/IT1
AIN4/IT5/PB4(10mA) 13 20 PA5/ICAP2/IT2
AIN3/PB3(10mA) 14 19 PA6/OCMP1/IT3
AIN2/PB2(10mA) 15 18 PA7/OCMP2/IT4
AIN1/PB1/(10mA) 16 17 PB0(10mA)/AIN0

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Figure 6. 24-pin SO package pinout

VDD 1 24 USBVcc
OSCOUT 2 23 USBDM
OSCIN 3 22 USBDP
VSS 4 21 VSSA
TDO/PC1 5 20 PA0/MCO
RDI/PC0 6 19 PA1(25mA)/SDA/ICCDATA
RESET/ 7 18 PA2(25mA)/SCL/ICCCLK
IT7/PB6(10mA) 8 17 PA3/EXTCLK
VPP/TEST 9 16 PA4/ICAP1/IT1
PB3(10mA) 10 15 PA5/ICAP2/IT2
PB2(10mA) 11 14 PA7/OCMP2/IT4
USBOE/PB1(10mA) 12 13 PB0(10mA)

RESET (see Note 1): bidirectional. This active low Note 1: Adding two 100 nF decoupling capacitors
signal forces the initialization of the MCU. This on the Reset pin (respectively connected to VDD
event is the top priority non maskable interrupt. and VSS) will significantly improve product electro-
This pin is switched low when the Watchdog is trig- magnetic susceptibility performance.
gered or the VDD is low. It can be used to reset ex- Note 2: To enhance the reliability of operation, it is
ternal peripherals. recommended that VDDA and VDD be connected to-
OSCIN/OSCOUT: input/output oscillator pin. gether on the application board. This also applies
These pins connect a parallel-resonant crystal, or to VSSA and VSS.
an external source, to the on-chip oscillator. Note 3: The USBOE alternate function is mapped
VDD/VSS (see Note 2): main power supply and on port C2 in 32/34/48 pin devices. In SO24 devic-
Ground voltages. es it is mapped on Port B1.
VDDA/VSSA (see Note 2): power supply and Note 4: The timer OCMP1 alternate function is
ground voltages for analog peripherals. mapped on Port A6 in 32/34/48 pin devices. In
Alternate Functions: Several pins of the I/O ports SO24 devices it is not available.
assume software programmable alternate func-
tions as shown in the pin description.

Legend / Abbreviations for Table 2 and Table 3:

Type: I = input, O = output, S = supply
In/Output level: CT = CMOS 0.3VDD/0.7VDD with input trigger
Output level: 10mA = 10mA high sink (Fn N-buffer only)
25mA = 25mA very high sink (on N-buffer only)
Port and control configuration:
– Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog
– Output: OD = open drain, PP = push-pull, T = True open drain
The RESET configuration of each pin is shown in
bold. This configuration is kept as long as the de-
vice is under reset state.

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 ST7263BDx ST7263BHx ST7263BKx ST7263BE

Table 2. Device pin description (QFN40, LQFP48, SO34 and SDIP32)

Pin n° Level Port / Control Main

Type
function
LQFP48

Input Output
SDIP32

Output
QFN40

Pin name Alternate function

SO34

Input
(after

float
wpu

ana
OD
PP
reset)

int
1 1 7 6 VDD S Power supply voltage (4V - 5.5V)
2 2 8 7 OSCOUT O Oscillator output
3 3 9 8 OSCIN I Oscillator input
4 4 10 9 VSS S Digital ground
5 5 11 10 PC2/USBOE I/O CT X X Port C2 USB Output Enable
SCI Transmit Data Out-
6 6 12 13 PC1/TDO I/O CT X X Port C1
put
7 7 13 14 PC0/RDI I/O CT X X Port C0 SCI Receive Data Input
8 8 14 15 RESET I/O X X Reset
- 9 15 16 NC -- Not connected
- - 16 17 NC -- Not connected
- - - 18 NC -- Not connected
- - - 19 NC -- Not connected
- - - 20 NC -- Not connected
- - - 21 NC -- Not connected
- - - 22 NC -- Not connected
9 10 17 23 PB7/AIN7/IT8 I/O CT 10mA X X X X Port B7 ADC analog input 7
10 11 18 24 PB6/AIN6/IT7 I/O CT 10mA X X X X Port B6 ADC analog input 6
11 12 19 25 VPP/TEST S Programming supply
12 13 20 26 PB5/AIN5/IT6 I/O CT 10mA X X X X Port B5 ADC analog input 5
13 14 21 27 PB4/AIN4/IT5 I/O CT 10mA X X X X Port B4 ADC analog input 4
14 15 22 28 PB3/AIN3 I/O CT 10mA X X X Port B3 ADC analog input 3
15 16 23 29 PB2/AIN2 I/O CT 10mA X X X Port B2 ADC analog input 2
16 17 24 30 PB1/AIN1 I/O CT 10mA X X X Port B1 ADC analog input 1
17 18 25 31 PB0/AIN0 I/O CT 10mA X X X Port B0 ADC analog Input 0
Timer Output Compare
18 19 26 32 PA7/OCMP2/IT4 I/O CT X X X Port A7
2
Timer Output Compare
19 20 27 33 PA6/OCMP1/IT3 I/O CT X X X Port A6
1
20 21 28 34 PA5/ICAP2/IT2 I/O CT X X X Port A5 Timer Input Capture 2
21 22 29 35 PA4/ICAP1/IT1 I/O CT X X X Port A4 Timer Input Capture 1
22 23 30 36 PA3/EXTCLK I/O CT X X Port A3 Timer External Clock
I²C serial clock, ICC
23 24 31 38 PA2/SCL/ICCCLK I/O CT 25mA X T Port A2
Clock
- - 32 39 PD01)/AIN8 I/O CT X X X Port D0 ADC analog Input 8

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Pin n° Level Port / Control Main

Type
function
LQFP48
Input Output
SDIP32

Output
QFN40

Pin name Alternate function

SO34

Input
(after

float
wpu

ana
OD
PP
reset)

int
- - 33 40 PD11)/AIN9 I/O CT X X X Port D1 ADC analog Input 9
- - 34 41 PD21) /AIN10 I/O CT X X X Port D2 ADC analog Input 10
- - 35 42 PD31)/AIN11 I/O CT X X X Port D3 ADC analog Input 11
1)
- - 36 43 PD4 I/O CT X X Port D4
- - 37 44 PD51) I/O CT X X Port D5
1)
- - 38 45 PD6 I/O CT X X Port D6
- - 39 46 PD71) I/O CT X X Port D7
- 25 - - NC -- Not connected
24 26 - - NC -- Not connected
25 27 - - NC -- Not connected
I²C serial data, ICC
26 28 40 47 PA1/SDA/ICCDATA I/O CT 25mA X T Port A1
Data
27 29 1 48 PA0/MCO I/O CT X X Port A0 Main Clock Output
28 30 2 1 VSSA S Analog ground
29 31 3 2 USBDP I/O USB bidirectional data (data +)
30 32 4 3 USBDM I/O USB bidirectional data (data -)
31 33 5 4 USBVCC 2) O USB power supply 2)
32 34 6 5 VDDA S Analog supply voltage

Note:
1. Port D functions are not available on the 8K version of the QFN40 package (ST7263BK2) and should not be connect-
ed.
2. The drive from USBVcc is sufficient to only drive an external pull-up in addition to the internal transceiver.

Table 3. Device pin description (SO24)

Pin n° Level Port / Control
Main
Type

Input Output
Output

Pin Name Function Alternate Function

SO24

Input

(after reset)
float
wpu

ana
OD
PP
int

1 VDD S Power supply voltage (4V - 5.5V)

2 OSCOUT O Oscillator output
3 OSCIN I Oscillator input
4 VSS S Digital ground
SCI Transmit Data Out-
5 PC1/TDO I/O CT X X Port C1
put
6 PC0/RDI I/O CT X X Port C0 SCI Receive Data Input
7 RESET I/O X X Reset

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Pin n° Level Port / Control

Main

Type
Input Output

Output
Pin Name Function Alternate Function
SO24

Input
(after reset)

float
wpu

ana
OD
PP
int
8 PB6/IT7 I/O CT 10mA X X X X Port B6
9 VPP/TEST S Programming supply
10 PB3 I/O CT 10mA X X X Port B3
11 PB2 I/O CT 10mA X X X Port B2
12 PB1/USBOE I/O CT 10mA X X X Port B1 USB Output Enable
13 PB0 I/O CT 10mA X X X Port B0
14 PA7/OCMP2/IT4 I/O CT X X X Port A7 Timer Output Compare 2
15 PA5/ICAP2/IT2 I/O CT X X X Port A5 Timer Input Capture 2
16 PA4/ICAP1/IT1 I/O CT X X X Port A4 Timer Input Capture 1
17 PA3/EXTCLK I/O CT X X Port A3 Timer External Clock
PA2/SCL/ I²C serial clock,
18 I/O CT 25mA X T Port A2
ICCCLK ICC Clock
19 PA1/SDA/ICCDATA I/O CT 25mA X T Port A1 I²C serial data, ICC Data
20 PA0/MCO I/O CT X X Port A0 Main Clock Output
21 VSSA S Analog ground
22 USBDP I/O USB bidirectional data (data +)
23 USBDM I/O USB bidirectional data (data -)
24 USBVCC O USB power supply

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3 Register & memory map

As shown in Figure 7, the MCU is capable of ad- The highest address bytes contain the user reset
dressing 32 Kbytes of memories and I/O registers. and interrupt vectors.
The available memory locations consist of up to IMPORTANT: Memory locations noted “Re-
1024 bytes of RAM including 64 bytes of register served” must never be accessed. Accessing a re-
locations, and up to 32K bytes of user program served area can have unpredictable effects on the
memory in which the upper 32 bytes are reserved device.
for interrupt vectors. The RAM space includes up
to 128 bytes for the stack from 0100h to 017Fh.
Figure 7. Memory map
0040h
0000h Short Addressing
HW Registers
(See Table 5) RAM (192 bytes)
003Fh 00FFh
0040h 0100h
Stack
RAM (128 bytes)
(384 / 512 / 1024 bytes) 017Fh
0180h
01BF / 023F / 043Fh
01C0 / 0240 / 0440h 16-bit Addressing
Reserved RAM
01BF / 023F / 043Fh
7FFFh
8000h 8000h
Program Memory 32 Kbytes
(4 / 8 / 16 / 32 Kbytes)
FFDFh C000h
FFE0h 16 Kbytes
Interrupt & Reset Vectors
(See Table 4) E000h
FFFFh 8 Kbytes
F000h
4 Kbytes
FFDFh

Table 4. interrupt vector map

Vector address Description Masked by Remarks Exit from Halt mode
FFE0h-FFEDh Reserved Area
FFEEh-FFEFh USB Interrupt Vector I- bit Internal Interrupt No
FFF0h-FFF1h SCI Interrupt Vector I- bit Internal Interrupt No
FFF2h-FFF3h I²C Interrupt Vector I- bit Internal Interrupt No
FFF4h-FFF5h TIMER Interrupt Vector I- bit Internal Interrupt No
FFF6h-FFF7h IT1 to IT8 Interrupt Vector I- bit External Interrupt Yes
FFF8h-FFF9h USB End Suspend mode Interrupt Vector I- bit External Interrupts Yes
FFFAh-FFFBh Flash Start Programming Interrupt Vector I- bit Internal Interrupt Yes
FFFCh-FFFDh TRAP (software) Interrupt Vector None CPU Interrupt No
FFFEh-FFFFh RESET Vector None Yes

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 ST7263BDx ST7263BHx ST7263BKx ST7263BE

Table 5. Hardware register memory map

Address Block Register label Register name Reset status Remarks

0000h PADR Port A Data Register 00h R/W
Port A
0001h PADDR Port A Data Direction Register 00h R/W
0002h PBDR Port B Data Register 00h R/W
Port B
0003h PBDDR Port B Data Direction Register 00h R/W
0004h PCDR Port C Data Register 1111 x000b R/W
Port C
0005h PCDDR Port C Data Direction Register 1111 x000b R/W
0006h PDDR Port D Data Register 00h R/W
Port D
0007h PDDDR Port D Data Direction Register 00h R/W
0008h ITC ITIFRE Interrupt Register 00h R/W
0009h MISC MISCR Miscellaneous Register 00h R/W
000Ah ADCDR ADC Data Register 00h Read only
ADC
000Bh ADCCSR ADC control Status register 00h R/W
000Ch WDG WDGCR Watchdog Control Register 7Fh R/W
000Dh
to Reserved (4 bytes)
0010h
0011h TCR2 Timer Control Register 2 00h R/W
0012h TCR1 Timer Control Register 1 00h R/W
0013h TCSR Timer Control/Status Register 00h R/W
0014h TIC1HR Timer Input Capture High Register 1 xxh Read only
0015h TIC1LR Timer Input Capture Low Register 1 xxh Read only
0016h TOC1HR Timer Output Compare High Register 1 80h R/W
0017h TOC1LR Timer Output Compare Low Register 1 00h R/W
0018h TIM TCHR Timer Counter High Register FFh Read only
0019h TCLR Timer Counter Low Register FCh R/W
001Ah TACHR Timer Alternate Counter High Register FFh Read only
001Bh TACLR Timer Alternate Counter Low Register FCh R/W
001Ch TIC2HR Timer Input Capture High Register 2 xxh Read only
001Dh TIC2LR Timer Input Capture Low Register 2 xxh Read only
001Eh TOC2HR Timer Output Compare High Register 2 80h R/W
001Fh TOC2LR Timer Output Compare Low Register 2 00h R/W
0020h SCISR SCI Status Register C0h Read only
0021h SCIDR SCI Data Register xxh R/W
0022h SCI SCIBRR SCI Baud Rate Register 00h R/W
0023h SCICR1 SCI Control Register 1 x000 0000b R/W
0024h SCICR2 SCI Control Register 2 00h R/W

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Address Block Register label Register name Reset status Remarks

0025h USBPIDR USB PID Register x0h Read only
0026h USBDMAR USB DMA address Register xxh R/W
0027h USBIDR USB Interrupt/DMA Register x0h R/W
0028h USBISTR USB Interrupt Status Register 00h R/W
0029h USBIMR USB Interrupt Mask Register 00h R/W
002Ah USBCTLR USB Control Register 06h R/W
002Bh USB USBDADDR USB Device Address Register 00h R/W
002Ch USBEP0RA USB Endpoint 0 Register A 0000 xxxxb R/W
002Dh USBEP0RB USB Endpoint 0 Register B 80h R/W
002Eh USBEP1RA USB Endpoint 1 Register A 0000 xxxxb R/W
002Fh USBEP1RB USB Endpoint 1 Register B 0000 xxxxb R/W
0030h USBEP2RA USB Endpoint 2 Register A 0000 xxxxb R/W
0031h USBEP2RB USB Endpoint 2 Register B 0000 xxxxb R/W
0032h to
Reserved (5 bytes)
0036h
0032h
Reserved (5 bytes)
0036h
0037h Flash FCSR Flash Control /Status Register 00h R/W
0038h Reserved (1 byte)
0039h I2CDR I²C Data Register 00h R/W
003Ah Reserved -
003Bh I2COAR I²C (7 Bits) Slave Address Register 00h R/W
003Ch I²C I2CCCR I²C Clock Control Register 00h R/W
003Dh I2CSR2 I²C 2nd Status Register 00h Read only
003Eh I2CSR1 I²C 1st Status Register 00h Read only
003Fh I2CCR I²C Control Register 00h R/W

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4 Flash program memory

4.1 Introduction
The ST7 dual voltage High Density Flash be erased independently to avoid unnecessary
(HDFlash) is a non-volatile memory that can be erasing of the whole Flash memory when only a
electrically erased as a single block or by individu- partial erasing is required.
al sectors and programmed on a byte-by-byte ba- The first two sectors have a fixed size of 4 Kbytes
sis using an external VPP supply. (see Figure 8). They are mapped in the upper part
The HDFlash devices can be programmed and of the ST7 addressing space so the reset and in-
erased off-board (plugged in a programming tool) terrupt vectors are located in Sector 0 (F000h-
or on-board using ICP (in-circuit programming) or FFFFh).
IAP (in-application programming).
Table 6. Sectors available in Flash devices
The array matrix organisation allows each sector
to be erased and reprogrammed without affecting Flash size (bytes) Available sectors
other [Link] features
4K Sector 0
■ 3 Flash programming modes:
8K Sectors 0,1
– Insertion in a programming tool. In this mode,
all sectors including option bytes can be pro- > 8K Sectors 0,1, 2
grammed or erased.
– ICP (in-circuit programming). In this mode, all 4.2.1 Read-Out protection
sectors including option bytes can be pro-
grammed or erased without removing the de- Read-Out protection, when selected, provides a
vice from the application board. protection against Program Memory content ex-
– IAP (in-application programming) In this traction and against write access to Flash memo-
mode, all sectors except Sector 0, can be pro- ry. Even if no protection can be considered as to-
grammed or erased without removing the de-
vice from the application board and while the tally unbreakable, the feature provides a very high
application is running. level of protection for a general purpose microcon-
■ ICT (in-circuit testing) for downloading and troller.
executing user application test patterns in RAM In Flash devices, this protection is removed by re-
■ Read-Out protection programming the option. In this case, the entire
■ Register access security system (RASS) to
program memory is first automatically erased and
prevent accidental programming or erasing the device can be reprogrammed.
Read-Out protection selection depends on the de-
4.2 Structure vice type:
– In Flash devices it is enabled and removed
The Flash memory is organised in sectors and can through the FMP_R bit in the option byte.
be used for both code and data storage.
– In ROM devices it is enabled by mask option
Depending on the overall Flash memory size in the specified in the Option List.
microcontroller device, there are up to three user
sectors (see Table 6). Each of these sectors can

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Figure 8. Memory map and sector address

4K 8K 10K 16K 24K 32K 48K 60K FLASH

1000h MEMORY SIZE
3FFFh
7FFFh
9FFFh
SECTOR 2
BFFFh
D7FFh
2 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes 52 Kbytes
DFFFh
EFFFh
4 Kbytes SECTOR 1
FFFFh
4 Kbytes SECTOR 0

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Flash program memory (Cont’d)

4.3 ICC interface

ICC (in-circuit communication) needs a minimum – ICCDATA: ICC input/output serial data pin
of four and up to six pins to be connected to the – ICCSEL/VPP: programming voltage
programming tool (see Figure 9). These pins are: – OSC1(or OSCIN): main clock input for exter-
– RESET: device reset nal source (optional)
– VSS: device power supply ground – VDD: application board power supply (see Fig-
ure 9, Note 3)
– ICCCLK: ICC output serial clock pin
Figure 9. Typical ICC interface
PROGRAMMING TOOL
ICC CONNECTOR

ICC Cable
APPLICATION BOARD

(See Note 3) ICC CONNECTOR

OPTIONAL HE10 CONNECTOR TYPE
(See Note 4) 9 7 5 3 1

10 8 6 4 2
APPLICATION
RESET SOURCE
See Note 2

10kΩ

APPLICATION CL2 CL1

POWER SUPPLY See Note 1

APPLICATION
RESET

ICCCLK

ICCDATA
OSC1

ICCSEL/VPP
OSC2

VSS
VDD

I/O

ST7

Notes:
1. If the ICCCLK or ICCDATA pins are only used agement IC with open drain output and pull-up
as outputs in the application, no signal isolation is resistor > 1K, no additional components are need-
necessary. As soon as the Programming Tool is ed. In all cases the user must ensure that no exter-
plugged to the board, even if an ICC session is not nal reset is generated by the application during the
in progress, the ICCCLK and ICCDATA pins are ICC session.
not available for the application. If they are used as 3. The use of Pin 7 of the ICC connector depends
inputs by the application, isolation such as a serial on the Programming Tool architecture. This pin
resistor has to implemented in case another de- must be connected when using most ST Program-
vice forces the signal. Refer to the Programming ming Tools (it is used to monitor the application
Tool documentation for recommended resistor val- power supply). Please refer to the Programming
ues. Tool manual.
2. During the ICC session, the programming tool 4. Pin 9 has to be connected to the OSC1 or OS-
must control the RESET pin. This can lead to con- CIN pin of the ST7 when the clock is not available
flicts between the programming tool and the appli- in the application or if the selected clock option is
cation reset circuit if it drives more than 5mA at not programmed in the option byte. ST7 devices
high level (push pull output or pull-up resistor<1K). with multioscillator capability need to have OSC2
A schottky diode can be used to isolate the appli- grounded in this case.
cation RESET circuit in this case. When using a
classical RC network with R > 1K or a reset man-

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Flash program memory (Cont’d)

4.4 ICP (in-circuit programming) 4.6 Related documentation

To perform ICP the microcontroller must be For details on Flash programming and ICC proto-
switched to ICC (in-circuit communication) mode col, refer to the ST7 Flash Programming Refer-
by an external controller or programming tool. ence Manual and to the ST7 ICC Protocol Refer-
Depending on the ICP code downloaded in RAM, ence Manual.
Flash memory programming can be fully custom-
ized (number of bytes to program, program loca- 4.7 Register description
tions, or selection serial communication interface
for downloading). Flash Control/Status register (FCSR)
When using an STMicroelectronics or third-party Read/Write
programming tool that supports ICP and the spe-
Reset value: 0000 0000 (00h)
cific microcontroller device, the user needs only to
implement the ICP hardware interface on the ap-
7 0
plication board (see Figure 9). For more details on
the pin locations, refer to the device pinout de-
0 0 0 0 0 0 0 0
scription.

4.5 IAP (in-application programming) This register is reserved for use by programming
This mode uses a BootLoader program previously tool software. It controls the Flash programming
stored in Sector 0 by the user (in ICP mode or by and erasing operations.
plugging the device in a programming tool).
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (us-
er-defined strategy for entering programming
mode, choice of communications protocol used to
fetch the data to be stored, etc.). For example, it is
possible to download code from the SPI, SCI or
other type of serial interface and program it in the
Flash. IAP mode can be used to program any of
the Flash sectors except Sector 0, which is write/
erase protected to allow recovery in case errors
occur during the programming operation.

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5 Central processing unit

5.1 Introduction Accumulator (A)

This CPU has a full 8-bit architecture and contains The Accumulator is an 8-bit general purpose reg-
six internal registers allowing efficient 8-bit data ister used to hold operands and the results of the
manipulation. arithmetic and logic calculations and to manipulate
data.
5.2 Features Index registers (X and Y)
In indexed addressing modes, these 8-bit registers
■ 63 basic instructions are used to create either effective addresses or
■ Fast 8-bit by 8-bit multiply temporary storage areas for data manipulation.
■ 17 main addressing modes (The cross-assembler generates a precede in-
■ Two 8-bit index registers struction (PRE) to indicate that the following in-
struction refers to the Y register.)
■ 16-bit stack pointer
The Y register is not affected by the interrupt auto-
■ Low power modes matic procedures (not pushed to and popped from
■ Maskable hardware interrupts the stack).
■ Non-maskable software interrupt Program Counter (PC)
The program counter is a 16-bit register containing
5.3 CPU registers the address of the next instruction to be executed
The six CPU registers shown in Figure 10 are not by the CPU. It is made of two 8-bit registers PCL
present in the memory mapping and are accessed (Program Counter Low which is the LSB) and PCH
by specific instructions. (Program Counter High which is the MSB).

Figure 10. CPU registers

7 0
ACCUMULATOR
RESET VALUE = XXh
7 0
X INDEX REGISTER
RESET VALUE = XXh
7 0
Y INDEX REGISTER
RESET VALUE = XXh

15 PCH 8 7 PCL 0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7 0
1 1 1 H I N Z C CONDITION CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X

15 8 7 0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined value

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CPU registers (cont’d)

Condition Code register (CC) because the I bit is set by hardware at the start of
Read/Write the routine and reset by the IRET instruction at the
end of the routine. If the I bit is cleared by software
Reset value: 111x1xxx in the interrupt routine, pending interrupts are
7 0 serviced regardless of the priority level of the cur-
rent interrupt routine.
1 1 1 H I N Z C

Bit 2 = N Negative
The 8-bit Condition Code register contains the in- This bit is set and cleared by hardware. It is repre-
terrupt mask and four flags representative of the sentative of the result sign of the last arithmetic,
result of the instruction just executed. This register logical or data manipulation. It is a copy of the 7th
can also be handled by the PUSH and POP in- bit of the result.
structions. 0: The result of the last operation is positive or null.
These bits can be individually tested and/or con- 1: The result of the last operation is negative
trolled by specific instructions. (that is, the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instruc-
Bit 4 = H Half carry tions.
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or Bit 1 = Z Zero
ADC instruction. It is reset by hardware during the
same instructions. This bit is set and cleared by hardware. This bit in-
0: No half carry has occurred. dicates that the result of the last arithmetic, logical
1: A half carry has occurred. or data manipulation is zero.
0: The result of the last operation is different from
This bit is tested using the JRH or JRNH instruc- zero.
tion. The H bit is useful in BCD arithmetic subrou- 1: The result of the last operation is zero.
tines.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 3 = I Interrupt mask
This bit is set by hardware when entering in inter-
rupt or by software to disable all interrupts except Bit 0 = C Carry/borrow
the TRAP software interrupt. This bit is cleared by This bit is set and cleared by hardware and soft-
software. ware. It indicates an overflow or an underflow has
0: Interrupts are enabled. occurred during the last arithmetic operation.
1: Interrupts are disabled. 0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is controlled by the RIM, SIM and IRET in-
structions and is tested by the JRM and JRNM in- This bit is driven by the SCF and RCF instructions
structions. and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
Note: Interrupts requested while I is set are rotate instructions.
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptible

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6 CPU registers (Cont’d)

Stack Pointer (SP) The least significant byte of the Stack Pointer
Read/Write (called S) can be directly accessed by a LD in-
struction.
Reset value: 017Fh
Note: When the lower limit is exceeded, the Stack
15 8 Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
0 0 0 0 0 0 0 1 stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
7 0 flow.
The stack is used to save the return address dur-
0 SP6 SP5 SP4 SP3 SP2 SP1 SP0 ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
The Stack Pointer is a 16-bit register which is al- at the first location pointed to by the SP. Then the
ways pointing to the next free location in the stack. other registers are stored in the next locations as
It is then decremented after data has been pushed shown in Figure 11.
onto the stack and incremented before data is – When an interrupt is received, the SP is decre-
popped from the stack (see Figure 11). mented and the context is pushed on the stack.
Since the stack is 128 bytes deep, the 9 most sig- – On return from interrupt, the SP is incremented
nificant bits are forced by hardware. Following an and the context is popped from the stack.
MCU Reset, or after a Reset Stack Pointer instruc-
tion (RSP), the Stack Pointer contains its reset val- A subroutine call occupies two locations and an in-
ue (the SP6 to SP0 bits are set) which is the stack terrupt five locations in the stack area.
higher address.

Figure 11. Stack manipulation example

CALL Interrupt PUSH Y POP Y IRET RET
Subroutine Event or RSP

@ 0100h

SP
SP SP
Y
CC CC CC
A A A
X X X
PCH PCH PCH
SP SP
PCL PCL PCL
PCH PCH PCH PCH PCH
SP
@ 017Fh PCL PCL PCL PCL PCL

Stack Higher Address = 017Fh

Stack Lower Address = 0100h

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7 Reset and clock management

7.1 Reset
The Reset procedure is used to provide an orderly 7.1.3 External reset
software start-up or to exit low power modes. The external reset is an active low input signal ap-
Three reset modes are provided: a low voltage plied to the RESET pin of the MCU.
(LVD) reset, a watchdog reset and an external re- As shown in Figure 15, the RESET signal must
set at the RESET pin. stay low for a minimum of one and a half CPU
A reset causes the reset vector to be fetched from clock cycles.
addresses FFFEh and FFFFh in order to be loaded An internal Schmitt trigger at the RESET pin is pro-
into the PC and with program execution starting vided to improve noise immunity.
from this point. Figure 12. Low voltage detector functional diagram
An internal circuitry provides a 4096 CPU clock cy-
cle delay from the time that the oscillator becomes RESET
active.
VDD LOW VOLTAGE
7.1.1 Low voltage detector (LVD) DETECTOR
INTERNAL
Low voltage reset circuitry generates a reset when RESET
VDD is: FROM
■ below VIT+ when VDD is rising, WATCHDOG
RESET
■ below VIT- when VDD is falling.

Figure 13. Low voltage reset signal output

During low voltage reset, the RESET pin is held low,
thus permitting the MCU to reset other devices.
VIT+
It is recommended to make sure that the VDD sup- VIT-
ply voltage rises monotonously when the device is
exiting from Reset, to ensure the application func-
VDD
tions properly.

7.1.2 Watchdog reset RESET

When a watchdog reset occurs, the RESET pin is
pulled low permitting the MCU to reset other devic- Note: Hysteresis (VIT+-VIT-) = Vhys
es in the same way as the low voltage reset (Fig-
ure 12).
Figure 14. Temporization timing diagram after an internal Reset

VIT+
VDD

Temporization (4096 CPU clock cycles)

Addresses $FFFE

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Reset (Cont’d)
Figure 15. Reset timing diagram

tDDR

VDD

OSCIN

tOXOV

fCPU

PC FFFE FFFF

RESET 4096 CPU

CLOCK
CYCLES
DELAY
WATCHDOG RESET

Note: Refer to Section 14, "Electrical characteristics" for values of tDDR, tOXOV, VIT+, VIT- and Vhys

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7.2 Clock system

7.2.1 General description source should be used instead of tOXOV (see Sec-
The MCU accepts either a crystal or ceramic reso- tion 6.5 CONTROL TIMING).
nator, or an external clock signal to drive the inter- Figure 16. External clock source connections
nal oscillator. The internal clock (fCPU) is derived
from the external oscillator frequency (fOSC),
which is divided by 3 (and by 2 or 4 for USB, de-
pending on the external clock used). The internal
clock is further divided by 2 by setting the SMS bit
in the Miscellaneous Register.
Using the OSC24/12 bit in the option byte, a 12 OSCIN OSCOUT
MHz or a 24 MHz external clock can be used to
provide an internal frequency of either 2, 4 or 8 NC
MHz while maintaining a 6 MHz for the USB (refer
to Figure 18). EXTERNAL
CLOCK
The internal clock signal (fCPU) is also routed to
the on-chip peripherals. The CPU clock signal
consists of a square wave with a duty cycle of Figure 17. Crystal/ceramic resonator
50%.
The internal oscillator is designed to operate with
an AT-cut parallel resonant quartz or ceramic res-
onator in the frequency range specified for fosc.
The circuit shown in Figure 17 is recommended
when using a crystal, and Table 7, "Recommend- OSCIN OSCOUT
RP
ed values for 24 MHz crystal resonator" lists the
recommended capacitance. The crystal and asso-
ciated components should be mounted as close as
possible to the input pins in order to minimize out- COSCIN COSCOUT
put distortion and start-up stabilisation time.
Table 7. Recommended values for 24 MHz
crystal resonator
Figure 18. Clock block diagram
RSMAX 20 Ω 25 Ω 70 Ω
COSCIN 56pF 47pF 22pF 8, 4 or 2 MHz
COSCOUT 0 CPU and
56pF 47pF 22pF
peripherals)
RP 1-10 MΩ 1-10 MΩ 1-10 MΩ
%2
%3 1
Note: RSMAX is the equivalent serial resistor of the
crystal (see crystal specification). SMS
7.2.2 External clock
An external clock may be applied to the OSCIN in-
1 6 MHz (USB)
put with the OSCOUT pin not connected, as %2
24 or %2
shown on Figure 16. The tOXOV specifications do
not apply when using an external clock input. The 12 MHz 0
%2
equivalent specification of the external clock Crystal
OSC24/12

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8 Interrupts
The ST7 core may be interrupted by one of two dif-
ferent methods: maskable hardware interrupts as Interrupts and low power mode
listed in Table 8, "Interrupt mapping" and a non-
maskable software interrupt (TRAP). The Interrupt All interrupts allow the processor to leave the Wait
processing flowchart is shown in Figure 19. low power mode. Only external and specific men-
tioned interrupts allow the processor to leave the
Halt low power mode (refer to the “Exit from Halt“
The maskable interrupts must be enabled clearing column in Table 8, "Interrupt mapping").
the I bit in order to be serviced. However, disabled
interrupts may be latched and processed when
they are enabled (see external interrupts subsec- External interrupts
tion). The pins ITi/PAk and ITj/PBk (i=1,2; j= 5,6; k=4,5)
When an interrupt has to be serviced: can generate an interrupt when a rising edge oc-
– Normal processing is suspended at the end of curs on this pin. Conversely, the ITl/PAn and ITm/
the current instruction execution. PBn pins (l=3,4; m= 7,8; n=6,7) can generate an
interrupt when a falling edge occurs on this pin.
– The PC, X, A and CC registers are saved onto
the stack. Interrupt generation will occur if it is enabled with
the ITiE bit (i=1 to 8) in the ITRFRE register and if
– The I bit of the CC register is set to prevent addi- the I bit of the CCR is reset.
tional interrupts.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of Peripheral interrupts
the interrupt service routine is fetched (refer to Different peripheral interrupt flags in the status
Table 8, "Interrupt mapping" for vector address- register are able to cause an interrupt when they
es). are active if both:
The interrupt service routine should finish with the – The I bit of the CC register is cleared.
IRET instruction which causes the contents of the
– The corresponding enable bit is set in the control
saved registers to be recovered from the stack.
register.
Note: As a consequence of the IRET instruction,
If any of these two conditions is false, the interrupt
the I bit will be cleared and the main program will is latched and thus remains pending.
resume.
Clearing an interrupt request is done by one of the
two following operations:
Priority management – Writing “0” to the corresponding bit in the status
By default, a servicing interrupt cannot be inter- register.
rupted because the I bit is set by hardware enter-
– Accessing the status register while the flag is set
ing in interrupt routine.
followed by a read or write of an associated reg-
In the case several interrupts are simultaneously ister.
pending, a hardware priority defines which one will
Notes:
be serviced first (see Table 8, "Interrupt map-
ping"). 1. The clearing sequence resets the internal latch.
A pending interrupt (i.e. waiting to be enabled) will
therefore be lost if the clear sequence is executed.
Non-maskable software interrupts
2. All interrupts allow the processor to leave the
This interrupt is entered when the TRAP instruc- Wait low power mode.
tion is executed regardless of the state of the I bit.
3. Exit from Halt mode may only be triggered by an
It will be serviced according to the flowchart on
External Interrupt on one of the ITi ports (PA4-PA7
Figure 19.
and PB4-PB7), an end suspend mode Interrupt
coming from USB peripheral, or a reset.

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Interrupts (Cont’d)
Figure 19. Interrupt processing flowchart

FROM RESET

N
BIT I SET

Y N
INTERRUPT

FETCH NEXT INSTRUCTION Y

N
IRET
STACK PC, X, A, CC
Y SET I BIT
LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION

RESTORE PC, X, A, CC FROM STACK

THIS CLEARS I BIT BY DEFAULT

Table 8. Interrupt mapping

Exit Vector
Source Register Priority
N° Description from
block label order address
Halt
RESET Reset Highest yes FFFEh-FFFFh
N/A
TRAP Software Interrupt Priority no FFFCh-FFFDh
FLASH Flash Start Programming Interrupt yes FFFAh-FFFBh
USB End Suspend mode ISTR FFF8h-FFF9h
yes
1 ITi External Interrupts ITRFRE FFF6h-FFF7h
2 TIMER Timer Peripheral Interrupts TIMSR FFF4h-FFF5h
I²CSR1
3 I²C I²C Peripheral Interrupts FFF2h-FFF3h
I²CSR2 Lowest no
4 SCI SCI Peripheral Interrupts SCISR Priority FFF0h-FFF1h
5 USB USB Peripheral Interrupts ISTR FFEEh-FFEFh

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Interrupts (Cont’d)

8.1 Interrupt register

Interrupt register (ITRFRE)
Address: 0008h — Read/Write If an ITiE bit is set, the corresponding interrupt is
Reset value: 0000 0000 (00h) generated when
7 0 – a rising edge occurs on the pin PA4/IT1 or PA5/
IT2 or PB4/IT5 or PB5/IT6
IT8E IT7E IT6E IT5E IT4E IT3E IT2E IT1E or
– a falling edge occurs on the pin PA6/IT3 or PA7/
Bit 7:0 = ITiE (i=1 to 8). Interrupt Enable Control IT4 or PB6/IT7 or PB7/IT8
Bits.
No interrupt is generated elsewhere.
Note: Analog input must be disabled for interrupts
coming from port B.

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9 Power saving modes

9.1 Introduction
To give a large measure of flexibility to the applica- Figure 20. Halt mode flowchart
tion in terms of power consumption, two main pow-
er saving modes are implemented in the ST7.
After a RESET, the normal operating mode is se- HALT INSTRUCTION
lected by default (Run mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided by 3 (fCPU). OSCILLATOR OFF
PERIPH. CLOCK OFF
From Run mode, the different power saving
modes may be selected by setting the relevant CPU CLOCK OFF
register bits or by calling the specific ST7 software I-BIT CLEARED
instruction whose action depends on the oscillator
status.

9.2 Halt mode N

The MCU consumes the least amount of power in RESET
Halt mode. The Halt mode is entered by executing N
the HALT instruction. The internal oscillator is then
turned off, causing all internal processing to be EXTERNAL Y
stopped, including the operation of the on-chip pe- INTERRUPT*
ripherals.
When entering Halt mode, the I bit in the Condition Y
Code Register is cleared. Thus, all external inter- OSCILLATOR ON
rupts (ITi or USB end suspend mode) are allowed PERIPH. CLOCK ON
and if an interrupt occurs, the CPU clock becomes
CPU CLOCK ON
active.
I-BIT SET
The MCU can exit Halt mode on reception of either
an external interrupt on ITi, an end suspend mode
interrupt coming from USB peripheral, or a reset.
The oscillator is then turned on and a stabilization 4096 CPU CLOCK
time is provided before releasing CPU operation. CYCLES DELAY
The stabilization time is 4096 CPU clock cycles.
After the start up delay, the CPU continues opera-
tion by servicing the interrupt which wakes it up or
by fetching the reset vector if a reset wakes it up.
FETCH RESET VECTOR
OR SERVICE INTERRUPT

Note: Before servicing an interrupt, the CC register is

pushed on the stack. The I-Bit is set during the inter-
rupt routine and cleared when the CC register is
popped.

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Power saving modes (Cont’d)

9.3 Slow mode

In Slow mode, the oscillator frequency can be di- Figure 21. Wait mode flowchart
vided by 2 as selected by the SMS bit in the Mis-
cellaneous Register. The CPU and peripherals are
clocked at this lower frequency. Slow mode is WFI INSTRUCTION
used to reduce power consumption, and enables
the user to adapt the clock frequency to the avail-
able supply voltage.
OSCILLATOR ON
9.4 Wait mode PERIPH. CLOCK ON
Wait mode places the MCU in a low power con- CPU CLOCK OFF
sumption mode by stopping the CPU. I-BIT CLEARED
This power saving mode is selected by calling the
“WFI” ST7 software instruction.
All peripherals remain active. During Wait mode,
the I bit of the CC register is forced to 0 to enable
all interrupts. All other registers and memory re-
main unchanged. The MCU remains in Wait mode N
until an interrupt or Reset occurs, whereupon the RESET
Program Counter branches to the starting address
N
of the interrupt or Reset service routine.
The MCU will remain in Wait mode until a Reset or Y
an Interrupt occurs, causing it to wake up. INTERRUPT

Refer to Figure 21.

Related documentation
Y OSCILLATOR ON
AN 980: ST7 Keypad Decoding Techniques, Im-
plementing Wake-Up on Keystroke PERIPH. CLOCK ON
AN1014: How to Minimize the ST7 Power Con- CPU CLOCK ON
sumption I-BIT SET
AN1605: Using an active RC to wakeup the
ST7LITE0 from power saving mode IF RESET
4096 CPU CLOCK
CYCLES DELAY

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note: Before servicing an interrupt, the CC register is

pushed on the stack. The I-Bit is set during the inter-
rupt routine and cleared when the CC register is
popped.

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10 I/O ports

10.1 Introduction
The I/O ports offer different functional modes: tivity is given independently according to the de-
– Transfer of data through digital inputs and out- scription mentioned in the ITRFRE interrupt regis-
puts and for specific pins ter.
– Analog signal input (ADC) Each pin can independently generate an Interrupt
request.
– Alternate signal input/output for the on-chip pe-
ripherals Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see Interrupts sec-
– External interrupt generation tion). If more than one input pin is selected simul-
An I/O port consists of up to 8 pins. Each pin can taneously as an interrupt source, this is logically
be programmed independently as a digital input ORed. For this reason if one of the interrupt pins is
(with or without interrupt generation) or a digital tied low, the other ones are masked.
output. Output mode
The pin is configured in output mode by setting the
10.2 Functional description corresponding DDR register bit (see Table 7).
Each port is associated to 2 main registers: In this mode, writing “0” or “1” to the DR register
– Data Register (DR) applies this digital value to the I/O pin through the
latch. Therefore, the previously saved value is re-
– Data Direction Register (DDR) stored when the DR register is read.
Each I/O pin may be programmed using the corre- Note: The interrupt function is disabled in this
sponding register bits in DDR register: bit X corre- mode.
sponding to pin X of the port. The same corre-
spondence is used for the DR register.
Digital alternate function
Table 9. I/O pin functions
When an on-chip peripheral is configured to use a
DDR MODE
pin, the alternate function is automatically select-
ed. This alternate function takes priority over
0 Input standard I/O programming. When the signal is
1 Output coming from an on-chip peripheral, the I/O pin is
automatically configured in output mode (push-pull
or open drain according to the peripheral).
Input modes
When the signal is going to an on-chip peripheral,
The input configuration is selected by clearing the the I/O pin has to be configured in input mode. In
corresponding DDR register bit. this case, the pin’s state is also digitally readable
In this case, reading the DR register returns the by addressing the DR register.
digital value applied to the external I/O pin. Notes:
Note 1: All the inputs are triggered by a Schmitt 1. Input pull-up configuration can cause an unex-
trigger. pected value at the input of the alternate peripher-
Note 2: When switching from input mode to output al input.
mode, the DR register should be written first to 2. When the on-chip peripheral uses a pin as input
output the correct value as soon as the port is con- and output, this pin must be configured as an input
figured as an output. (DDR = 0).
Interrupt function Warning: The alternate function must not be acti-
vated as long as the pin is configured as an input
When an I/O is configured as an Input with Inter-
rupt, an event on this I/O can generate an external with interrupt in order to avoid generating spurious
interrupts.
Interrupt request to the CPU. The interrupt sensi-

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I/O ports (Cont’d)

Analog alternate function have clocking pins located close to a selected an-
When the pin is used as an ADC input the I/O must alog pin.
be configured as a floating input. The analog mul- Warning: The analog input voltage level must be
tiplexer (controlled by the ADC registers) switches within the limits stated in the Absolute Maximum
the analog voltage present on the selected pin to Ratings.
the common analog rail which is connected to the
ADC input. 10.3 I/O port implementation
It is recommended not to change the voltage level
or loading on any port pin while conversion is in The hardware implementation on each I/O port de-
progress. Furthermore it is recommended not to pends on the settings in the DDR register and spe-
cific feature of the I/O port such as ADC Input or
true open drain.

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I/O ports (Cont’d)

10.3.1 Port A
Table 10. Port A0, A3, A4, A5, A6, A7 description

I/O Alternate function

PORT A
Input1 Output Signal Condition
PA0 with pull-up push-pull MCO (Main Clock Output) MCO = 1 (MISCR)
CC1 =1
PA3 with pull-up push-pull Timer EXTCLK
CC0 = 1 (Timer CR2)
Timer ICAP1
PA4 with pull-up
push-pull IT1 Schmitt triggered input IT1E = 1 (ITIFRE)
Timer ICAP2
PA5 with pull-up
push-pull IT2 Schmitt triggered input IT2E = 1 (ITIFRE)
Timer OCMP1 OC1E = 1
PA62 with pull-up
push-pull IT3 Schmitt triggered input IT3E = 1 (ITIFRE)
Timer OCMP2 OC2E = 1
PA7 with pull-up
push-pull IT4 Schmitt triggered input IT4E = 1 (ITIFRE)
1
Reset State
2
Not available on SO24

Figure 22. PA0, PA3, PA4, PA5, PA6, PA7 and PD[7:4] configuration

ALTERNATE ENABLE
ALTERNATE 1 VDD
OUTPUT

0 P-BUFFER

DR VDD
PULL-UP
LATCH
DATA BUS

ALTERNATE ENABLE
DDR
LATCH PAD

DDR SEL

N-BUFFER

1 DIODES
DR SEL
ALTERNATE ENABLE
VSS

ALTERNATE INPUT 0
CMOS SCHMITT TRIGGER

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I/O ports (Cont’d)

Table 11. PA1, PA2 description

I/O Alternate function

PORT A
Input1 Output Signal Condition
PA1 without pull-up Very High Current open drain SDA (I²C data) I²C enable
PA2 without pull-up Very High Current open drain SCL (I²C clock) I²C enable
1
Reset State

Figure 23. PA1, PA2 configuration

ALTERNATE ENABLE
ALTERNATE 1
OUTPUT
0

DR
LATCH

DDR
LATCH
DATA BUS

PAD

DDR SEL

N-BUFFER

DR SEL 1
ALTERNATE ENABLE

0 VSS
CMOS SCHMITT TRIGGER

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I/O ports (Cont’d)

10.3.2 Port B
Table 12. Port B description
PORT B I/O Alternate function

Input1 Output Signal Condition

PB0 without pull-up push-pull Analog input (ADC) CH[3:0] = 000 (ADCCSR)

Analog input (ADC) CH[3:0] = 001 (ADCCSR)

PB1 without pull-up push-pull USBOE (USB output ena- USBOE =1
ble)2 (MISCR)
PB2 without pull-up push-pull Analog input (ADC) CH[3:0]= 010 (ADCCSR)

PB3 without pull-up push-pull Analog input (ADC) CH[3:0]= 011 (ADCCSR)

Analog input (ADC) CH[3:0]= 100 (ADCCSR)

PB4 without pull-up push-pull
IT5 Schmitt triggered input IT4E = 1 (ITIFRE)

Analog input (ADC) CH[3:0]= 101 (ADCCSR)

PB5 without pull-up push-pull
IT6 Schmitt triggered input IT5E = 1 (ITIFRE)

Analog input (ADC) CH[3:0]= 110 (ADCCSR)

PB6 without pull-up push-pull
IT7 Schmitt triggered input IT6E = 1 (ITIFRE)

Analog input (ADC) CH[3:0]= 111 (ADCCSR)

PB7 without pull-up push-pull
IT8 Schmitt triggered input IT7E = 1 (ITIFRE)
1Reset State
2
On SO24 only

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Figure 24. Port B and D[3:0] configuration

ALTERNATE ENABLE
ALTERNATE 1 VDD
OUTPUT
0
VDD
DR P-BUFFER
LATCH
ALTERNATE ENABLE
DDR
PAD
LATCH
COMMON ANALOG RAIL

ANALOG ENABLE
DATA BUS

(ADC)

DDR SEL ANALOG

SWITCH DIODES
N-BUFFER

1
DR SEL
ALTERNATE ENABLE

DIGITAL ENABLE
0 VSS

ALTERNATE INPUT

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I/O ports (Cont’d)

10.3.3 Port C
Table 13. Port C description

I/O Alternate function

PORT C
1
Input Output Signal Condition

PC0 with pull-up push-pull RDI (SCI input)

PC1 with pull-up push-pull TDO (SCI output) SCI enable

USBOE (USB output ena- USBOE =1

PC22 with pull-up push-pull
ble) (MISCR)
1
Reset State
2
Not available on SO24

Figure 25. Port C configuration

ALTERNATE ENABLE
ALTERNATE 1 VDD
OUTPUT

0
P-BUFFER

DR VDD
PULL-UP
LATCH
ALTERNATE ENABLE
DATA BUS

DDR
LATCH PAD

DDR SEL

N-BUFFER

DR SEL 1 DIODES
ALTERNATE ENABLE

0 VSS
ALTERNATE INPUT

CMOS SCHMITT TRIGGER

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10.3.4 Port D
Table 14. Port D description

I/O Alternate function

PORT D
Input* Output Signal Condition
CH[3:0] = 1000 (ADCC-
PD0 without pull-up push-pull Analog input (ADC)
SR)
CH[3:0] = 1001 (ADCC-
PD1 without pull-up push-pull Analog input (ADC)
SR)
CH[3:0] = 1010 (ADCC-
PD2 without pull-up push-pull Analog input (ADC)
SR)
CH[3:0] = 1011 (ADCC-
PD3 without pull-up push-pull Analog input (ADC)
SR)
PD4 with pull-up push-pull

PD5 with pull-up push-pull

PD6 with pull-up push-pull

PD7 with pull-up push-pull

*Reset State

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I/O ports (Cont’d)

10.3.5 Register description Data Direction Register (PxDDR)
Data registers (PxDR) Port A Data Direction Register (PADDR): 0001h
Port A Data Register (PADR): 0000h Port B Data Direction Register (PBDDR): 0003h
Port B Data Register (PBDR): 0002h Port C Data Direction Register (PCDDR): 0005h
Port C Data Register (PCDR): 0004h Port D Data Direction Register (PDDDR): 0007h
Port D Data Register (PDDR): 0006h Read/Write
Read/Write Reset value Port A: 0000 0000 (00h)
Reset value Port A: 0000 0000 (00h) Reset value Port B: 0000 0000 (00h)
Reset value Port B: 0000 0000 (00h) Reset value Port C: 1111 x000 (FXh)
Reset value Port C: 1111 x000 (FXh) Reset value Port D: 0000 0000 (00h)
Reset value Port D: 0000 0000 (00h) Note: For Port C, unused bits (7-3) are not acces-
Note: For Port C, unused bits (7-3) are not acces- sible
sible.
7 0
7 0
DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0
D7 D6 D5 D4 D3 D2 D1 D0

Bit 7:0 = DD[7:0] Data Direction Register 8 bits.

Bit 7:0 = D[7:0] Data Register 8 bits. The DDR register gives the input/output direction
The DR register has a specific behaviour accord- configuration of the pins. Each bit is set and
ing to the selected input/output configuration. Writ- cleared by software.
ing the DR register is always taken into account 0: Input mode
even if the pin is configured as an input. Reading 1: Output mode
the DR register returns either the DR register latch
content (pin configured as output) or the digital val-
ue applied to the I/O pin (pin configured as input).
Note: When using open-drain I/Os in output con-
figuration, the value read in DR is the digital value
applied to the I/Opin.

Table 15. I/O ports register map

Address Register
7 6 5 4 3 2 1 0
(Hex.) label
00 PADR MSB LSB
01 PADDR MSB LSB
02 PBDR MSB LSB
03 PBDDR MSB LSB
04 PCDR MSB LSB
05 PCDDR MSB LSB
06 PDDR MSB LSB
07 PDDDR MSB LSB

Related documentation
AN 970: SPI communication between ST7 and EEPROM
AN1045: S/W implementation of I2C bus master
AN1048: Software LCD driver

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11 Miscellaneous register
Address: 0009h — Read/Write 1: Divide-by-2 enabled and CPU clock frequency is
Reset value: 0000 0000 (00h) halved.
7 0 Bit 1 = USBOE USB enable.
If this bit is set, the port PC2 (PB1 on SO24) out-
- - - - - SMS USBOE MCO puts the USB output enable signal (at “1” when the
ST7 USB is transmitting data).
Bit 7:3 = Reserved Unused bits 7-4 are set.

Bit 2 = SMS Slow Mode Select. Bit 0 = MCO Main Clock Out selection
This bit is set by software and only cleared by hard- This bit enables the MCO alternate function on the
ware after a reset. If this bit is set, it enables the use PA0 I/O port. It is set and cleared by software.
of an internal divide-by-2 clock divider (refer to Fig- 0: MCO alternate function disabled (I/O pin free for
ure 18 on page 26). The SMS bit has no effect on general-purpose I/O)
the USB frequency. 1: MCO alternate function enabled (fCPU on I/O
port)
0: Divide-by-2 disabled and CPU clock frequency
is standard

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12 On-chip peripherals

12.1 Watchdog timer (WDG)

12.1.1 Introduction cles, and the length of the timeout period can be
The Watchdog timer is used to detect the occur- programmed by the user in 64 increments.
rence of a software fault, usually generated by ex- If the watchdog is activated (the WDGA bit is set)
ternal interference or by unforeseen logical condi- and when the 7-bit timer (bits T6:T0) rolls over
tions, which causes the application program to from 40h to 3Fh (T6 becomes cleared), it initiates
abandon its normal sequence. The Watchdog cir- a reset cycle pulling low the reset pin for typically
cuit generates an MCU reset on expiry of a pro- 30µs.
grammed time period, unless the program refresh- The application program must write in the CR reg-
es the counter’s contents before the T6 bit be- ister at regular intervals during normal operation to
comes cleared. prevent an MCU reset. This downcounter is free-
12.1.2 Main features running: it counts down even if the watchdog is
■ Programmable free-running counter (64 disabled. The value to be stored in the CR register
increments of 49,152 CPU cycles) must be between FFh and C0h (see Table 16, ".
Watchdog timing (fCPU = 8 MHz)"):
■ Programmable reset

■ Reset (if watchdog activated) when the T6 bit

– The WDGA bit is set (watchdog enabled)
reaches zero – The T6 bit is set to prevent generating an imme-
■ Optional reset on HALT instruction diate reset
(configurable by option byte) – The T5:T0 bits contain the number of increments
■ Hardware Watchdog selectable by option byte. which represents the time delay before the
watchdog produces a reset.
12.1.3 Functional description
The counter value stored in the CR register (bits
T6:T0), is decremented every 49,152 machine cy-
Figure 26. Watchdog block diagram

RESET

WATCHDOG CONTROL REGISTER (CR)

WDGA T6 T5 T4 T3 T2 T1 T0

7-BIT DOWNCOUNTER

fCPU CLOCK DIVIDER

÷49152

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Watchdog timer (Cont’d)

Table 16. Watchdog timing (fCPU = 8 MHz) In this case, the HALT instruction stops the oscilla-
tor. When the oscillator is stopped, the WDG stops
CR register WDG timeout period counting and is no longer able to generate a reset
initial value (ms) until the microcontroller receives an external inter-
Max FFh 393.216 rupt or a reset.
Min C0h 6.144 If an external interrupt is received, the WDG re-
starts counting after 4096 CPU clocks. If a reset is
Notes: Following a reset, the watchdog is disa-
generated, the WDG is disabled (reset state).
bled. Once activated it cannot be disabled, except
by a reset. Recommendations
The T6 bit can be used to generate a software re- – Make sure that an external event is available to
set (the WDGA bit is set and the T6 bit is cleared). wake up the microcontroller from Halt mode.
– Before executing the HALT instruction, refresh
the WDG counter, to avoid an unexpected WDG
12.1.4 Software Watchdog option
reset immediately after waking up the microcon-
If Software Watchdog is selected by option byte, troller.
the watchdog is disabled following a reset. Once
– When using an external interrupt to wake up the
activated it cannot be disabled, except by a reset.
microcontroller, reinitialize the corresponding I/O
The T6 bit can be used to generate a software re- as “Input Pull-up with Interrupt” before executing
set (the WDGA bit is set and the T6 bit is cleared). the HALT instruction. The main reason for this is
that the I/O may be wrongly configured due to ex-
ternal interference or by an unforeseen logical
12.1.5 Hardware Watchdog option condition.
If Hardware Watchdog is selected by option byte, – For the same reason, reinitialize the level sensi-
the watchdog is always active and the WDGA bit in tiveness of each external interrupt as a precau-
the CR is not used. tionary measure.
– The opcode for the HALT instruction is 0x8E. To
12.1.6 Low power modes avoid an unexpected HALT instruction due to a
WAIT instruction program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
No effect on Watchdog. ry. For example, avoid defining a constant in
HALT instruction ROM with the value 0x8E.
If the Watchdog reset on Halt option is selected by – As the HALT instruction clears the I bit in the CC
option byte, a HALT instruction causes an immedi- register to allow interrupts, the user may choose
ate reset generation if the Watchdog is activated to clear all pending interrupt bits before execut-
(WDGA bit is set). ing the HALT instruction. This avoids entering
other peripheral interrupt routines after executing
the external interrupt routine corresponding to
[Link] Using Halt mode with the WDG the wake-up event (reset or external interrupt).
(option)
If the Watchdog reset on Halt option is not select-
12.1.7 Interrupts
ed by option byte, the Halt mode can be used
when the watchdog is enabled. None.

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Watchdog timer (Cont’d)

12.1.8 Register description hardware after a reset. When WDGA = 1, the
Control Register (CR) watchdog can generate a reset.
0: Watchdog disabled
Read/Write 1: Watchdog enabled
Reset value: 0111 1111 (7Fh)
7 0
Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
WDGA T6 T5 T4 T3 T2 T1 T0 is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).

Bit 7 = WDGA Activation bit.

This bit is set by software and only cleared by
Table 17. Watchdog timer register map and reset values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

WDGCR WDGA T6 T5 T4 T3 T2 T1 T0
0Ch
Reset value 0 1 1 1 1 1 1 1

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12.2 16-bit timer

12.2.1 Introduction When reading an input signal on a non-bonded
The timer consists of a 16-bit free-running counter pin, the value will always be ‘1’.
driven by a programmable prescaler. 12.2.3 Functional description
It may be used for a variety of purposes, including [Link] Counter
pulse length measurement of up to two input sig- The main block of the Programmable Timer is a
nals (input capture) or generation of up to two out- 16-bit free running upcounter and its associated
put waveforms (output compare and PWM). 16-bit registers. The 16-bit registers are made up
Pulse lengths and waveform periods can be mod- of two 8-bit registers called high and low.
ulated from a few microseconds to several milli- Counter Register (CR):
seconds using the timer prescaler and the CPU
clock prescaler. – Counter High Register (CHR) is the most sig-
nificant byte (MS byte).
Some ST7 devices have two on-chip 16-bit timers.
They are completely independent, and do not – Counter Low Register (CLR) is the least sig-
share any resources. They are synchronized after nificant byte (LS byte).
a MCU reset as long as the timer clock frequen- Alternate Counter Register (ACR)
cies are not modified. – Alternate Counter High Register (ACHR) is the
This description covers one or two 16-bit timers. In most significant byte (MS byte).
ST7 devices with two timers, register names are – Alternate Counter Low Register (ACLR) is the
prefixed with TA (Timer A) or TB (Timer B). least significant byte (LS byte).
12.2.2 Main features These two read-only 16-bit registers contain the
■ Programmable prescaler: fCPU divided by 2, 4 or 8 same value but with the difference that reading the
■ Overflow status flag and maskable interrupt
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register, (SR),
■ External clock input (must be at least four times
(see note at the end of paragraph titled 16-bit read
slower than the CPU clock speed) with the choice sequence).
of active edge
Writing in the CLR register or ACLR register resets
■ 1 or 2 Output Compare functions each with:
the free running counter to the FFFCh value.
– 2 dedicated 16-bit registers Both counters have a reset value of FFFCh (this is
– 2 dedicated programmable signals the only value which is reloaded in the 16-bit tim-
er). The reset value of both counters is also
– 2 dedicated status flags FFFCh in One Pulse mode and PWM mode.
– 1 dedicated maskable interrupt
■ 1 or 2 Input Capture functions each with:
The timer clock depends on the clock control bits
– 2 dedicated 16-bit registers of the CR2 register, as illustrated in Table 18,
– 2 dedicated active edge selection signals "Clock Control Bits". The value in the counter reg-
ister repeats every 131072, 262144 or 524288
– 2 dedicated status flags CPU clock cycles depending on the CC[1:0] bits.
– 1 dedicated maskable interrupt The timer frequency can be fCPU/2, fCPU/4, fCPU/8
■ Pulse width modulation mode (PWM) or an external frequency.
■ One Pulse mode

■ Reduced Power mode

■ 5 alternate functions on I/O ports (ICAP1, ICAP2,

OCMP1, OCMP2, EXTCLK)*

The block diagram is shown in Figure 27.

*Note: Some timer pins may not be available (not
bonded) in some ST7 devices. Refer to the device
pin out description.

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16-bit timer (Cont’d)

Figure 27. Timer block diagram

ST7 INTERNAL BUS

fCPU
MCU-PERIPHERAL INTERFACE

8 high 8 low
8-bit 8 8 8 8 8 8 8 8
buffer

high

high

high

high
low

low

low

low
EXEDG
16

1/2 OUTPUT OUTPUT INPUT INPUT

COUNTER
COMPARE COMPARE CAPTURE CAPTURE
1/4
REGISTER REGISTER REGISTER REGISTER REGISTER
1/8
1 2 1 2
EXTCLK ALTERNATE
pin COUNTER
16 16
REGISTER
16
CC[1:0]
TIMER INTERNAL BUS
16 16

OVERFLOW
OUTPUT COMPARE EDGE DETECT ICAP1
DETECT
CIRCUIT CIRCUIT1 pin
CIRCUIT

6 EDGE DETECT ICAP2

CIRCUIT2 pin

LATCH1 OCMP1
pin
ICF1 OCF1 TOF ICF2 OCF2 TIMD 0 0
(Control/Status Register) LATCH2 OCMP2
CSR pin

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

(Control Register 1) CR1 (Control Register 2) CR2

(See note)

TIMER INTERRUPT Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (See device Interrupt Vector Table)

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16-bit timer (Cont’d)

16-bit read sequence: (from either the Counter Clearing the overflow interrupt request is done in
Register or the Alternate Counter Register). two steps:
Beginning of the sequence 1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Read LS byte Notes: The TOF bit is not cleared by accesses to
At t0 MS byte is buffered ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
Other it allows simultaneous use of the overflow function
instructions and reading the free running counter at random
times (for example, to measure elapsed time) with-
Read Returns the buffered out the risk of clearing the TOF bit erroneously.
At t0 +∆t LS byte LS byte value at t0 The timer is not affected by Wait mode.
Sequence completed In Halt mode, the counter stops counting until the
mode is exited. Counting then resumes from the
The user must read the MS byte first, then the LS previous count (MCU awakened by an interrupt) or
byte value is buffered automatically. from the reset count (MCU awakened by a Reset).
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the [Link] External clock
user reads the MS byte several times.
The external clock (where available) is selected if
After a complete reading sequence, if only the CC0 = 1 and CC1 = 1 in the CR2 register.
CLR register or ACLR register are read, they re-
The status of the EXEDG bit in the CR2 register
turn the LS byte of the count value at the time of
determines the type of level transition on the exter-
the read.
nal clock pin EXTCLK that will trigger the free run-
Whatever the timer mode used (input capture, out- ning counter.
put compare, One Pulse mode or PWM mode) an
The counter is synchronized with the falling edge
overflow occurs when the counter rolls over from
of the internal CPU clock.
FFFFh to 0000h then:
A minimum of four falling edges of the CPU clock
– The TOF bit of the SR register is set.
must occur between two consecutive active edges
– A timer interrupt is generated if: of the external clock; thus the external clock fre-
– TOIE bit of the CR1 register is set and quency must be less than a quarter of the CPU
clock frequency.
– I bit of the CC register is cleared.
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.

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16-bit timer (Cont’d)

Figure 28. Counter timing diagram, internal clock divided by 2

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

FFFD FFFE FFFF 0000 0001 0002 0003

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

Figure 29. Counter timing diagram, internal clock divided by 4

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER FFFC FFFD 0000 0001

TIMER OVERFLOW FLAG (TOF)

Figure 30. Counter timing diagram, internal clock divided by 8

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER FFFC FFFD 0000

TIMER OVERFLOW FLAG (TOF)

Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.

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16-bit timer (Cont’d)

[Link] Input Capture When an input capture occurs:
In this section, the index, i, may be 1 or 2 because – ICFi bit is set.
there are two input capture functions in the 16-bit – The ICiR register contains the value of the free
timer. running counter on the active transition on the
The two 16-bit input capture registers (IC1R and ICAPi pin (see Figure 32).
IC2R) are used to latch the value of the free run- – A timer interrupt is generated if the ICIE bit is set
ning counter after a transition is detected on the and the I bit is cleared in the CC register. Other-
ICAPi pin (see Figure 31). wise, the interrupt remains pending until both
MS byte LS byte conditions become true.
ICiR ICiHR ICiLR Clearing the Input Capture interrupt request (that
is, clearing the ICFi bit) is done in two steps:
ICiR register is a read-only register. 1. Reading the SR register while the ICFi bit is set.
The active transition is software programmable 2. An access (read or write) to the ICiLR register.
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
counter: (fCPU/CC[1:0]). Notes:
1. After reading the ICiHR register, transfer of
input capture data is inhibited and ICFi will
Procedure: never be set until the ICiLR register is also
To use the input capture function select the follow- read.
ing in the CR2 register: 2. The ICiR register contains the free running
– Select the timer clock (CC[1:0]) (see Table 18, counter value which corresponds to the most
"Clock Control Bits"). recent input capture.
– Select the edge of the active transition on the 3. The two input capture functions can be used
ICAP2 pin with the IEDG2 bit (the ICAP2 pin together even if the timer also uses the two out-
must be configured as floating input or input with put compare functions.
pull-up without interrupt if this configuration is 4. In One Pulse mode and PWM mode only Input
available). Capture 2 can be used.
And select the following in the CR1 register: 5. The alternate inputs (ICAP1 and ICAP2) are
– Set the ICIE bit to generate an interrupt after an always directly connected to the timer. So any
input capture coming from either the ICAP1 pin transitions on these pins activates the input
or the ICAP2 pin capture function.
– Select the edge of the active transition on the Moreover if one of the ICAPi pins is configured
ICAP1 pin with the IEDG1 bit (the ICAP1pin must as an input and the second one as an output,
be configured as floating input or input with pull- an interrupt can be generated if the user tog-
up without interrupt if this configuration is availa- gles the output pin and if the ICIE bit is set.
ble). This can be avoided if the input capture func-
tion i is disabled by reading the ICiHR (see note
1).
6. The TOF bit can be used with interrupt genera-
tion in order to measure events that go beyond
the timer range (FFFFh).

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16-bit timer (Cont’d)

Figure 31. Input Capture block diagram

ICAP1 (Control Register 1) CR1

pin
EDGE DETECT EDGE DETECT ICIE IEDG1
ICAP2 CIRCUIT2 CIRCUIT1
pin (Status Register) SR

IC2R Register IC1R Register ICF1 ICF2 0 0 0

16-BIT (Control Register 2) CR2

16-BIT FREE RUNNING CC1 CC0 IEDG2

COUNTER

Figure 32. Input Capture timing diagram

TIMER CLOCK

COUNTER REGISTER FF01 FF02 FF03

ICAPi PIN

ICAPi FLAG

ICAPi REGISTER FF03

Note: The rising edge is the active edge.

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16-bit timer (Cont’d)

[Link] Output Compare – The OCMPi pin takes OLVLi bit value (OCMPi
In this section, the index, i, may be 1 or 2 because pin latch is forced low during reset).
there are two output compare functions in the 16- – A timer interrupt is generated if the OCIE bit is
bit timer. set in the CR1 register and the I bit is cleared in
This function can be used to control an output the CC register (CC).
waveform or indicate when a period of time has
elapsed. The OCiR register value required for a specific tim-
When a match is found between the Output Com- ing application can be calculated using the follow-
pare register and the free running counter, the out- ing formula:
put compare function:
– Assigns pins with a programmable value if the ∆t * fCPU
OCiE bit is set ∆ OCiR =
PRESC
– Sets a flag in the status register
Where:
– Generates an interrupt if enabled
∆t = Output compare period (in seconds)
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R) fCPU = CPU clock frequency (in hertz)
contain the value to be compared to the counter PRESC = Timer prescaler factor (2, 4 or 8 de-
register each timer clock cycle. pending on CC[1:0] bits, see Table 18,
MS byte LS byte
"Clock Control Bits")
OCiR OCiHR OCiLR
If the timer clock is an external clock, the formula
These registers are readable and writable and are is:
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h. ∆ OCiR = ∆t * fEXT
Timing resolution is one count of the free running Where:
counter: (fCPU/CC[1:0]).
∆t = Output compare period (in seconds)
fEXT = External timer clock frequency (in hertz)
Procedure:
To use the output compare function, select the fol-
lowing in the CR2 register: Clearing the output compare interrupt request
(that is, clearing the OCFi bit) is done by:
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i 1. Reading the SR register while the OCFi bit is
signal. set.
– Select the timer clock (CC[1:0]) (see Table 18, 2. An access (read or write) to the OCiLR register.
"Clock Control Bits"). The following procedure is recommended to pre-
And select the following in the CR1 register: vent the OCFi bit from being set between the time
it is read and the write to the OCiR register:
– Select the OLVLi bit to applied to the OCMPi pins
after the match occurs. – Write to the OCiHR register (further compares
are inhibited).
– Set the OCIE bit to generate an interrupt if it is
needed. – Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
When a match is found between OCiR register
and CR register: – Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
– OCFi bit is set.

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16-bit timer (Cont’d)

Notes: Forced Compare output capability
1. After a processor write cycle to the OCiHR reg- When the FOLVi bit is set by software, the OLVLi
ister, the output compare function is inhibited bit is copied to the OCMPi pin. The OLVi bit has to
until the OCiLR register is also written. be toggled in order to toggle the OCMPi pin when
2. If the OCiE bit is not set, the OCMPi pin is a it is enabled (OCiE bit = 1). The OCFi bit is then
general I/O port and the OLVLi bit will not not set by hardware, and thus no interrupt request
appear when a match is found but an interrupt is generated.
could be generated if the OCIE bit is set. The FOLVLi bits have no effect in both One Pulse
3. In both internal and external clock modes, mode and PWM mode.
OCFi and OCMPi are set while the counter
value equals the OCiR register value (see Fig-
ure 34 on page 53 for an example with fCPU/2
and Figure 35 on page 53 for an example with
fCPU/4). This behavior is the same in OPM or
PWM mode.
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OCiR register and the
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.

Figure 33. Output Compare block diagram

16 BIT FREE RUNNING OC1E OC2E CC1 CC0

COUNTER
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE Latch
OCIE FOLV2 FOLV1 OLVL2 OLVL1 OCMP1
CIRCUIT 1
Pin
16-bit 16-bit
Latch
2 OCMP2
OC1R Register Pin
OCF1 OCF2 0 0 0
OC2R Register
(Status Register) SR

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16-bit timer (Cont’d)

Figure 34. Output Compare timing diagram, fTIMER = fCPU/2

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER REGISTER 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4

OUTPUT COMPARE REGISTER i (OCRi) 2ED3

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi = 1)

Figure 35. Output Compare timing diagram, fTIMER = fCPU/4

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER REGISTER 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4

OUTPUT COMPARE REGISTER i (OCRi) 2ED3

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi = 1)

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16-bit timer (Cont’d)

[Link] One Pulse mode Clearing the Input Capture interrupt request (that
One Pulse mode enables the generation of a is, clearing the ICFi bit) is done in two steps:
pulse when an external event occurs. This mode is 1. Reading the SR register while the ICFi bit is set.
selected via the OPM bit in the CR2 register. 2. An access (read or write) to the ICiLR register.
The One Pulse mode uses the Input Capture1 The OC1R register value required for a specific
function and the Output Compare1 function. timing application can be calculated using the fol-
Procedure: lowing formula:
To use One Pulse mode: t * fCPU -5
OCiR value =
1. Load the OC1R register with the value corre- PRESC
sponding to the length of the pulse (see the for- Where:
mula in the opposite column). t = Pulse period (in seconds)
2. Select the following in the CR1 register: fCPU = CPU clock frequency (in hertz)
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after the pulse. PRESC = Timer prescaler factor (2, 4 or 8 depend-
ing on the CC[1:0] bits, see Table 18,
– Using the OLVL2 bit, select the level to be ap- "Clock Control Bits")
plied to the OCMP1 pin during the pulse. If the timer clock is an external clock the formula is:
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin OCiR = t * fEXT -5
must be configured as floating input).
Where:
3. Select the following in the CR2 register:
t = Pulse period (in seconds)
– Set the OC1E bit, the OCMP1 pin is then ded-
icated to the Output Compare 1 function. fEXT = External timer clock frequency (in hertz)
– Set the OPM bit.
– Select the timer clock CC[1:0] (see Table 18, When the value of the counter is equal to the value
"Clock Control Bits"). of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin, (See Figure 36).

One Pulse mode cycle

Notes:
ICR1 = Counter 1. The OCF1 bit cannot be set by hardware in
When One Pulse mode but the OCF2 bit can generate
event occurs OCMP1 = OLVL2
an Output Compare interrupt.
on ICAP1 Counter is reset
to FFFCh 2. When the Pulse Width Modulation (PWM) and
One Pulse mode (OPM) bits are both set, the
ICF1 bit is set PWM mode is the only active one.
3. If OLVL1 = OLVL2 a continuous signal will be
When
Counter seen on the OCMP1 pin.
= OC1R OCMP1 = OLVL1 4. The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R can be
Then, on a valid event on the ICAP1 pin, the coun- loaded) but the user must take care that the
ter is initialized to FFFCh and OLVL2 bit is loaded counter is reset each time a valid edge occurs
on the OCMP1 pin, the ICF1 bit is set and the val- on the ICAP1 pin and ICF1 can also generates
ue FFFDh is loaded in the IC1R register. interrupt if ICIE is set.
Because the ICF1 bit is set when an active edge 5. When One Pulse mode is used OC1R is dedi-
occurs, an interrupt can be generated if the ICIE cated to this mode. Nevertheless OC2R and
bit is set. OCF2 can be used to indicate a period of time
has been elapsed but cannot generate an out-
put waveform because the level OLVL2 is dedi-
cated to the One Pulse mode.

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16-bit timer (Cont’d)

Figure 36. One Pulse mode timing example

IC1R 01F8 2ED3

01F8 FFFC FFFD FFFE 2ED0 2ED1 2ED2 FFFC FFFD

COUNTER
2ED3

ICAP1

OLVL2 OLVL1 OLVL2

OCMP1
compare1

Note: IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1

Figure 37. Pulse Width Modulation mode timing example with 2 Output Compare functions

COUNTER 34E2 FFFC FFFD FFFE 2ED0 2ED1 2ED2 34E2 FFFC

OCMP1 OLVL2 OLVL1 OLVL2

compare2 compare1 compare2

Note: OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1

Note: On timers with only one Output Compare register, a fixed frequency PWM signal can be generated
using the output compare and the counter overflow to define the pulse length.

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16-bit timer (Cont’d)

[Link] Pulse Width Modulation mode If OLVL1 = 1 and OLVL2 = 0 the length of the pos-
Pulse Width Modulation (PWM) mode enables the itive pulse is the difference between the OC2R and
generation of a signal with a frequency and pulse OC1R registers.
length determined by the value of the OC1R and If OLVL1 = OLVL2 a continuous signal will be
OC2R registers. seen on the OCMP1 pin.
Pulse Width Modulation mode uses the complete The OCiR register value required for a specific tim-
Output Compare 1 function plus the OC2R regis- ing application can be calculated using the follow-
ter, and so this functionality can not be used when ing formula:
PWM mode is activated. t * fCPU
OCiR value =
-5
In PWM mode, double buffering is implemented on
PRESC
the output compare registers. Any new values writ-
ten in the OC1R and OC2R registers are taken Where:
into account only at the end of the PWM period t = Signal or pulse period (in seconds)
(OC2) to avoid spikes on the PWM output pin fCPU = CPU clock frequency (in hertz)
(OCMP1).
PRESC = Timer prescaler factor (2, 4 or 8 depend-
Procedure ing on CC[1:0] bits, see Table 18,
To use Pulse Width Modulation mode: "Clock Control Bits")
1. Load the OC2R register with the value corre- If the timer clock is an external clock the formula is:
sponding to the period of the signal using the
formula in the opposite column. OCiR = t * fEXT -5
2. Load the OC1R register with the value corre- Where:
sponding to the period of the pulse if t = Signal or pulse period (in seconds)
(OLVL1 = 0 and OLVL2 = 1) using the formula
in the opposite column. fEXT = External timer clock frequency (in hertz)
3. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be ap- The Output Compare 2 event causes the counter
plied to the OCMP1 pin after a successful to be initialized to FFFCh (See Figure 37)
comparison with the OC1R register. Notes:
– Using the OLVL2 bit, select the level to be ap- 1. After a write instruction to the OCiHR register,
plied to the OCMP1 pin after a successful the output compare function is inhibited until the
comparison with the OC2R register. OCiLR register is also written.
4. Select the following in the CR2 register: 2. The OCF1 and OCF2 bits cannot be set by
– Set OC1E bit: the OCMP1 pin is then dedicat- hardware in PWM mode therefore the Output
ed to the output compare 1 function. Compare interrupt is inhibited.
– Set the PWM bit. 3. The ICF1 bit is set by hardware when the coun-
ter reaches the OC2R value and can produce a
– Select the timer clock (CC[1:0]) (see Table 18,
"Clock Control Bits"). timer interrupt if the ICIE bit is set and the I bit is
cleared.
Pulse Width Modulation cycle 4. In PWM mode the ICAP1 pin can not be used
to perform input capture because it is discon-
When nected to the timer. The ICAP2 pin can be used
Counter OCMP1 = OLVL1 to perform input capture (ICF2 can be set and
= OC1R IC2R can be loaded) but the user must take
care that the counter is reset each period and
ICF1 can also generates interrupt if ICIE is set.
When OCMP1 = OLVL2 5. When the Pulse Width Modulation (PWM) and
Counter Counter is reset One Pulse mode (OPM) bits are both set, the
= OC2R to FFFCh PWM mode is the only active one.
ICF1 bit is set

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16-bit timer (Cont’d)

12.2.4 Low power modes
Mode Description
No effect on 16-bit timer.
Wait
Timer interrupts cause the device to exit from Wait mode.
16-bit timer registers are frozen.
In Halt mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from Halt mode” capability or from the counter
Halt reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-
ly, when the MCU is woken up by an interrupt with “exit from Halt mode” capability, the ICFi bit is set, and
the counter value present when exiting from Halt mode is captured into the ICiR register.

12.2.5 Interrupts
Enable Exit Exit
Event
Interrupt event control from from
flag
bit Wait Halt
Input Capture 1 event/Counter reset in PWM mode ICF1
ICIE
Input Capture 2 event ICF2
Output Compare 1 event (not available in PWM mode) OCF1 Yes No
OCIE
Output Compare 2 event (not available in PWM mode) OCF2
Timer Overflow event TOF TOIE

Note: The 16-bit timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).

12.2.6 Summary of timer modes

Timer resources
MODES
Input Capture 1 Input Capture 2 Output Compare 1 Output Compare 2
Input Capture (1 and/or 2)
Yes Yes Yes Yes
Output Compare (1 and/or 2)
One Pulse mode Not Recommended1) Partially 2)
No No
PWM mode Not Recommended3) No

1) See note 4 in Section [Link], "One Pulse mode"

2) See note 5 in Section [Link], "One Pulse mode"
3) See note 4 in Section [Link], "Pulse Width Modulation mode"

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16-bit timer (Cont’d)

12.2.7 Register description Bit 4 = FOLV2 Forced Output Compare 2.
Each Timer is associated with three control and This bit is set and cleared by software.
status registers, and with six pairs of data registers 0: No effect on the OCMP2 pin.
(16-bit values) relating to the two input captures, 1: Forces the OLVL2 bit to be copied to the
the two output compares, the counter and the al- OCMP2 pin, if the OC2E bit is set and even if
ternate counter. there is no successful comparison.

Control Register 1 (CR1) Bit 3 = FOLV1 Forced Output Compare 1.

This bit is set and cleared by software.
Read/Write 0: No effect on the OCMP1 pin.
Reset value: 0000 0000 (00h) 1: Forces OLVL1 to be copied to the OCMP1 pin, if
7 0 the OC1E bit is set and even if there is no suc-
cessful comparison.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 2 = OLVL2 Output Level 2.
Bit 7 = ICIE Input Capture Interrupt Enable. This bit is copied to the OCMP2 pin whenever a
0: Interrupt is inhibited. successful comparison occurs with the OC2R reg-
1: A timer interrupt is generated whenever the ister and OCxE is set in the CR2 register. This val-
ICF1 or ICF2 bit of the SR register is set. ue is copied to the OCMP1 pin in One Pulse mode
and Pulse Width Modulation mode.

Bit 6 = OCIE Output Compare Interrupt Enable.

0: Interrupt is inhibited. Bit 1 = IEDG1 Input Edge 1.
1: A timer interrupt is generated whenever the This bit determines which type of level transition
OCF1 or OCF2 bit of the SR register is set. on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF Bit 0 = OLVL1 Output Level 1.
bit of the SR register is set. The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.

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16-bit timer (Cont’d)

Control Register 2 (CR2) Bit 4 = PWM Pulse Width Modulation.
Read/Write 0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
Reset value: 0000 0000 (00h) programmable cyclic signal; the length of the
7 0
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

Bit 3, 2 = CC[1:0] Clock Control.

Bit 7 = OC1E Output Compare 1 Pin Enable.
The timer clock mode depends on these bits:
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Com- Table 18. Clock Control Bits
pare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E Timer Clock CC1 CC0
bit, the Output Compare 1 function of the timer re- fCPU / 4 0
mains active. 0
fCPU / 2 1
0: OCMP1 pin alternate function disabled (I/O pin fCPU / 8 0
free for general-purpose I/O). 1
1: OCMP1 pin alternate function enabled. External Clock (where available) 1

Bit 6 = OC2E Output Compare 2 Pin Enable. Note: If the external clock pin is not available, pro-
This bit is used only to output the signal from the gramming the external clock configuration stops
timer on the OCMP2 pin (OLV2 in Output Com- the counter.
pare mode). Whatever the value of the OC2E bit,
the Output Compare 2 function of the timer re-
Bit 1 = IEDG2 Input Edge 2.
mains active.
This bit determines which type of level transition
0: OCMP2 pin alternate function disabled (I/O pin
on the ICAP2 pin will trigger the capture.
free for general-purpose I/O).
0: A falling edge triggers the capture.
1: OCMP2 pin alternate function enabled.
1: A rising edge triggers the capture.

Bit 5 = OPM One Pulse Mode.

Bit 0 = EXEDG External Clock Edge.
0: One Pulse mode is not active.
This bit determines which type of level transition
1: One Pulse mode is active, the ICAP1 pin can be
on the external clock pin EXTCLK will trigger the
used to trigger one pulse on the OCMP1 pin; the
counter register.
active transition is given by the IEDG1 bit. The
0: A falling edge triggers the counter register.
length of the generated pulse depends on the
1: A rising edge triggers the counter register.
contents of the OC1R register.

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16-bit timer (Cont’d)

Control/status Register (CSR) Note: Reading or writing the ACLR register does
Read/Write (bits 7:3 read only) not clear TOF.
Reset value: xxxx x0xx (xxh)
7 0 Bit 4 = ICF2 Input Capture flag 2.
0: No input capture (reset value).
ICF1 OCF1 TOF ICF2 OCF2 TIMD 0 0 1: An input capture has occurred on the ICAP2
pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R
Bit 7 = ICF1 Input Capture flag 1. (IC2LR) register.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin Bit 3 = OCF2 Output Compare flag 2.
or the counter has reached the OC2R value in 0: No match (reset value).
PWM mode. To clear this bit, first read the SR 1: The content of the free running counter has
register, then read or write the low byte of the matched the content of the OC2R register. To
IC1R (IC1LR) register. clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) reg-
Bit 6 = OCF1 Output Compare flag 1. ister.
0: No match (reset value).
1: The content of the free running counter has Bit 2 = TIMD Timer disable.
matched the content of the OC1R register. To This bit is set and cleared by software. When set, it
clear this bit, first read the SR register, then read freezes the timer prescaler and counter and disa-
or write the low byte of the OC1R (OC1LR) reg- bled the output functions (OCMP1 and OCMP2
ister. pins) to reduce power consumption. Access to the
timer registers is still available, allowing the timer
Bit 5 = TOF Timer Overflow flag. configuration to be changed, or the counter reset,
0: No timer overflow (reset value). while it is disabled.
1: The free running counter rolled over from FFFFh 0: Timer enabled
to 0000h. To clear this bit, first read the SR reg- 1: Timer prescaler, counter and outputs disabled
ister, then read or write the low byte of the CR
(CLR) register. Bits 1:0 = Reserved, must be kept cleared.

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16-bit timer (Cont’d)

Input Capture 1 High Register (IC1HR) Output Compare 1 High Register (OC1HR)
Read Only Read/Write
Reset value: Undefined Reset value: 1000 0000 (80h)
This is an 8-bit read only register that contains the This is an 8-bit register that contains the high part
high part of the counter value (transferred by the of the value to be compared to the CHR register.
input capture 1 event).
7 0
7 0
MSB LSB
MSB LSB

Output Compare 1 Low Register (OC1LR)

Input Capture 1 Low Register (IC1LR) Read/Write
Read Only Reset value: 0000 0000 (00h)
Reset value: Undefined This is an 8-bit register that contains the low part of
This is an 8-bit read only register that contains the the value to be compared to the CLR register.
low part of the counter value (transferred by the in-
put capture 1 event). 7 0

7 0 MSB LSB

MSB LSB

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Output Compare 2 High Register (OC2HR) Alternate Counter High Register (ACHR)
Read/Write Read Only
Reset value: 1000 0000 (80h) Reset value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part This is an 8-bit register that contains the high part
of the value to be compared to the CHR register. of the counter value.
7 0 7 0

MSB LSB MSB LSB

Output Compare 2 Low Register (OC2LR) Alternate Counter Low Register (ACLR)
Read/Write Read Only
Reset value: 0000 0000 (00h) Reset value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of This is an 8-bit register that contains the low part of
the value to be compared to the CLR register. the counter value. A write to this register resets the
counter. An access to this register after an access
7 0 to CSR register does not clear the TOF bit in the
CSR register.
MSB LSB
7 0

Counter High Register (CHR) MSB LSB

Read Only
Reset value: 1111 1111 (FFh)
Input Capture 2 High Register (IC2HR)
This is an 8-bit register that contains the high part
of the counter value. Read Only
Reset value: Undefined
7 0 This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
MSB LSB Input Capture 2 event).
7 0

Counter Low Register (CLR) MSB LSB

Read Only
Reset value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of Input Capture 2 Low Register (IC2LR)
the counter value. A write to this register resets the
counter. An access to this register after accessing Read Only
the CSR register clears the TOF bit. Reset value: Undefined
This is an 8-bit read only register that contains the
7 0 low part of the counter value (transferred by the In-
put Capture 2 event).
MSB LSB
7 0

MSB LSB

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Table 19. 16-bit timer register map and reset values
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
CR2 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
11
Reset value 0 0 0 0 0 0 0 0
CR1 ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
12
Reset value 0 0 0 0 0 0 0 0
CSR ICF1 OCF1 TOF ICF2 OCF2 TIMD 0 0
13
Reset value 0 0 0 0 0 0 0 0
IC1HR
14 MSB LSB
Reset value
IC1LR
15 MSB LSB
Reset value
OC1HR MSB - - - - - - LSB
16
Reset value 1 0 0 0 0 0 0 0
OC1LR MSB - - - - - - LSB
17
Reset value 0 0 0 0 0 0 0 0
CHR MSB - - - - - - LSB
18
Reset value 1 1 1 1 1 1 1 1
CLR MSB - - - - - - LSB
19
Reset value 1 1 1 1 1 1 0 0
ACHR MSB - - - - - - LSB
1A
Reset value 1 1 1 1 1 1 1 1
ACLR MSB - - - - - - LSB
1B
Reset value 1 1 1 1 1 1 0 0
IC2HR
1C MSB LSB
Reset value
IC2LR
1D MSB LSB
Reset value
OC2HR MSB - - - - - - LSB
1E
Reset value 1 0 0 0 0 0 0 0
OC2LR MSB - - - - - - LSB
1F
Reset value 0 0 0 0 0 0 0 0

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12.3 Serial communications interface (SCI)

12.3.1 Introduction 12.3.3 General description
The Serial Communications Interface (SCI) offers The interface is externally connected to another
a flexible means of full-duplex data exchange with device by two pins (see Figure 39):
external equipment requiring an industry standard – TDO: Transmit Data Output. When the transmit-
NRZ asynchronous serial data format. The SCI of- ter and the receiver are disabled, the output pin
fers a very wide range of baud rates using two returns to its I/O port configuration. When the
baud rate generator systems. transmitter and/or the receiver are enabled and
12.3.2 Main features nothing is to be transmitted, the TDO pin is at
■ Full duplex, asynchronous communications high level.
■ NRZ standard format (Mark/Space) – RDI: Receive Data Input is the serial data input.
■ Independently programmable transmit and Oversampling techniques are used for data re-
receive baud rates up to 250K baud. covery by discriminating between valid incoming
data and noise.
■ Programmable data word length (8 or 9 bits)
Through these pins, serial data is transmitted and
■ Receive buffer full, Transmit buffer empty and
received as frames comprising:
End of Transmission flags
– An Idle Line prior to transmission or reception
■ Two receiver wake-up modes:
– A start bit
– Address bit (MSB)
– A data word (8 or 9 bits) least significant bit first
– Idle line
■ Muting function for multiprocessor configurations
– A Stop bit indicating that the frame is complete.
■ Separate enable bits for Transmitter and This interface uses two types of baud rate generator:
Receiver – A conventional type for commonly-used baud
■ Four error detection flags: rates.
– Overrun error
– Noise error
– Frame error
– Parity error
■ Six interrupt sources with flags:

– Transmit data register empty

– Transmission complete
– Receive data register full
– Idle line received
– Overrun error detected
– Parity error
■ Parity control:

– Transmits parity bit

– Checks parity of received data byte
■ Reduced power consumption mode

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Figure 38. SCI block diagram

Write Read (DATA REGISTER) DR

Transmit Data Register (TDR) Received Data Register (RDR)

TDO

Transmit Shift Register Received Shift Register

RDI
CR1
R8 T8 SCID M WAKE PCE PS PIE

WAKE
TRANSMIT UP RECEIVER RECEIVER
CONTROL UNIT CONTROL CLOCK

CR2 SR
TIE TCIE RIE ILIE TE RE RWU SBK TDRE TC RDRF IDLE OR NF FE PE

SCI
INTERRUPT
CONTROL

TRANSMITTER
CLOCK
TRANSMITTER RATE
CONTROL
fCPU
/16 /PR
BRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0

RECEIVER RATE
CONTROL

BAUD RATE GENERATOR

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12.3.4 Functional description The TDO pin is in low state during the start bit.
The block diagram of the Serial Control Interface, The TDO pin is in high state during the stop bit.
is shown in Figure 38 It contains 6 dedicated reg- An Idle character is interpreted as an entire frame
isters: of “1”s followed by the start bit of the next frame
– Two control registers (SCICR1 & SCICR2) which contains data.
– A status register (SCISR) A Break character is interpreted on receiving “0”s
– A baud rate register (SCIBRR) for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an ex-
Refer to the register descriptions in Section 12.3.7 tra “1” bit to acknowledge the start bit.
for the definitions of each bit.
Transmission and reception are driven by their
[Link] Serial data format own baud rate generator.
Word length may be selected as being either 8 or 9
bits by programming the M bit in the SCICR1 reg-
ister (see Figure 38).
Figure 39. Word length programming

9-bit Word length (M bit is set)

Possible Next Data Frame
Parity
Data Frame Bit Next
Start Stop Start
Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit
Bit

Start
Idle Frame Bit

Break Frame Extra Start

’1’ Bit

8-bit Word length (M bit is reset)

Possible Next Data Frame
Data Frame Parity
Bit Next
Start Stop Start
Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit
Bit

Start
Idle Frame Bit

Break Frame Extra Start

’1’ Bit

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[Link] Transmitter When a frame transmission is complete (after the
The transmitter can send data words of either 8 or stop bit or after the break frame) the TC bit is set
9 bits depending on the M bit status. When the M and an interrupt is generated if the TCIE is set and
bit is set, word length is 9 bits and the 9th bit (the the I bit is cleared in the CCR register.
MSB) has to be stored in the T8 bit in the SCICR1 Clearing the TC bit is performed by the following
register. software sequence:
Character transmission 1. An access to the SCISR register
2. A write to the SCIDR register
During an SCI transmission, data shifts out least
significant bit first on the TDO pin. In this mode, Note: The TDRE and TC bits are cleared by the
the SCIDR register consists of a buffer (TDR) be- same software sequence.
tween the internal bus and the transmit shift regis- Break characters
ter (see Figure 38). Setting the SBK bit loads the shift register with a
Procedure break character. The break frame length depends
– Select the M bit to define the word length. on the M bit (see Figure 39).
– Select the desired baud rate using the SCIBRR As long as the SBK bit is set, the SCI send break
and the SCIETPR registers. frames to the TDO pin. After clearing this bit by
software the SCI insert a logic 1 bit at the end of
– Set the TE bit to assign the TDO pin to the alter- the last break frame to guarantee the recognition
nate function and to send a idle frame as first of the start bit of the next frame.
transmission.
Idle characters
– Access the SCISR register and write the data to
send in the SCIDR register (this sequence clears Setting the TE bit drives the SCI to send an idle
the TDRE bit). Repeat this sequence for each frame before the first data frame.
data to be transmitted. Clearing and then setting the TE bit during a trans-
Clearing the TDRE bit is always performed by the mission sends an idle frame after the current word.
following software sequence: Note: Resetting and setting the TE bit causes the
1. An access to the SCISR register data in the TDR register to be lost. Therefore the
2. A write to the SCIDR register best time to toggle the TE bit is when the TDRE bit
The TDRE bit is set by hardware and it indicates: is set i.e. before writing the next byte in the SCIDR.
– The TDR register is empty.
– The data transfer is beginning.
– The next data can be written in the SCIDR regis-
ter without overwriting the previous data.
This flag generates an interrupt if the TIE bit is set
and the I bit is cleared in the CCR register.
When a transmission is taking place, a write in-
struction to the SCIDR register stores the data in
the TDR register and which is copied in the shift
register at the end of the current transmission.
When no transmission is taking place, a write in-
struction to the SCIDR register places the data di-
rectly in the shift register, the data transmission
starts, and the TDRE bit is immediately set.

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[Link] Receiver RDR register as long as the RDRF bit is not
The SCI can receive data words of either 8 or 9 cleared.
bits. When the M bit is set, word length is 9 bits When a overrun error occurs:
and the MSB is stored in the R8 bit in the SCICR1 – The OR bit is set.
register.
– The RDR content will not be lost.
Character reception
– The shift register will be overwritten.
During a SCI reception, data shifts in least signifi-
cant bit first through the RDI pin. In this mode, the – An interrupt is generated if the RIE bit is set and
SCIDR register consists or a buffer (RDR) be- the I bit is cleared in the CCR register.
tween the internal bus and the received shift regis- The OR bit is reset by an access to the SCISR reg-
ter (see Figure 38). ister followed by a SCIDR register read operation.
Procedure Noise error
– Select the M bit to define the word length. Oversampling techniques are used for data recov-
– Select the desired baud rate using the SCIBRR ery by discriminating between valid incoming data
and the SCIERPR registers. and noise. Normal data bits are considered valid if
three consecutive samples (8th, 9th, 10th) have
– Set the RE bit, this enables the receiver which the same bit value, otherwise the NF flag is set. In
begins searching for a start bit. the case of start bit detection, the NF flag is set on
When a character is received: the basis of an algorithm combining both valid
– The RDRF bit is set. It indicates that the content edge detection and three samples (8th, 9th, 10th).
of the shift register is transferred to the RDR. Therefore, to prevent the NF flag getting set during
start bit reception, there should be a valid edge de-
– An interrupt is generated if the RIE bit is set and tection as well as three valid samples.
the I bit is cleared in the CCR register.
When noise is detected in a frame:
– The error flags can be set if a frame error, noise
or an overrun error has been detected during re- – The NF flag is set at the rising edge of the RDRF
ception. bit.
Clearing the RDRF bit is performed by the following – Data is transferred from the Shift register to the
software sequence done by: SCIDR register.
1. An access to the SCISR register – No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
2. A read to the SCIDR register. generates an interrupt.
The RDRF bit must be cleared before the end of the The NF flag is reset by a SCISR register read op-
reception of the next character to avoid an overrun eration followed by a SCIDR register read opera-
error. tion.
Break characters During reception, if a false start bit is detected (e.g.
When a break character is received, the SCI han- 8th, 9th, 10th samples are 011,101,110), the
dles it as a framing error. frame is discarded and the receiving sequence is
Idle characters not started for this frame. There is no RDRF bit set
for this frame and the NF flag is set internally (not
When a idle frame is detected, there is the same accessible to the user). This NF flag is accessible
procedure as a data received character plus an in- along with the RDRF bit when a next valid frame is
terrupt if the ILIE bit is set and the I bit is cleared in received.
the CCR register.
Note: If the application Start Bit is not long enough
Overrun error to match the above requirements, then the NF flag
An overrun error occurs when a character is re- may get set due to the short Start Bit. In this case,
ceived when RDRF has not been reset. Data can the NF flag may be ignored by the application soft-
not be transferred from the shift register to the ware when the first valid byte is received.
See also Section [Link].

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Framing error [Link] Receiver Muting and Wake-up feature
A framing error is detected when: In multiprocessor configurations it is often desira-
– The stop bit is not recognized on reception at the ble that only the intended message recipient
expected time, following either a de-synchroni- should actively receive the full message contents,
zation or excessive noise. thus reducing redundant SCI service overhead for
all non addressed receivers.
– A break is received.
The non addressed devices may be placed in
When the framing error is detected: sleep mode by means of the muting function.
– the FE bit is set by hardware Setting the RWU bit by software puts the SCI in
– Data is transferred from the Shift register to the sleep mode:
SCIDR register. All the reception status bits can not be set.
– No interrupt is generated. However this bit rises All the receive interrupts are inhibited.
at the same time as the RDRF bit which itself
generates an interrupt. A muted receiver may be awakened by one of the
following two ways:
The FE bit is reset by a SCISR register read oper-
ation followed by a SCIDR register read operation. – by Idle Line detection if the WAKE bit is reset,
[Link] Baud rate generation – by Address Mark detection if the WAKE bit is set.
The baud rate for the receiver and transmitter (Rx Receiver wakes-up by Idle Line detection when
and Tx) are set independently and calculated as the Receive line has recognised an Idle Frame.
follows: Then the RWU bit is reset by hardware but the
IDLE bit is not set.
fCPU fCPU
Tx = Rx = Receiver wakes-up by Address Mark detection
(16*PR)*TR (16*PR)*RR when it received a “1” as the most significant bit of
a word, thus indicating that the message is an ad-
with: dress. The reception of this particular word wakes
PR = 1, 3, 4 or 13 (see SCP[1:0] bits) up the receiver, resets the RWU bit and sets the
RDRF bit, which allows the receiver to receive this
TR = 1, 2, 4, 8, 16, 32, 64,128 word normally and to use it as an address word.
(see SCT[2:0] bits) Caution: In Mute mode, do not write to the
RR = 1, 2, 4, 8, 16, 32, 64,128 SCICR2 register. If the SCI is in Mute mode during
the read operation (RWU=1) and a address mark
(see SCR[2:0] bits) wake up event occurs (RWU is reset) before the
All these bits are in the SCIBRR register. write operation, the RWU bit will be set again by
Example: If fCPU is 8 MHz (normal mode) and if this write operation. Consequently the address
PR=13 and TR=RR=1, the transmit and receive byte is lost and the SCI is not woken up from Mute
baud rates are 38400 baud. mode.
Note: the baud rate registers MUST NOT be
changed while the transmitter or the receiver is en-
abled.

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[Link] Parity control even number of “1s” if even parity is selected
Parity control (generation of parity bit in transmis- (PS=0) or an odd number of “1s” if odd parity is se-
sion and parity checking in reception) can be ena- lected (PS=1). If the parity check fails, the PE flag
bled by setting the PCE bit in the SCICR1 register. is set in the SCISR register and an interrupt is gen-
Depending on the frame length defined by the M erated if PIE is set in the SCICR1 register.
bit, the possible SCI frame formats are as listed in [Link] SCI clock tolerance
Table 20. During reception, each bit is sampled 16 times.
Table 20. Frame formats The majority of the 8th, 9th and 10th samples is
considered as the bit value. For a valid bit detec-
M bit PCE bit SCI frame tion, all the three samples should have the same
0 0 | SB | 8 bit data | STB | value otherwise the noise flag (NF) is set. For ex-
0 1 | SB | 7-bit data | PB | STB | ample: if the 8th, 9th and 10th samples are 0, 1
and 1 respectively, then the bit value will be “1”,
1 0 | SB | 9-bit data | STB |
but the Noise flag bit is be set because the three
1 1 | SB | 8-bit data PB | STB | samples values are not the same.
Legend: SB = Start Bit, STB = Stop Bit,
Consequently, the bit length must be long enough
PB = Parity Bit
so that the 8th, 9th and 10th samples have the de-
Note: In case of wake up by an address mark, the sired bit value. This means the clock frequency
MSB bit of the data is taken into account and not should not vary more than 6/16 (37.5%) within one
the parity bit bit. The sampling clock is resynchronized at each
Even parity: the parity bit is calculated to obtain start bit, so that when receiving 10 bits (one start
an even number of “1s” inside the frame made of bit, 1 data byte, 1 stop bit), the clock deviation
the 7 or 8 LSB bits (depending on whether M is must not exceed 3.75%.
equal to 0 or 1) and the parity bit. Note: The internal sampling clock of the microcon-
Ex: data=00110101; 4 bits set => parity bit will be troller samples the pin value on every falling edge.
0 if even parity is selected (PS bit = 0). Therefore, the internal sampling clock and the time
the application expects the sampling to take place
Odd parity: the parity bit is calculated to obtain an may be out of sync. For example: If the baud rate
odd number of “1s” inside the frame made of the 7 is 15.625 kbaud (bit length is 64µs), then the 8th,
or 8 LSB bits (depending on whether M is equal to 9th and 10th samples will be at 28µs, 32µs & 36µs
0 or 1) and the parity bit. respectively (the first sample starting ideally at
Ex: data=00110101; 4 bits set => parity bit will be 0µs). But if the falling edge of the internal clock oc-
1 if odd parity is selected (PS bit = 1). curs just before the pin value changes, the sam-
Transmission mode: If the PCE bit is set then the ples would then be out of sync by ~4us. This
MSB bit of the data written in the data register is means the entire bit length must be at least 40µs
not transmitted but is changed by the parity bit. (36µs for the 10th sample + 4µs for synchroniza-
tion with the internal sampling clock).
Reception mode: If the PCE bit is set then the in-
terface checks if the received data byte has an

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[Link] Clock deviation causes [Link] Noise error causes
The causes which contribute to the total deviation See also description of Noise error in Section
are: [Link].
– DTRA: Deviation due to transmitter error (Local Start bit
oscillator error of the transmitter or the trans- The noise flag (NF) is set during start bit reception
mitter is transmitting at a different baud rate). if one of the following conditions occurs:
– DQUANT: Error due to the baud rate quantisa- 1. A valid falling edge is not detected. A falling
tion of the receiver. edge is considered to be valid if the 3 consecu-
– DREC: Deviation of the local oscillator of the tive samples before the falling edge occurs are
receiver: This deviation can occur during the detected as '1' and, after the falling edge
reception of one complete SCI message as- occurs, during the sampling of the 16 samples,
suming that the deviation has been compen- if one of the samples numbered 3, 5 or 7 is
sated at the beginning of the message. detected as a “1”.
– DTCL: Deviation due to the transmission line 2. During sampling of the 16 samples, if one of the
(generally due to the transceivers) samples numbered 8, 9 or 10 is detected as a
All the deviations of the system should be added “1”.
and compared to the SCI clock tolerance: Therefore, a valid Start Bit must satisfy both the
DTRA + DQUANT + DREC + DTCL < 3.75% above conditions to prevent the Noise flag getting
set.
Data bits
The noise flag (NF) is set during normal data bit re-
ception if the following condition occurs:
– During the sampling of 16 samples, if all three
samples numbered 8, 9 and10 are not the same.
The majority of the 8th, 9th and 10th samples is
considered as the bit value.
Therefore, a valid Data Bit must have samples 8, 9
and 10 at the same value to prevent the Noise flag
getting set.

Figure 40. Bit sampling in reception mode

RDI LINE

sampled values
Sample
clock 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

6/16

7/16 7/16
One bit time

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12.3.5 Low power modes Enable Exit Exit
Event
Interrupt event control from from
Mode Description flag
bit Wait Halt
No effect on SCI. Transmit Data Register
Wait TDRE TIE Yes No
SCI interrupts cause the device to exit Empty
from Wait mode. Transmission Com-
TC TCIE Yes No
SCI registers are frozen. plete
Received Data Ready
In Halt mode, the SCI stops transmit- RDRF Yes No
Halt to be Read RIE
ting/receiving until Halt mode is exit-
Overrun Error Detected OR Yes No
ed.
Idle Line Detected IDLE ILIE Yes No
12.3.6 Interrupts Parity Error PE PIE Yes No
The SCI interrupt events are connected to the rupt mask in the CC register is reset (RIM instruc-
same interrupt vector. tion).
These events generate an interrupt if the corre-
sponding Enable Control Bit is set and the inter-

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12.3.7 Register description Note: The IDLE bit will not be set again until the
Status Register (SCISR) RDRF bit has been set itself (i.e. a new idle line oc-
Read Only curs).
Reset value: 1100 0000 (C0h)
7 0 Bit 3 = OR Overrun error.
This bit is set by hardware when the word currently
being received in the shift register is ready to be
TDRE TC RDRF IDLE OR NF FE PE
transferred into the RDR register while RDRF=1.
An interrupt is generated if RIE=1 in the SCICR2
Bit 7 = TDRE Transmit data register empty. register. It is cleared by a software sequence (an
This bit is set by hardware when the content of the access to the SCISR register followed by a read to
TDR register has been transferred into the shift the SCIDR register).
register. An interrupt is generated if the TIE bit=1 0: No Overrun error
in the SCICR2 register. It is cleared by a software 1: Overrun error is detected
sequence (an access to the SCISR register fol- Note: When this bit is set RDR register content will
lowed by a write to the SCIDR register). not be lost but the shift register will be overwritten.
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Note: Data will not be transferred to the shift reg- Bit 2 = NF Noise flag.
ister unless the TDRE bit is cleared. This bit is set by hardware when noise is detected
on a received frame. It is cleared by a software se-
quence (an access to the SCISR register followed
Bit 6 = TC Transmission complete. by a read to the SCIDR register).
This bit is set by hardware when transmission of a 0: No noise is detected
frame containing Data is complete. An interrupt is 1: Noise is detected
generated if TCIE=1 in the SCICR2 register. It is Note: This bit does not generate interrupt as it ap-
cleared by a software sequence (an access to the pears at the same time as the RDRF bit which it-
SCISR register followed by a write to the SCIDR self generates an interrupt.
register).
0: Transmission is not complete
1: Transmission is complete Bit 1 = FE Framing error.
Note: TC is not set after the transmission of a Pre- This bit is set by hardware when a de-synchroniza-
amble or a Break. tion, excessive noise or a break character is de-
tected. It is cleared by a software sequence (an
access to the SCISR register followed by a read to
Bit 5 = RDRF Received data ready flag. the SCIDR register).
This bit is set by hardware when the content of the 0: No Framing error is detected
RDR register has been transferred to the SCIDR 1: Framing error or break character is detected
register. An interrupt is generated if RIE=1 in the
SCICR2 register. It is cleared by a software se- Note: This bit does not generate interrupt as it ap-
quence (an access to the SCISR register followed pears at the same time as the RDRF bit which it-
by a read to the SCIDR register). self generates an interrupt. If the word currently
0: Data is not received being transferred causes both frame error and
1: Received data is ready to be read overrun error, it will be transferred and only the OR
bit will be set.
Bit 4 = IDLE Idle line detect.
This bit is set by hardware when a Idle Line is de- Bit 0 = PE Parity error.
tected. An interrupt is generated if the ILIE=1 in This bit is set by hardware when a parity error oc-
the SCICR2 register. It is cleared by a software se- curs in receiver mode. It is cleared by a software
quence (an access to the SCISR register followed sequence (a read to the status register followed by
by a read to the SCIDR register). an access to the SCIDR data register). An inter-
0: No Idle Line is detected rupt is generated if PIE=1 in the SCICR1 register.
1: Idle Line is detected 0: No parity error
1: Parity error

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Control Register 1 (SCICR1)
Read/Write Bit 3 = WAKE Wake-Up method.
Reset value: x000 0000 (x0h) This bit determines the SCI Wake-Up method, it is
set or cleared by software.
7 0 0: Idle Line
1: Address Mark
R8 T8 SCID M WAKE PCE PS PIE

Bit 2 = PCE Parity control enable.

Bit 7 = R8 Receive data bit 8. This bit selects the hardware parity control (gener-
This bit is used to store the 9th bit of the received ation and detection). When the parity control is en-
word when M=1. abled, the computed parity is inserted at the MSB
position (9th bit if M=1; 8th bit if M=0) and parity is
checked on the received data. This bit is set and
Bit 6 = T8 Transmit data bit 8. cleared by software. Once it is set, PCE is active
This bit is used to store the 9th bit of the transmit- after the current byte (in reception and in transmis-
ted word when M=1. sion).
0: Parity control disabled
1: Parity control enabled
Bit 5 = SCID Disabled for low power consumption
When this bit is set the SCI prescalers and outputs
are stopped and the end of the current byte trans- Bit 1 = PS Parity selection.
fer in order to reduce power [Link] bit This bit selects the odd or even parity when the
is set and cleared by software. parity generation/detection is enabled (PCE bit
0: SCI enabled set). It is set and cleared by software. The parity
1: SCI prescaler and outputs disabled will be selected after the current byte.
0: Even parity
1: Odd parity
Bit 4 = M Word length.
This bit determines the word length. It is set or
cleared by software. Bit 0 = PIE Parity interrupt enable.
0: 1 Start bit, 8 Data bits, 1 Stop bit This bit enables the interrupt capability of the hard-
1: 1 Start bit, 9 Data bits, 1 Stop bit ware parity control when a parity error is detected
(PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
Note: The M bit must not be modified during a data
1: Parity error interrupt enabled.
transfer (both transmission and reception).

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Serial communication interface (Cont’d)

Control Register 2 (SCICR2) Notes:
Read/Write – During transmission, a “0” pulse on the TE bit
Reset value: 0000 0000 (00h) (“0” followed by “1”) sends a preamble (idle line)
after the current word.
7 0 – When TE is set there is a 1 bit-time delay before
the transmission starts.
TIE TCIE RIE ILIE TE RE RWU SBK
Caution: The TDO pin is free for general purpose
I/O only when the TE and RE bits are both cleared
Bit 7 = TIE Transmitter interrupt enable. (or if TE is never set).
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever Bit 2 = RE Receiver enable.
TDRE=1 in the SCISR register This bit enables the receiver. It is set and cleared
by software.
0: Receiver is disabled
Bit 6 = TCIE Transmission complete interrupt ena- 1: Receiver is enabled and begins searching for a
ble start bit
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC=1 in Bit 1 = RWU Receiver wake-up.
the SCISR register This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
Bit 5 = RIE Receiver interrupt enable. recognized.
This bit is set and cleared by software. 0: Receiver in Active mode
0: Interrupt is inhibited 1: Receiver in Mute mode
1: An SCI interrupt is generated whenever OR=1
or RDRF=1 in the SCISR register Note: Before selecting Mute mode (setting the
RWU bit), the SCI must receive some data first,
otherwise it cannot function in Mute mode with
Bit 4 = ILIE Idle line interrupt enable. wakeup by idle line detection.
This bit is set and cleared by software.
0: Interrupt is inhibited Bit 0 = SBK Send break.
1: An SCI interrupt is generated whenever IDLE=1 This bit set is used to send break characters. It is
in the SCISR register. set and cleared by software.
0: No break character is transmitted
Bit 3 = TE Transmitter enable. 1: Break characters are transmitted
This bit enables the transmitter. It is set and Note: If the SBK bit is set to “1” and then to “0”, the
cleared by software. transmitter will send a BREAK word at the end of
0: Transmitter is disabled the current word.
1: Transmitter is enabled

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Serial communication interface (Cont’d)

Data Register (SCIDR) PR prescaling factor SCP1 SCP0
Read/Write 4 1 0
Reset value: Undefined 13 1 1
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ- Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
ten to. These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
7 0
clock to yield the transmit rate clock.
DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 TR dividing factor SCT2 SCT1 SCT0
1 0 0 0
The Data register performs a double function (read 2 0 0 1
and write) since it is composed of two registers, 4 0 1 0
one for transmission (TDR) and one for reception
(RDR). 8 0 1 1
The TDR register provides the parallel interface 16 1 0 0
between the internal bus and the output shift reg- 32 1 0 1
ister (see Figure 38).
64 1 1 0
The RDR register provides the parallel interface
between the input shift register and the internal 128 1 1 1
bus (see Figure 38).
Bits 2:0 = SCR[2:0] SCI Receiver rate divisor.
Baud Rate Register (SCIBRR) These 3 bits, in conjunction with the SCP[1:0] bits
define the total division applied to the bus clock to
Read/Write yield the receive rate clock.
Reset value: 0000 0000 (00h)
RR dividing factor SCR2 SCR1 SCR0
7 0 1 0 0 0
2 0 0 1
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
4 0 1 0
8 0 1 1
Bits 7:6= SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard 16 1 0 0
clock division ranges: 32 1 0 1
64 1 1 0
PR prescaling factor SCP1 SCP0
128 1 1 1
1 0 0
3 0 1

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Table 21. SCI register map and reset values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
20 SCISR TDRE TC RDRF IDLE OR NF FE PE
Reset value 1 1 0 0 0 0 0 0
21 SCIDR DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
Reset value x x x x x x x x
22 SCIBRR SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
Reset value 0 0 x x x x x x
23 SCICR1 R8 T8 SCID M WAKE PCE PS PIE
Reset value x x 0 x x 0 0 0
24 SCICR2 TIE TCIE RIE ILIE TE RE RWU SBK
Reset value 0 0 0 0 0 0 0 0

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12.4 USB interface (USB)

12.4.1 Introduction For general information on the USB, refer to the
The USB Interface implements a low-speed func- “Universal Serial Bus Specifications” document
tion interface between the USB and the ST7 mi- available at http//:[Link].
crocontroller. It is a highly integrated circuit which Serial interface engine
includes the transceiver, 3.3 voltage regulator, SIE The SIE (serial interface engine) interfaces with
and DMA. No external components are needed the USB, via the transceiver.
apart from the external pull-up on USBDM for low
speed recognition by the USB host. The use of The SIE processes tokens, handles data transmis-
DMA architecture allows the endpoint definition to sion/reception, and handshaking as required by
be completely flexible. Endpoints can be config- the USB standard. It also performs frame format-
ured by software as in or out. ting, including CRC generation and checking.
12.4.2 Main features Endpoints
■ USB Specification Version 1.1 Compliant The Endpoint registers indicate if the microcontrol-
■ Supports Low-Speed USB Protocol
ler is ready to transmit/receive, and how many
bytes need to be transmitted.
■ Two or Three Endpoints (including default one)
depending on the device (see device feature list DMA
and register map) When a token for a valid Endpoint is recognized by
■ CRC generation/checking, NRZI encoding/ the USB interface, the related data transfer takes
decoding and bit-stuffing place, using DMA. At the end of the transaction, an
interrupt is generated.
■ USB Suspend/Resume operations

■ DMA Data transfers

Interrupts
■ On-Chip 3.3V Regulator
By reading the Interrupt Status register, applica-
tion software can know which USB event has oc-
■ On-Chip USB Transceiver
curred.
12.4.3 Functional description
The block diagram in Figure 41, gives an overview
of the USB interface hardware.
Figure 41. USB block diagram
6 MHz

ENDPOINT
REGISTERS CPU

USBDM
Transceiver Address,
SIE DMA
USBDP data buses
and interrupts

3.3V
USBVCC Voltage INTERRUPT
Regulator REGISTERS MEMORY

USBGND

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USB interface (Cont’d)

12.4.4 Register description Interrupt/DMA register (IDR)
DMA address register (DMAR) Read / Write
Read / Write Reset value: xxxx 0000 (x0h)
Reset value: Undefined
7 0
7 0
DA7 DA6 EP1 EP0 CNT3 CNT2 CNT1 CNT0
DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8

Bits 7:6 = DA[7:6] DMA address bits 7-6.

Bits 7:0=DA[15:8] DMA address bits 15-8. Software must reset these bits. See the descrip-
Software must write the start address of the DMA tion of the DMAR register and Figure 42.
memory area whose most significant bits are given
by DA15-DA6. The remaining 6 address bits are Bits 5:4 = EP[1:0] Endpoint number (read-only).
set by hardware. See the description of the IDR These bits identify the endpoint which required at-
register and Figure 42. tention.
00: Endpoint 0
01: Endpoint 1
10: Endpoint 2
When a CTR interrupt occurs (see register ISTR)
the software should read the EP bits to identify the
endpoint which has sent or received a packet.

Bits 3:0 = CNT[3:0] Byte count (read only).

This field shows how many data bytes have been
received during the last data reception.
Note: Not valid for data transmission.
Figure 42. DMA buffers

101111
Endpoint 2 TX
101000
100111
Endpoint 2 RX
100000
011111
Endpoint 1 TX
011000
010111
Endpoint 1 RX
010000
001111
Endpoint 0 TX
001000
000111
Endpoint 0 RX
DA15-6,000000 000000

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USB interface (Cont’d)

PID Register (PIDR) INTERRUPT Status Register (ISTR)
Read only Read / Write
Reset value: xx00 0000 (x0h) Reset value: 0000 0000 (00h)

7 0 7 0

RX_ SUSP DOVR CTR ERR IOVR ESUSP RESET SOF

TP3 TP2 0 0 0 RXD 0
SEZ

When an interrupt occurs these bits are set by

Bits 7:6 = TP[3:2] Token PID bits 3 & 2. hardware. Software must read them to determine
USB token PIDs are encoded in four bits. TP[3:2] the interrupt type and clear them after servicing.
correspond to the variable token PID bits 3 & 2. Note: These bits cannot be set by software.
Note: PID bits 1 & 0 have a fixed value of 01.
When a CTR interrupt occurs (see register ISTR)
the software should read the TP3 and TP2 bits to Bit 7 = SUSP Suspend mode request.
retrieve the PID name of the token received. This bit is set by hardware when a constant idle
The USB standard defines TP bits as: state is present on the bus line for more than 3 ms,
indicating a suspend mode request from the USB
TP3 TP2 PID Name bus. The suspend request check is active immedi-
0 0 OUT ately after each USB reset event and its disabled
1 0 IN by hardware when suspend mode is forced
(FSUSP bit of CTLR register) until the end of
1 1 SETUP
resume sequence.
Bits 5:3 Reserved. Forced by hardware to 0.
Bit 6 = DOVR DMA over/underrun.
This bit is set by hardware if the ST7 processor
Bit 2 = RX_SEZ Received single-ended zero can’t answer a DMA request in time.
This bit indicates the status of the RX_SEZ trans- 0: No over/underrun detected
ceiver output. 1: Over/underrun detected
0: No SE0 (single-ended zero) state
1: USB lines are in SE0 (single-ended zero) state
Bit 5 = CTR Correct Transfer. This bit is set by
hardware when a correct transfer operation is per-
Bit 1 = RXD Received data formed. The type of transfer can be determined by
0: No K-state looking at bits TP3-TP2 in register PIDR. The End-
1: USB lines are in K-state point on which the transfer was made is identified
This bit indicates the status of the RXD transceiver by bits EP1-EP0 in register IDR.
output (differential receiver output). 0: No Correct Transfer detected
Note: If the environment is noisy, the RX_SEZ and 1: Correct Transfer detected
RXD bits can be used to secure the application. By Note: A transfer where the device sent a NAK or
interpreting the status, software can distinguish a STALL handshake is considered not correct (the
valid End Suspend event from a spurious wake-up host only sends ACK handshakes). A transfer is
due to noise on the external USB line. A valid End considered correct if there are no errors in the PID
Suspend is followed by a Resume or Reset se- and CRC fields, if the DATA0/DATA1 PID is sent
quence. A Resume is indicated by RXD=1, a Re- as expected, if there were no data overruns, bit
set is indicated by RX_SEZ=1. stuffing or framing errors.

Bit 0 = Reserved. Forced by hardware to 0. Bit 4 = ERR Error.

This bit is set by hardware whenever one of the er-
rors listed below has occurred:
0: No error detected
1: Timeout, CRC, bit stuffing or nonstandard
framing error detected

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USB interface (Cont’d)

Bit 3 = IOVR Interrupt overrun. of each bit, please refer to the corresponding bit
This bit is set when hardware tries to set ERR, or description in ISTR.
SOF before they have been cleared by software.
0: No overrun detected
1: Overrun detected Control Register (CTLR)
Read / Write
Bit 2 = ESUSP End suspend mode. Reset value: 0000 0110 (06h)
This bit is set by hardware when, during suspend
mode, activity is detected that wakes the USB in- 7 0
terface up from suspend mode.
0 0 0 0 RESUME PDWN FSUSP FRES
This interrupt is serviced by a specific vector, in or-
der to wake up the ST7 from Halt mode.
0: No End Suspend detected Bits 7:4 = Reserved. Forced by hardware to 0.
1: End Suspend detected

Bit 3 = RESUME Resume.

Bit 1 = RESET USB reset. This bit is set by software to wake-up the Host
This bit is set by hardware when the USB reset se- when the ST7 is in suspend mode.
quence is detected on the bus. 0: Resume signal not forced
0: No USB reset signal detected 1: Resume signal forced on the USB bus.
1: USB reset signal detected
Software should clear this bit after the appropriate
Note: The DADDR, EP0RA, EP0RB, EP1RA, delay.
EP1RB, EP2RA and EP2RB registers are reset by
a USB reset.
Bit 2 = PDWN Power down.
This bit is set by software to turn off the 3.3V on-
Bit 0 = SOF Start of frame. chip voltage regulator that supplies the external
This bit is set by hardware when a low-speed SOF pull-up resistor and the transceiver.
indication (keep-alive strobe) is seen on the USB 0: Voltage regulator on
bus. It is also issued at the end of a resume se- 1: Voltage regulator off
quence.
0: No SOF signal detected Note: After turning on the voltage regulator, soft-
1: SOF signal detected ware should allow at least 3 µs for stabilisation of
the power supply before using the USB interface.
Note: To avoid spurious clearing of some bits, it is
recommended to clear them using a load instruc-
tion where all bits which must not be altered are Bit 1 = FSUSP Force suspend mode.
set, and all bits to be cleared are reset. Avoid read- This bit is set by software to enter Suspend mode.
modify-write instructions like AND , XOR.. The ST7 should also be halted allowing at least
600 ns before issuing the HALT instruction.
0: Suspend mode inactive
Interrupt Mask Register (IMR) 1: Suspend mode active
Read / Write When the hardware detects USB activity, it resets
Reset value: 0000 0000 (00h) this bit (it can also be reset by software).

7 0
Bit 0 = FRES Force reset.
SUS DOV CTR ERR IOVR ESU RES SOF
This bit is set by software to force a reset of the
PM RM M M M SPM ETM M
USB interface, just as if a RESET sequence came
from the USB.
0: Reset not forced
Bits 7:0 = These bits are mask bits for all interrupt 1: USB interface reset forced.
condition bits included in the ISTR. Whenever one The USB is held in RESET state until software
of the IMR bits is set, if the corresponding ISTR bit clears this bit, at which point a “USB-RESET” in-
is set, and the I bit in the CC register is cleared, an terrupt will be generated if enabled.
interrupt request is generated. For an explanation

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USB interface (Cont’d)

Device Address Register (DADDR) Bit 6 = DTOG_TX Data Toggle, for transmission
Read / Write transfers.
It contains the required value of the toggle bit
Reset value: 0000 0000 (00h) (0=DATA0, 1=DATA1) for the next transmitted
data packet. This bit is set by hardware at the re-
7 0 ception of a SETUP PID. DTOG_TX toggles only
when the transmitter has received the ACK signal
0 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 from the USB host. DTOG_TX and also
DTOG_RX (see EPnRB) are normally updated by
hardware, at the receipt of a relevant PID. They
Bit 7 = Reserved. Forced by hardware to 0. can be also written by software.

Bits 6:0 = ADD[6:0] Device address, 7 bits. Bits 5:4 = STAT_TX[1:0] Status bits, for transmis-
Software must write into this register the address sion transfers.
sent by the host during enumeration. These bits contain the information about the end-
Note: This register is also reset when a USB reset point status, which are listed below:
is received from the USB bus or forced through bit STAT_TX1 STAT_TX0 Meaning
FRES in the CTLR register. DISABLED: transmission
0 0
transfers cannot be executed.
Endpoint n Register A (EPnRA) STALL: the endpoint is stalled
0 1 and all transmission requests
Read / Write result in a STALL handshake.
Reset value: 0000 xxxx (0xh) NAK: the endpoint is naked
1 0 and all transmission requests
7 0 result in a NAK handshake.
VALID: this endpoint is ena-
ST_ DTOG STAT STAT TBC TBC TBC TBC 1 1
bled for transmission.
OUT _TX _TX1 _TX0 3 2 1 0

These bits are written by software. Hardware sets

These registers (EP0RA, EP1RA and EP2RA) are the STAT_TX bits to NAK when a correct transfer
used for controlling data transmission. They are has occurred (CTR=1) related to a IN or SETUP
also reset by the USB bus reset. transaction addressed to this endpoint; this allows
the software to prepare the next set of data to be
Note: Endpoint 2 and the EP2RA register are not transmitted.
available on some devices (see device feature list
and register map).
Bits 3:0 = TBC[3:0] Transmit byte count for End-
point n.
Bit 7 = ST_OUT Status out. Before transmission, after filling the transmit buff-
This bit is set by software to indicate that a status er, software must write in the TBC field the trans-
out packet is expected: in this case, all nonzero mit packet size expressed in bytes (in the range 0-
OUT data transfers on the endpoint are STALLed 8).
instead of being ACKed. When ST_OUT is reset,
OUT transactions can have any number of bytes, Warning: Any value outside the range 0-8 will-
as needed. induce undesired effects (such as continuous data
transmission).

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USB INTERFACE (Cont’d)

Endpoint n Register B (EPnRB) STAT_RX1 STAT_RX0 Meaning
Read / Write NAK: the endpoint is na-
Reset value: 0000 xxxx (0xh) ked and all reception re-
1 0
quests result in a NAK
handshake.
7 0
VALID: this endpoint is
1 1
DTOG STAT STAT enabled for reception.
CTRL EA3 EA2 EA1 EA0
_RX _RX1 _RX0
These bits are written by software. Hardware sets
the STAT_RX bits to NAK when a correct transfer
These registers (EP1RB and EP2RB) are used for has occurred (CTR=1) related to an OUT or SET-
controlling data reception on Endpoints 1 and 2. UP transaction addressed to this endpoint, so the
They are also reset by the USB bus reset. software has the time to elaborate the received
data before acknowledging a new transaction.
Note: Endpoint 2 and the EP2RB register are not
available on some devices (see device feature list
and register map). Bits 3:0 = EA[3:0] Endpoint address.
Software must write in this field the 4-bit address
used to identify the transactions directed to this
Bit 7 = CTRL Control.
endpoint. Usually EP1RB contains “0001” and
This bit should be 0.
EP2RB contains “0010”.
Note: If this bit is 1, the Endpoint is a control end-
point. (Endpoint 0 is always a control Endpoint, but
it is possible to have more than one control End- Endpoint 0 Register B (EP0RB)
point). Read / Write
Reset value: 1000 0000 (80h)
Bit 6 = DTOG_RX Data toggle, for reception trans-
fers. 7 0
It contains the expected value of the toggle bit
(0=DATA0, 1=DATA1) for the next data packet. 1
DTOG STAT STAT
0 0 0 0
This bit is cleared by hardware in the first stage RX RX1 RX0
(Setup Stage) of a control transfer (SETUP trans-
actions start always with DATA0 PID). The receiv-
er toggles DTOG_RX only if it receives a correct This register is used for controlling data reception
data packet and the packet’s data PID matches on Endpoint 0. It is also reset by the USB bus re-
the receiver sequence bit. set.

Bits 5:4 = STAT_RX [1:0] Status bits, for reception Bit 7 = Forced by hardware to 1.
transfers.
These bits contain the information about the end- Bits 6:4 = Refer to the EPnRB register for a de-
point status, which are listed below: scription of these bits.
STAT_RX1 STAT_RX0 Meaning
DISABLED: reception Bits 3:0 = Forced by hardware to 0.
0 0 transfers cannot be exe-
cuted.
STALL: the endpoint is
stalled and all reception
0 1
requests result in a
STALL handshake.

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USB interface (Cont’d)

12.4.5 Programming considerations tively) must not be modified by software, as the
The interaction between the USB interface and the hardware can change their value on the fly.
application program is described below. Apart When the operation is completed, they can be ac-
from system reset, action is always initiated by the cessed again to enable a new operation.
USB interface, driven by one of the USB events [Link] Interrupt handling
associated with the Interrupt Status Register (IS-
TR) bits. Start of Frame (SOF)
[Link] Initializing the registers The interrupt service routine may monitor the SOF
events for a 1 ms synchronization event to the
At system reset, the software must initialize all reg- USB bus. This interrupt is generated at the end of
isters to enable the USB interface to properly gen- a resume sequence and can also be used to de-
erate interrupts and DMA requests. tect this event.
1. Initialize the DMAR, IDR, and IMR registers USB Reset (RESET)
(choice of enabled interrupts, address of DMA
buffers). Refer the paragraph titled initializing When this event occurs, the DADDR register is re-
the DMA Buffers. set, and communication is disabled in all endpoint
registers (the USB interface will not respond to any
2. Initialize the EP0RA and EP0RB registers to packet). Software is responsible for reenabling
enable accesses to address 0 and endpoint 0 endpoint 0 within 10 ms of the end of reset. To do
to support USB enumeration. Refer to the para- this, set the STAT_RX bits in the EP0RB register
graph titled Endpoint Initialization. to VALID.
3. When addresses are received through this Suspend (SUSP)
channel, update the content of the DADDR.
The CPU is warned about the lack of bus activity
4. If needed, write the endpoint numbers in the EA for more than 3 ms, which is a suspend request.
fields in the EP1RB and EP2RB register. The software should set the USB interface to sus-
[Link] Initializing DMA buffers pend mode and execute an ST7 HALT instruction
The DMA buffers are a contiguous zone of memo- to meet the USB-specified power constraints.
ry whose maximum size is 48 bytes. They can be End Suspend (ESUSP)
placed anywhere in the memory space to enable The CPU is alerted by activity on the USB, which
the reception of messages. The 10 most signifi- causes an ESUSP interrupt. The ST7 automatical-
cant bits of the start of this memory area are spec- ly terminates Halt mode.
ified by bits DA15-DA6 in registers DMAR and
IDR, the remaining bits are 0. The memory map is Correct Transfer (CTR)
shown in Figure 42. 1. When this event occurs, the hardware automat-
Each buffer is filled starting from the bottom (last 3 ically sets the STAT_TX or STAT_RX to NAK.
address bits=000) up. Note: Every valid endpoint is NAKed until soft-
ware clears the CTR bit in the ISTR register,
[Link] Endpoint initialization independently of the endpoint number
To be ready to receive: addressed by the transfer which generated the
Set STAT_RX to VALID (11b) in EP0RB to enable CTR interrupt.
reception. Note: If the event triggering the CTR interrupt is
a SETUP transaction, both STAT_TX and
To be ready to transmit: STAT_RX are set to NAK.
1. Write the data in the DMA transmit buffer. 2. Read the PIDR to obtain the token and the IDR
2. In register EPnRA, specify the number of bytes to get the endpoint number related to the last
to be transmitted in the TBC field transfer.
3. Enable the endpoint by setting the STAT_TX Note: When a CTR interrupt occurs, the TP3-
bits to VALID (11b) in EPnRA. TP2 bits in the PIDR register and EP1-EP0 bits
in the IDR register stay unchanged until the
Note: Once transmission and/or reception are en- CTR bit in the ISTR register is cleared.
abled, registers EPnRA and/or EPnRB (respec-
3. Clear the CTR bit in the ISTR register.

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USB interface (Cont’d)

Table 22. USB register map and reset values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Name
PIDR TP3 TP2 0 0 0 RX_SEZ RXD 0
25
Reset value x x 0 0 0 0 0 0
DMAR DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8
26
Reset value x x x x x x x x
IDR DA7 DA6 EP1 EP0 CNT3 CNT2 CNT1 CNT0
27
Reset value x x x x 0 0 0 0
ISTR SUSP DOVR CTR ERR IOVR ESUSP RESET SOF
28
Reset value 0 0 0 0 0 0 0 0
IMR SUSPM DOVRM CTRM ERRM IOVRM ESUSPM RESETM SOFM
29
Reset value 0 0 0 0 0 0 0 0
CTLR 0 0 0 0 RESUME PDWN FSUSP FRES
2A
Reset value 0 0 0 0 0 1 1 0
DADDR 0 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
2B
Reset value 0 0 0 0 0 0 0 0
EP0RA ST_OUT DTOG_TX STAT_TX1 STAT_TX0 TBC3 TBC2 TBC1 TBC0
2C
Reset value 0 0 0 0 x x x x
EP0RB 1 DTOG_RX STAT_RX1 STAT_RX0 0 0 0 0
2D
Reset value 1 0 0 0 0 0 0 0
EP1RA ST_OUT DTOG_TX STAT_TX1 STAT_TX0 TBC3 TBC2 TBC1 TBC0
2E
Reset value 0 0 0 0 x x x x
EP1RB CTRL DTOG_RX STAT_RX1 STAT_RX0 EA3 EA2 EA1 EA0
2F
Reset value 0 0 0 0 x x x x
EP2RA ST_OUT DTOG_TX STAT_TX1 STAT_TX0 TBC3 TBC2 TBC1 TBC0
30
Reset value 0 0 0 0 x x x x
EP2RB CTRL DTOG_RX STAT_RX1 STAT_RX0 EA3 EA2 EA1 EA0
31
Reset value 0 0 0 0 x x x x

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12.5 I²C bus interface (I²C)

12.5.1 Introduction handshake. The interrupts are enabled or disabled
The I²C Bus Interface serves as an interface be- by software. The interface is connected to the I²C
tween the microcontroller and the serial I²C bus. It bus by a data pin (SDAI) and by a clock pin (SCLI).
provides both multimaster and slave functions, It can be connected both with a standard I²C bus
and controls all I²C bus-specific sequencing, pro- and a Fast I²C bus. This selection is made by soft-
tocol, arbitration and timing. It supports fast I²C ware.
mode (400 kHz). Mode selection
12.5.2 Main features The interface can operate in the four following
■ Parallel-bus/I²C protocol converter modes:
■ Multi-master capability – Slave transmitter/receiver
■ 7-bit Addressing – Master transmitter/receiver
■ Transmitter/Receiver flag By default, it operates in slave mode.
■ End-of-byte transmission flag The interface automatically switches from slave to
■ Transfer problem detection master after it generates a START condition and
from master to slave in case of arbitration loss or a
I²C master features:
STOP generation, allowing then Multi-Master ca-
■ Clock generation pability.
■ I²C bus busy flag
Communication flow
■ Arbitration Lost flag
In Master mode, it initiates a data transfer and
■ End of byte transmission flag generates the clock signal. A serial data transfer
■ Transmitter/Receiver flag always begins with a start condition and ends with
■ Start bit detection flag
a stop condition. Both start and stop conditions are
generated in master mode by software.
■ Start and Stop generation
In Slave mode, the interface is capable of recog-
I²C slave features: nising its own address (7-bit), and the General Call
■ Stop bit detection address. The General Call address detection may
■ I²C bus busy flag be enabled or disabled by software.
■ Detection of misplaced start or stop condition Data and addresses are transferred as 8-bit bytes,
■ Programmable I²C Address detection
MSB first. The first byte following the start condi-
tion is the address byte; it is always transmitted in
■ Transfer problem detection
Master mode.
■ End-of-byte transmission flag
A 9th clock pulse follows the 8 clock cycles of a
■ Transmitter/Receiver flag byte transfer, during which the receiver must send
12.5.3 General description an acknowledge bit to the transmitter. Refer to Fig-
ure 43.
In addition to receiving and transmitting data, this
interface converts it from serial to parallel format
and vice versa, using either an interrupt or polled
Figure 43. I²C bus protocol

SDA
MSB ACK

SCL
1 2 8 9

START STOP
CONDITION CONDITION
VR02119B

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I²C bus interface (Cont’d)

Acknowledge may be enabled and disabled by The SCL frequency (FSCL) is controlled by a pro-
software. grammable clock divider which depends on the I²C
The I²C interface address and/or general call ad- bus mode.
dress can be selected by software. When the I²C cell is enabled, the SDA and SCL
The speed of the I²C interface may be selected be- ports must be configured as floating inputs. In this
tween Standard (up to 100kHz) and Fast I²C (up to case, the value of the external pull-up resistor
400kHz). used depends on the application.
When the I²C cell is disabled, the SDA and SCL
ports revert to being standard I/O port pins.
SDA/SCL Line Control
Transmitter mode: the interface holds the clock
line low before transmission to wait for the micro-
controller to write the byte in the Data Register.
Receiver mode: the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
Figure 44. I²C Interface block diagram
DATA REGISTER (DR)

SDA or SDAI DATA CONTROL

DATA SHIFT REGISTER

COMPARATOR

OWN ADDRESS REGISTER (OAR)

SCL or SCLI CLOCK CONTROL

CLOCK CONTROL REGISTER (CCR)

CONTROL REGISTER (CR)

STATUS REGISTER 1 (SR1) CONTROL LOGIC

STATUS REGISTER 2 (SR2)

INTERRUPT

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I²C bus interface (Cont’d)

12.5.4 Functional description The slave waits for a read of the SR1 register fol-
Refer to the CR, SR1 and SR2 registers in Section lowed by a write in the DR register, holding the
12.5.7. for the bit definitions. SCL line low (see Figure 45 Transfer sequencing
EV3).
By default the I²C interface operates in Slave
mode (M/SL bit is cleared) except when it initiates When the acknowledge pulse is received:
a transmit or receive sequence. – The EVF and BTF bits are set by hardware with
an interrupt if the ITE bit is set.
[Link] Slave mode
As soon as a start condition is detected, the Closing slave communication
address is received from the SDA line and sent to After the last data byte is transferred a Stop Con-
the shift register; then it is compared with the dition is generated by the master. The interface
address of the interface or the General Call detects this condition and sets:
address (if selected by software). – EVF and STOPF bits with an interrupt if the ITE
Address not matched: the interface ignores it bit is set.
and waits for another Start condition. Then the interface waits for a read of the SR2 reg-
Address matched: the interface generates in se- ister (see Figure 45 Transfer sequencing EV4).
quence:
– Acknowledge pulse if the ACK bit is set. Error cases
– EVF and ADSL bits are set with an interrupt if the – BERR: Detection of a Stop or a Start condition
ITE bit is set. during a byte transfer. In this case, the EVF and
Then the interface waits for a read of the SR1 reg- the BERR bits are set with an interrupt if the ITE
ister, holding the SCL line low (see Figure 45 bit is set.
Transfer sequencing EV1). If it is a Stop, then the interface discards the data,
Next, software must read the DR register to deter- released the lines and waits for another Start
mine from the least significant bit (Data Direction condition.
Bit) if the slave must enter Receiver or Transmitter If it is a Start, then the interface discards the data
mode. and waits for the next slave address on the bus.
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set with an inter-
Slave receiver rupt if the ITE bit is set.
Following the address reception and after SR1 The AF bit is cleared by reading the I2CSR2 reg-
register has been read, the slave receives bytes ister. However, if read before the completion of
from the SDA line into the DR register via the inter- the transmission, the AF flag will be set again,
nal shift register. After each byte the interface gen- thus possibly generating a new interrupt. Soft-
erates in sequence: ware must ensure either that the SCL line is back
– Acknowledge pulse if the ACK bit is set at 0 before reading the SR2 register, or be able
to correctly handle a second interrupt during the
– EVF and BTF bits are set with an interrupt if the 9th pulse of a transmitted byte.
ITE bit is set.
Note: In case of errors, SCL line is not held low;
Then the interface waits for a read of the SR1 reg- however, the SDA line can remain low if the last
ister followed by a read of the DR register, holding bits transmitted are all 0. While AF=1, the SCL line
the SCL line low (see Figure 45 Transfer se- may be held low due to SB or BTF flags that are
quencing EV2). set at the same time. It is then necessary to re-
lease both lines by software.
Slave transmitter
Following the address reception and after the SR1 How to release the SDA / SCL lines
register has been read, the slave sends bytes from Set and subsequently clear the STOP bit while
the DR register to the SDA line via the internal shift BTF is set. The SDA/SCL lines are released after
register. the transfer of the current byte.

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I²C bus interface (Cont’d)

[Link] Master mode automatically back to slave mode (M/SL bit
To switch from default Slave mode to Master cleared).
mode, a Start condition generation is needed. Note: In order to generate the non-acknowledge
pulse after the last received data byte, the ACK bit
must be cleared just before reading the second
Start condition last data byte.
Setting the START bit while the BUSY bit is
cleared causes the interface to switch to Master
mode (M/SL bit set) and generates a Start condi- Master transmitter
tion. Following the address transmission and after SR1
Once the Start condition is sent: register has been read, the master sends bytes
from the DR register to the SDA line via the inter-
– The EVF and SB bits are set by hardware with nal shift register.
an interrupt if the ITE bit is set.
The master waits for a read of the SR1 register fol-
Then the master waits for a read of the SR1 regis- lowed by a write in the DR register, holding the
ter followed by a write in the DR register with the SCL line low (see Figure 45 Transfer sequencing
Slave address byte, holding the SCL line low EV8).
(see Figure 45 Transfer sequencing EV5).
When the acknowledge bit is received, the
interface sets:
Slave address transmission – EVF and BTF bits with an interrupt if the ITE bit
Then the slave address byte is sent to the SDA is set.
line via the internal shift register. To close the communication: after writing the last
After completion of this transfer (and acknowledge byte to the DR register, set the STOP bit to gener-
from the slave if the ACK bit is set): ate the Stop condition. The interface goes auto-
– The EVF bit is set by hardware with interrupt matically back to slave mode (M/SL bit cleared).
generation if the ITE bit is set.
Then the master waits for a read of the SR1 regis- Error cases
ter followed by a write in the CR register (for exam- – BERR: Detection of a Stop or a Start condition
ple set PE bit), holding the SCL line low (see Fig- during a byte transfer. In this case, the EVF and
ure 45 Transfer sequencing EV6). BERR bits are set by hardware with an interrupt
Next the master must enter Receiver or Transmit- if ITE is set.
ter mode. Note that BERR will not be set if an error is de-
tected during the first or second pulse of each 9-
bit transaction:
Master receiver Single Master mode
Following the address transmission and after the If a Start or Stop is issued during the first or sec-
SR1 and CR registers have been accessed, the ond pulse of a 9-bit transaction, the BERR flag
master receives bytes from the SDA line into the will not be set and transfer will continue however
DR register via the internal shift register. After the BUSY flag will be reset. To work around this,
each byte the interface generates in sequence: slave devices should issue a NACK when they
receive a misplaced Start or Stop. The reception
– Acknowledge pulse if the ACK bit is set of a NACK or BUSY by the master in the middle
– EVF and BTF bits are set by hardware with an in- of communication gives the possibility to reiniti-
terrupt if the ITE bit is set. ate transmission.
Then the interface waits for a read of the SR1 reg- Multimaster mode
ister followed by a read of the DR register, holding Normally the BERR bit would be set whenever
the SCL line low (see Figure 45 Transfer se- unauthorized transmission takes place while
quencing EV7). transfer is already in progress. However, an is-
sue will arise if an external master generates an
To close the communication: before reading the unauthorized Start or Stop while the I2C master
last byte from the DR register, set the STOP bit to is on the first or second pulse of a 9-bit transac-
generate the Stop condition. The interface goes tion. It is possible to work around this by polling
the BUSY bit during I2C master mode transmis-

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sion. The resetting of the BUSY bit can then be to correctly handle a second interrupt during the
handled in a similar manner as the BERR flag 9th pulse of a transmitted byte.
being set. – ARLO: Detection of an arbitration lost condition.
– AF: Detection of a non-acknowledge bit. In this In this case the ARLO bit is set by hardware (with
case, the EVF and AF bits are set by hardware an interrupt if the ITE bit is set and the interface
with an interrupt if the ITE bit is set. To resume, goes automatically back to slave mode (the M/SL
set the START or STOP bit. bit is cleared).
The AF bit is cleared by reading the I2CSR2 reg- Note: In all these cases, the SCL line is not held
ister. However, if read before the completion of low; however, the SDA line can remain low if the
the transmission, the AF flag will be set again, last bits transmitted are all 0. While AF=1, the SCL
thus possibly generating a new interrupt. Soft- line may be held low due to SB or BTF flags that
ware must ensure either that the SCL line is back are set at the same time. It is then necessary to re-
at 0 before reading the SR2 register, or be able lease both lines by software.

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I²C bus interface (Cont’d)

Figure 45. Transfer sequencing
Slave Receiver
S Address A Data1 A Data2 A DataN A P
.....
EV1 EV2 EV2 EV2 EV4

Slave Transmitter
S Address A Data1 A Data2 A DataN NA P
.....
EV1 EV3 EV3 EV3 EV3-1 EV4

Master Receiver
S Address A Data1 A Data2 A DataN NA P
.....
EV5 EV6 EV7 EV7 EV7

Master Transmitter
S Address A Data1 A Data2 A DataN A P
.....
EV5 EV6 EV8 EV8 EV8 EV8

Legend:
S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge
EVx=Event (with interrupt if ITE=1)
EV1: EVF=1, ADSL=1, cleared by reading the SR1 register.
EV2: EVF=1, BTF=1, cleared by reading the SR1 register followed by reading the DR register.
EV3: EVF=1, BTF=1, cleared by reading the SR1 register followed by writing the DR register.
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading the SR1 register. The BTF is cleared
by releasing the lines (STOP=1, STOP=0) or by writing the DR register (DR=FFh).
Note: If lines are released by STOP=1, STOP=0, the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, cleared by reading the SR2 register.
EV5: EVF=1, SB=1, cleared by reading the SR1 register followed by writing the DR register.
EV6: EVF=1, cleared by reading the SR1 register followed by writing the CR register
(for example PE=1).
EV7: EVF=1, BTF=1, cleared by reading the SR1 register followed by reading the DR register.
EV8: EVF=1, BTF=1, cleared by reading the SR1 register followed by writing the DR register.

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I²C bus interface (Cont’d)

12.5.5 Low power modes
Mode Description
No effect on I²C interface.
Wait
I²C interrupts cause the device to exit from Wait mode.
I²C registers are frozen.
Halt In Halt mode, the I²C interface is inactive and does not acknowledge data on the bus. The I²C
interface resumes operation when the MCU is woken up by an interrupt with “exit from Halt
mode” capability.

12.5.6 Interrupts
Figure 46. Event flags and interrupt generation

BTF ITE
ADSL
SB
AF INTERRUPT
STOPF
ARLO
BERR EVF
*
* EVF can also be set by EV6 or an error from the SR2 register.

Enable Exit Exit

Event
Interrupt event control from from
flag
bit Wait Halt
End of byte Transfer event BTF Yes No
Address Matched event (Slave mode) ADSL Yes No
Start Bit Generation event (Master mode) SB Yes No
Acknowledge Failure event AF ITE Yes No
Stop Detection event (Slave mode) STOPF Yes No
Arbitration Lost event (Multimaster configuration) ARLO Yes No
Bus Error event BERR Yes No

The I²C interrupt events are connected to the They generate an interrupt if the corresponding
same interrupt vector (see Interrupts chapter). Enable Control Bit is set and the I-bit in the CC
register is reset (RIM instruction).

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I²C bus interface (Cont’d)

12.5.7 Register description – In slave mode:
I²C Control Register (CR) 0: No start generation
Read / Write 1: Start generation when the bus is free
Reset value: 0000 0000 (00h)
Bit 2 = ACK Acknowledge enable.
7 0 This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
0 0 PE ENGC START ACK STOP ITE bled (PE=0).
0: No acknowledge returned
1: Acknowledge returned after an address byte or
a data byte is received
Bits 7:6 = Reserved. Forced to 0 by hardware.

Bit 5 = PE Peripheral enable. Bit 1 = STOP Generation of a Stop condition.

This bit is set and cleared by software. This bit is set and cleared by software. It is also
0: Peripheral disabled cleared by hardware in master mode. Note: This
1: Master/Slave capability bit is not cleared when the interface is disabled
Notes: (PE=0).
– When PE=0, all the bits of the CR register and – In Master mode:
the SR register except the Stop bit are reset. All 0: No stop generation
outputs are released while PE=0 1: Stop generation after the current byte transfer
– When PE=1, the corresponding I/O pins are se- or after the current Start condition is sent. The
lected by hardware as alternate functions. STOP bit is cleared by hardware when the Stop
– To enable the I²C interface, write the CR register condition is sent.
TWICE with PE=1 as the first write only activates – In Slave mode:
the interface (only PE is set).
0: No stop generation
1: Release the SCL and SDA lines after the cur-
Bit 4 = ENGC Enable General Call. rent byte transfer (BTF=1). In this mode the
This bit is set and cleared by software. It is also STOP bit has to be cleared by software.
cleared by hardware when the interface is disa-
bled (PE=0). The 00h General Call address is ac- Bit 0 = ITE Interrupt enable.
knowledged (01h ignored). This bit is set and cleared by software and cleared
0: General Call disabled
by hardware when the interface is disabled
1: General Call enabled (PE=0).
0: Interrupts disabled
Note: In accordance with the I2C standard, when
1: Interrupts enabled
GCAL addressing is enabled, an I2C slave can
only receive data. It will not transmit data to the Refer to Figure 46 for the relationship between the
master. events and the interrupt.
SCL is held low when the SB, BTF or ADSL flags
Bit 3 = START Generation of a Start condition. or an EV6 event (See Figure 45) is detected.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0) or when the Start condition is sent
(with interrupt generation if ITE=1).
– In master mode:
0: No start generation
1: Repeated start generation

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I²C bus interface (Cont’d)

I²C Status Register 1 (SR1) Note:
Read Only – The BUSY flag is NOT updated when the inter-
face is disabled (PE=0). This can have conse-
Reset value: 0000 0000 (00h) quences when operating in Multimaster mode;
7 0 i.e. a second active I2C master commencing a
transfer with an unset BUSY bit can cause a con-
flict resulting in lost data. A software workaround
EVF 0 TRA BUSY BTF ADSL M/SL SB
consists of checking that the I2C is not busy be-
fore enabling the I2C Multimaster cell.
Bit 7 = EVF Event flag.
This bit is set by hardware as soon as an event oc- Bit 3 = BTF Byte transfer finished.
curs. It is cleared by software reading SR2 register This bit is set by hardware as soon as a byte is cor-
in case of error event or as described in Figure 45. rectly received or transmitted with interrupt gener-
It is also cleared by hardware when the interface is ation if ITE=1. It is cleared by software reading
disabled (PE=0). SR1 register followed by a read or write of DR reg-
0: No event ister. It is also cleared by hardware when the inter-
1: One of the following events has occurred: face is disabled (PE=0).
– BTF=1 (byte received or transmitted) – Following a byte transmission, this bit is set after
– ADSL=1 (Address matched in Slave mode reception of the acknowledge clock pulse. In
while ACK=1) case an address byte is sent, this bit is set only
– SB=1 (Start condition generated in Master after the EV6 event (See Figure 45). BTF is
mode) cleared by reading SR1 register followed by writ-
ing the next byte in DR register.
– AF=1 (No acknowledge received after byte
transmission) – Following a byte reception, this bit is set after
transmission of the acknowledge clock pulse if
– STOPF=1 (Stop condition detected in Slave ACK=1. BTF is cleared by reading SR1 register
mode) followed by reading the byte from DR register.
– ARLO=1 (Arbitration lost in Master mode) The SCL line is held low while BTF=1.
– BERR=1 (Bus error, misplaced Start or Stop 0: byte transfer not done
condition detected) 1: byte transfer succeeded
– Address byte successfully transmitted in Mas-
ter mode.
Bit 2 = ADSL Address matched (Slave mode).
This bit is set by hardware as soon as the received
Bit 6 = Reserved. Forced to 0 by hardware. slave address matched with the OAR register con-
tent or a general call is recognized. An interrupt is
Bit 5 = TRA Transmitter/Receiver. generated if ITE=1. It is cleared by software read-
When BTF is set, TRA=1 if a data byte has been ing SR1 register or by hardware when the inter-
transmitted. It is cleared automatically when BTF face is disabled (PE=0).
is cleared. It is also cleared by hardware after de- The SCL line is held low while ADSL=1.
tection of Stop condition (STOPF=1), loss of bus 0: Address mismatched or not received
arbitration (ARLO=1) or when the interface is disa- 1: Received address matched
bled (PE=0).
0: Data byte received (if BTF=1)
1: Data byte transmitted Bit 1 = M/SL Master/Slave.
This bit is set by hardware as soon as the interface
is in Master mode (writing START=1). It is cleared
Bit 4 = BUSY Bus busy. by hardware after detecting a Stop condition on
This bit is set by hardware on detection of a Start the bus or a loss of arbitration (ARLO=1). It is also
condition and cleared by hardware on detection of cleared when the interface is disabled (PE=0).
a Stop condition. It indicates a communication in 0: Slave mode
progress on the bus. The BUSY flag of the I2CSR1 1: Master mode
register is cleared if a Bus Error occurs.
0: No communication on the bus
1: Communication ongoing on the bus

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Bit 0 = SB Start bit (Master mode). es the arbitration of the bus to another master. An
This bit is set by hardware as soon as the Start interrupt is generated if ITE=1. It is cleared by soft-
condition is generated (following a write ware reading SR2 register or by hardware when
START=1). An interrupt is generated if ITE=1. It is the interface is disabled (PE=0).
cleared by software reading SR1 register followed After an ARLO event the interface switches back
by writing the address byte in DR register. It is also automatically to Slave mode (M/SL=0).
cleared by hardware when the interface is disa-
bled (PE=0). The SCL line is not held low while ARLO=1.
0: No Start condition 0: No arbitration lost detected
1: Start condition generated 1: Arbitration lost detected
Note:
– In a Multimaster environment, when the interface
I²C Status Register 2 (SR2) is configured in Master Receive mode it does not
Read Only perform arbitration during the reception of the
Reset value: 0000 0000 (00h) Acknowledge Bit. Mishandling of the ARLO bit
from the I2CSR2 register may occur when a sec-
7 0 ond master simultaneously requests the same
data from the same slave and the I2C master
0 0 0 AF STOPF ARLO BERR GCAL does not acknowledge the data. The ARLO bit is
then left at 0 instead of being set.

Bits 7:5 = Reserved. Forced to 0 by hardware. Bit 1 = BERR Bus error.

This bit is set by hardware when the interface de-
tects a misplaced Start or Stop condition. An inter-
Bit 4 = AF Acknowledge failure. rupt is generated if ITE=1. It is cleared by software
This bit is set by hardware when no acknowledge reading SR2 register or by hardware when the in-
is returned. An interrupt is generated if ITE=1. It is terface is disabled (PE=0).
cleared by software reading SR2 register or by The SCL line is not held low while BERR=1.
hardware when the interface is disabled (PE=0).
0: No misplaced Start or Stop condition
Note: While AF=1, the SCL line may be held low 1: Misplaced Start or Stop condition
due to SB or BTF flags that are set at the same Note:
time. It is then necessary to release both lines by – If a Bus Error occurs, a Stop or a repeated Start
software. condition should be generated by the Master to
0: No acknowledge failure re-synchronize communication, get the transmis-
1: Acknowledge failure sion acknowledged and the bus released for fur-
ther communication
Bit 3 = STOPF Stop detection (Slave mode).
This bit is set by hardware when a Stop condition Bit 0 = GCAL General Call (Slave mode).
is detected on the bus after an acknowledge (if This bit is set by hardware when a general call ad-
ACK=1). An interrupt is generated if ITE=1. It is dress is detected on the bus while ENGC=1. It is
cleared by software reading SR2 register or by cleared by hardware detecting a Stop condition
hardware when the interface is disabled (PE=0). (STOPF=1) or when the interface is disabled
The SCL line is not held low while STOPF=1. (PE=0).
0: No Stop condition detected 0: No general call address detected on bus
1: Stop condition detected 1: general call address detected on bus

Bit 2 = ARLO Arbitration lost.

This bit is set by hardware when the interface los-

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I²C bus interface (Cont’d)

I²C Clock Control Register (CCR) Bits 7:0 = D[7:0] 8-bit Data Register.
Read / Write These bits contain the byte to be received or trans-
Reset value: 0000 0000 (00h) mitted on the bus.
– Transmitter mode: byte transmission start auto-
7 0
matically when the software writes in the DR reg-
ister.
FM/SM CC6 CC5 CC4 CC3 CC2 CC1 CC0
– Receiver mode: the first data byte is received au-
tomatically in the DR register using the least sig-
Bit 7 = FM/SM Fast/Standard I²C mode. nificant bit of the address.
This bit is set and cleared by software. It is not Then, the following data bytes are received one
cleared when the interface is disabled (PE=0). by one after reading the DR register.
0: Standard I²C mode
1: Fast I²C mode
I²C Own Address Register (OAR)
Read / Write
Bits 6:0 = CC[6:0] 7-bit clock divider.
Reset value: 0000 0000 (00h)
These bits select the speed of the bus (FSCL) de-
pending on the I²C mode. They are not cleared 7 0
when the interface is disabled (PE=0).
Refer to the Electrical Characteristics section for ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
the table of value.
Note: The programmed FSCL assumes no load on
SCL and SDA lines. Bits 7:1 = ADD[7:1] Interface address.
These bits define the I²C bus address of the inter-
face. They are not cleared when the interface is
disabled (PE=0).
I²C Data Register (DR)
Read / Write
Reset value: 0000 0000 (00h) Bit 0 = ADD0 Address direction bit.
This bit is don’t care, the interface acknowledges
7 0 either 0 or 1. It is not cleared when the interface is
disabled (PE=0).
D7 D6 D5 D4 D3 D2 D1 D0 Note: Address 01h is always ignored.

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Table 23. I²C register map

Address Register
7 6 5 4 3 2 1 0
(Hex.) name
39 DR DR7 .. DR0
3B OAR ADD7 .. ADD0
3C CCR FM/SM CC6 .. CC0
3D SR2 AF STOPF ARLO BERR GCAL
3E SR1 EVF TRA BUSY BTF ADSL M/SL SB
3F CR PE ENGC START ACK STOP ITE

Note: Refer to Section 17, "Known limitations" for information regarding a limitation on the alternate func-
tion on pin PA2 (SCL).

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12.6 8-bit A/D converter (ADC)

12.6.1 Introduction 12.6.3 Functional description

The on-chip Analog to Digital Converter (ADC) pe- [Link] Analog power supply
ripheral is a 8-bit, successive approximation con- VDDA and VSSA are the high and low level refer-
verter with internal sample and hold circuitry. This ence voltage pins. In some devices (refer to device
peripheral has up to 16 multiplexed analog input pin out description) they are internally connected
channels (refer to device pin out description) that to the VDD and VSS pins.
allow the peripheral to convert the analog voltage
levels from up to 16 different sources. Conversion accuracy may therefore be impacted
by voltage drops and noise in the event of heavily
The result of the conversion is stored in a 8-bit loaded or badly decoupled power supply lines.
Data Register. The A/D converter is controlled
through a Control/Status Register. See electrical characteristics section for more de-
tails.
12.6.2 Main features
■ 8-bit conversion

■ Up to 12 channels with multiplexed input

■ Linear successive approximation

■ Data register (DR) which contains the results

■ Conversion complete status flag

■ On/off bit (to reduce consumption)

The block diagram is shown in Figure 47.

Figure 47. ADC block diagram

fCPU fADC
DIV 4

COCO 0 ADON 0 CH3 CH2 CH1 CH0 ADCCSR

AIN0
HOLD CONTROL

AIN1 RADC
ANALOG ANALOG TO DIGITAL
MUX CONVERTER

AINx CADC

ADCDR D7 D6 D5 D4 D3 D2 D1 D0

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8-bit A/D converter (ADC) (Cont’d)

[Link] Digital A/D conversion result The analog input ports must be configured as in-
The conversion is monotonic, meaning that the re- put, no pull-up, no interrupt. Refer to the «I/O
sult never decreases if the analog input does not ports» chapter. Using these pins as analog inputs
and never increases if the analog input does not. does not affect the ability of the port to be read as
a logic input.
If the input voltage (VAIN) is greater than or equal
to VDDA (high-level voltage reference) then the In the CSR register:
conversion result in the DR register is FFh (full – Select the CH[3:0] bits to assign the analog
scale) without overflow indication. channel to be converted.
If input voltage (VAIN) is lower than or equal to ADC conversion
VSSA (low-level voltage reference) then the con- In the CSR register:
version result in the DR register is 00h.
– Set the ADON bit to enable the A/D converter
The A/D converter is linear and the digital result of and to start the first conversion. From this time
the conversion is stored in the ADCDR register. on, the ADC performs a continuous conver-
The accuracy of the conversion is described in the sion of the selected channel.
parametric section. When a conversion is complete
RAIN is the maximum recommended impedance – The COCO bit is set by hardware.
for an analog input signal. If the impedance is too – No interrupt is generated.
high, this will result in a loss of accuracy due to – The result is in the DR register and remains
leakage and sampling not being completed in the valid until the next conversion has ended.
alloted time. A write to the CSR register (with ADON set) aborts
[Link] A/D conversion phases the current conversion, resets the COCO bit and
The A/D conversion is based on two conversion starts a new conversion.
phases as shown in Figure 48:
Figure 48. ADC conversion timings
■ Sample capacitor loading [duration: tLOAD]
During this phase, the VAIN input voltage to be
measured is loaded into the CADC sample ADON
ADCCSR WRITE
capacitor. tCONV
OPERATION
■ A/D conversion [duration: tCONV]
During this phase, the A/D conversion is HOLD
computed (8 successive approximations cycles) CONTROL
and the CADC sample capacitor is disconnected
from the analog input pin to get the optimum tLOAD
analog to digital conversion accuracy. COCO BIT SET

While the ADC is on, these two phases are contin-

uously repeated. 12.6.4 Low power modes
At the end of each conversion, the sample capaci- Mode Description
tor is kept loaded with the previous measurement
load. The advantage of this behaviour is that it Wait No effect on A/D Converter
minimizes the current consumption on the analog A/D Converter disabled.
pin in case of single input channel measurement. After wakeup from Halt mode, the A/D Con-
Halt
verter requires a stabilisation time before ac-
[Link] Software Procedure
curate conversions can be performed.
Refer to the control/status register (CSR) and data
register (DR) in Section 12.6.6 for the bit defini- Note: The A/D converter may be disabled by reset-
tions and to Figure 48 for the timings. ting the ADON bit. This feature allows reduced
power consumption when no conversion is needed
ADC configuration and between single shot conversions.
The total duration of the A/D conversion is 12 ADC
clock periods (1/fADC=4/fCPU). 12.6.5 Interrupts
None

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8-bit A/D converter (ADC) (Cont’d)

12.6.6 Register description
Control/Status Register (CSR) pinout.
2
Read/Write For SDIP/SO34 devices, the CH3 bit is always at
‘0’. If, however, set to ‘1’ on error, channel (11:8)
Reset value: 0000 0000 (00h) becomes enabled which may result in a higher and
unnecessary level of consumption.
7 0
Data Register (DR)
COCO 0 ADON 0 CH3 CH2 CH1 CH0 Read Only
Reset value: 0000 0000 (00h)
Bit 7 = COCO Conversion Complete
This bit is set by hardware. It is cleared by soft- 7 0
ware reading the result in the DR register or writing
to the CSR register. D7 D6 D5 D4 D3 D2 D1 D0
0: Conversion is not complete
1: Conversion can be read from the DR register

Bits 7:0 = D[7:0] Analog Converted value

Bit 6 = Reserved. must always be cleared. This register contains the converted analog value
in the range 00h to FFh.
Bit 5 = ADON A/D Converter On Note: Reading this register reset the COCO flag.
This bit is set and cleared by software.
0: A/D converter is switched off
1: A/D converter is switched on

Bit 4 = Reserved. must always be cleared.

Bits 3:0 = CH[3:0] Channel Selection

These bits are set and cleared by software. They
select the analog input to convert.
Channel Pin1 CH32 CH2 CH1 CH0
AIN0 0 0 0 0
AIN1 0 0 0 1
AIN2 0 0 1 0
AIN3 0 0 1 1
AIN4 0 1 0 0
AIN5 0 1 0 1
AIN6 0 1 1 0
AIN7 0 1 1 1
AIN8 1 0 0 0
AIN9 1 0 0 1
AIN10 1 0 1 0
AIN11 1 0 1 1
1
The number of pins AND the channel selection
varies according to the device. Refer to the device

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8-bit A/D converter (ADC) (Cont’d)

Table 24. ADC register map

Address Register
7 6 5 4 3 2 1 0
(Hex.) Name
0Ah DR AD7 .. AD0
0Bh CSR COCO 0 ADON 0 CH3 CH2 CH1 CH0

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13 Instruction set

13.1 ST7 addressing modes so, most of the addressing modes may be subdi-
vided in two sub-modes called long and short:
The ST7 Core features 17 different addressing
modes which can be classified in 7 main groups: – Long addressing mode is more powerful be-
cause it can use the full 64 Kbyte address space,
Addressing mode Example however it uses more bytes and more CPU cy-
Inherent nop cles.
Immediate ld A,#$55 – Short addressing mode is less powerful because
it can generally only access page zero (0000h -
Direct ld A,$55 00FFh range), but the instruction size is more
Indexed ld A,($55,X) compact, and faster. All memory to memory in-
Indirect ld A,([$55],X) structions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
Relative jrne loop INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Bit operation bset byte,#5 The ST7 Assembler optimizes the use of long and
short addressing modes.
The ST7 instruction set is designed to minimize
the number of bytes required per instruction: To do
Table 25. ST7 addressing mode overview

Pointer Pointer
Destination/ Length
Mode Syntax address size
source (bytes)
(Hex.) (Hex.)
Inherent nop +0
Immediate ld A,#$55 +1
Short Direct ld A,$10 00..FF +1
Long Direct ld A,$1000 0000..FFFF +2
+ 0 (with X register)
No Offset Direct Indexed ld A,(X) 00..FF
+ 1 (with Y register)
Short Direct Indexed ld A,($10,X) 00..1FE +1
Long Direct Indexed ld A,($1000,X) 0000..FFFF +2
Short Indirect ld A,[$10] 00..FF 00..FF byte +2
Long Indirect ld A,[$10.w] 0000..FFFF 00..FF word +2
Short Indirect Indexed ld A,([$10],X) 00..1FE 00..FF byte +2
Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF 00..FF word +2
1)
Relative Direct jrne loop PC-128/PC+127 +1
Relative Indirect jrne [$10] PC-128/PC+1271) 00..FF byte +2
Bit Direct bset $10,#7 00..FF +1
Bit Indirect bset [$10],#7 00..FF 00..FF byte +2
Bit Direct Relative btjt $10,#7,skip 00..FF +2
Bit Indirect Relative btjt [$10],#7,skip 00..FF 00..FF byte +3

Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction follow-
ing JRxx.

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ST7 addressing modes (Cont’d)

13.1.1 Inherent 13.1.3 Direct
All Inherent instructions consist of a single byte. In Direct instructions, the operands are referenced
The opcode fully specifies all the required informa- by their memory address.
tion for the CPU to process the operation. The direct addressing mode consists of two sub-
Inherent instruction Function modes:
NOP No operation Direct (short)
TRAP S/W Interrupt The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF address-
Wait For Interrupt (Low power ing space.
WFI
mode)
Direct (long)
Halt Oscillator (Lowest Power
HALT The address is a word, thus allowing 64 Kbyte ad-
mode)
dressing space, but requires 2 bytes after the op-
RET Sub-routine Return code.
IRET Interrupt Sub-routine Return
SIM Set Interrupt Mask
13.1.4 Indexed (No Offset, Short, Long)
RIM Reset Interrupt Mask
In this mode, the operand is referenced by its
SCF Set Carry flag memory address, which is defined by the unsigned
RCF Reset Carry flag addition of an index register (X or Y) with an offset.
RSP Reset Stack Pointer The indirect addressing mode consists of three
sub-modes:
LD Load
Indexed (No Offset)
CLR Clear
There is no offset, (no extra byte after the opcode),
PUSH/POP Push/Pop to/from the stack
and allows 00 - FF addressing space.
INC/DEC Increment/Decrement
Indexed (Short)
TNZ Test Negative or Zero
The offset is a byte, thus requires only one byte af-
CPL, NEG 1 or 2 Complement ter the opcode and allows 00 - 1FE addressing
MUL Byte Multiplication space.
SLL, SRL, SRA, RLC, Indexed (long)
Shift and Rotate Operations
RRC The offset is a word, thus allowing 64 Kbyte ad-
SWAP Swap Nibbles dressing space and requires 2 bytes after the op-
code.
13.1.2 Immediate
Immediate instructions have two bytes, the first 13.1.5 Indirect (Short, Long)
byte contains the opcode, the second byte con-
The required data byte to do the operation is found
tains the operand value.
by its memory address, located in memory (point-
Immediate instruction Function er).
LD Load The pointer address follows the opcode. The indi-
rect addressing mode consists of two sub-modes:
CP Compare
Indirect (short)
BCP Bit Compare
The pointer address is a byte, the pointer size is a
AND, OR, XOR Logical Operations
byte, thus allowing 00 - FF addressing space, and
ADC, ADD, SUB, SBC Arithmetic Operations requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.

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ST7 addressing modes (Cont’d)

13.1.6 Indirect Indexed (Short, Long) SWAP Swap Nibbles
This is a combination of indirect and short indexed CALL, JP Call or Jump subroutine
addressing modes. The operand is referenced by
its memory address, which is defined by the un- 13.1.7 Relative mode (Direct, Indirect)
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point- This addressing mode is used to modify the PC
er address follows the opcode. register value by adding an 8-bit signed offset to it.
The indirect indexed addressing mode consists of Available Relative Direct/
Function
two sub-modes: Indirect instructions
Indirect Indexed (Short) JRxx Conditional Jump
The pointer address is a byte, the pointer size is a CALLR Call Relative
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode. The relative addressing mode consists of two sub-
Indirect Indexed (Long) modes:
The pointer address is a byte, the pointer size is a Relative (Direct)
word, thus allowing 64 Kbyte addressing space, The offset follows the opcode.
and requires 1 byte after the opcode. Relative (Indirect)
Table 26. Instructions supporting Direct, The offset is defined in memory, of which the ad-
Indexed, Indirect and Indirect Indexed dress follows the opcode.
addressing modes
Long and Short
Function
instructions
LD Load
CP Compare
AND, OR, XOR Logical Operations
Arithmetic Addition/subtrac-
ADC, ADD, SUB, SBC
tion operations
BCP Bit Compare

Short instructions only Function

CLR Clear
INC, DEC Increment/Decrement
TNZ Test Negative or Zero
CPL, NEG 1 or 2 Complement
BSET, BRES Bit Operations
Bit Test and Jump Opera-
BTJT, BTJF
tions
SLL, SRL, SRA, RLC,
Shift and Rotate Operations
RRC

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13.2 insTruction groups

The ST7 family devices use an instruction set con- subdivided into 13 main groups as illustrated in the
sisting of 63 instructions. The instructions may be following table:
Load and Transfer LD CLR
Stack operation PUSH POP RSP
Increment/Decrement INC DEC
Compare and Tests CP TNZ BCP
Logical operations AND OR XOR CPL NEG
Bit Operation BSET BRES
Conditional Bit Test and Branch BTJT BTJF
Arithmetic operations ADC ADD SUB SBC MUL
Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA
Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP RET
Conditional Branch JRxx
Interruption management TRAP WFI HALT IRET
Condition Code flag modification SIM RIM SCF RCF

Using a pre-byte
The instructions are described with one to four These prebytes enable instruction in Y as well as
bytes. indirect addressing modes to be implemented.
In order to extend the number of available op- They precede the opcode of the instruction in X or
codes for an 8-bit CPU (256 opcodes), three differ- the instruction using direct addressing mode. The
ent prebyte opcodes are defined. These prebytes prebytes are:
modify the meaning of the instruction they pre- PDY 90 Replace an X based instruction using
cede. immediate, direct, indexed, or inherent
The whole instruction becomes: addressing mode by a Y one.
PC-2 End of previous instruction PIX 92 Replace an instruction using direct, di-
rect bit, or direct relative addressing
PC-1 Prebyte mode to an instruction using the corre-
PC Opcode sponding indirect addressing mode.
PC+1 Additional word (0 to 2) according to the It also changes an instruction using X
number of bytes required to compute the indexed addressing mode to an instruc-
effective address tion using indirect X indexed addressing
mode.
PIY 91 Replace an instruction using X indirect
indexed addressing mode by a Y one.

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Instruction groups (Cont’d)

Mnemo Description Function/Example Dst Src H I N Z C
ADC Add with Carry A=A+M+C A M H N Z C
ADD Addition A=A+M A M H N Z C
AND Logical And A=A.M A M N Z
BCP Bit compare A, Memory tst (A . M) A M N Z
BRES Bit Reset bres byte, #3 M
BSET Bit Set bset byte, #3 M
BTJF Jump if bit is false (0) btjf byte, #3, Jmp1 M C
BTJT Jump if bit is true (1) btjt byte, #3, Jmp1 M C
CALL Call subroutine
CALLR Call subroutine relative
CLR Clear reg, M 0 1
CP Arithmetic Compare tst(Reg - M) reg M N Z C
CPL One Complement A = FFH-A reg, M N Z 1
DEC Decrement dec Y reg, M N Z
HALT Halt 0
IRET Interrupt routine return Pop CC, A, X, PC H I N Z C
INC Increment inc X reg, M N Z
JP Absolute Jump jp [TBL.w]
JRA Jump relative always
JRT Jump relative
JRF Never jump jrf *
JRIH Jump if ext. interrupt = 1
JRIL Jump if ext. interrupt = 0
JRH Jump if H = 1 H=1?
JRNH Jump if H = 0 H=0?
JRM Jump if I = 1 I=1?
JRNM Jump if I = 0 I=0?
JRMI Jump if N = 1 (minus) N=1?
JRPL Jump if N = 0 (plus) N=0?
JREQ Jump if Z = 1 (equal) Z=1?
JRNE Jump if Z = 0 (not equal) Z=0?
JRC Jump if C = 1 C=1?
JRNC Jump if C = 0 C=0?
JRULT Jump if C = 1 Unsigned <
JRUGE Jump if C = 0 Jmp if unsigned >=
JRUGT Jump if (C + Z = 0) Unsigned >

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Instruction groups(Cont’d)
Mnemo Description Function/Example Dst Src H I N Z C

JRULE Jump if (C + Z = 1) Unsigned <=

LD Load dst <= src reg, M M, reg N Z

MUL Multiply X,A = X * A A, X, Y X, Y, A 0 0

NEG Negate (2's compl) neg $10 reg, M N Z C

NOP No Operation

OR OR operation A=A+M A M N Z

POP Pop from the Stack pop reg reg M

pop CC CC M H I N Z C

PUSH Push onto the Stack push Y M reg, CC

RCF Reset carry flag C=0 0

RET Subroutine Return

RIM Enable Interrupts I=0 0

RLC Rotate left true C C <= Dst <= C reg, M N Z C

RRC Rotate right true C C => Dst => C reg, M N Z C

RSP Reset Stack Pointer S = Max allowed

SBC Subtract with Carry A=A-M-C A M N Z C

SCF Set carry flag C=1 1

SIM Disable Interrupts I=1 1

SLA Shift left Arithmetic C <= Dst <= 0 reg, M N Z C

SLL Shift left Logic C <= Dst <= 0 reg, M N Z C

SRL Shift right Logic 0 => Dst => C reg, M 0 Z C

SRA Shift right Arithmetic Dst7 => Dst => C reg, M N Z C

SUB Subtraction A=A-M A M N Z C

SWAP SWAP nibbles Dst[7..4] <=> Dst[3..0] reg, M N Z

TNZ Test for Neg & Zero tnz lbl1 N Z

TRAP S/W trap S/W interrupt 1

WFI Wait for Interrupt 0

XOR Exclusive OR A = A XOR M A M N Z

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14 Electrical characteristics

14.1 Parameter conditions

Unless otherwise specified, all voltages are re- Figure 50. Pin input voltage
ferred to VSS.
14.1.1 Minimum and maximum values
Unless otherwise specified the minimum and max- ST7 PIN
imum values are guaranteed in the worst condi-
tions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the VIN
devices with an ambient temperature at TA=25°C
and TA=TAmax (given by the selected temperature
range).
Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the min-
imum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean±3Σ).
14.1.2 Typical values
Unless otherwise specified, typical data are based
on TA=25°C, VDD=5V. They are given only as de-
sign guidelines and are not tested.
14.1.3 Typical curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
14.1.4 Loading capacitor
The loading conditions used for pin parameter
measurement are shown in Figure 49.
Figure 49. Pin loading conditions

ST7 PIN

CL

14.1.5 Pin input voltage

The input voltage measurement on a pin of the de-
vice is described in Figure 50.

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14.2 Absolute maximum ratings

Stresses above those listed as “absolute maxi- tions is not implied. Exposure to maximum rating
mum ratings” may cause permanent damage to conditions for extended periods may affect device
the device. This is a stress rating only and func- reliability.
tional operation of the device under these condi-
14.2.1 Voltage characteristics
Symbol Ratings Maximum value Unit
VDD - VSS Supply voltage 6.0
Input voltage on true open drain pins VSS-0.3 to 6.0 V
VIN1) & 2)
Input voltage on any other pin VSS-0.3 to VDD+0.3
See “Absolute maximum ratings
VESD(HBM) Electro-static discharge voltage (Human Body model)
(electrical sensitivity)” on page 116.

14.2.2 Current characteristics

Symbol Ratings Maximum value Unit
IVDD Total current into VDD power lines (source) 3) 80
IVSS Total current out of VSS ground lines (sink) 3) 80
Output current sunk by any standard I/O and control pin 25
IIO Output current sunk by any high sink I/O pin 50
Output current source by any I/Os and control pin - 25
mA
Injected current on VPP pin ±5
Injected current on RESET pin ±5
IINJ(PIN) 2) & 4)
Injected current on OSCIN and OSCOUT pins ±5
Injected current on any other pin 5) & 6) ±5
ΣIINJ(PIN) 2) Total injected current (sum of all I/O and control pins) 5) ± 20
2) & 4) Negative injected current to PB0(10mA)/AIN0 pin
IINJ(PIN) - 80 µA

Notes:
1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for
RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to VDD or VSS according to their reset configuration.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be
respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD
while a negative injection is induced by VIN<VSS. For true open-drain pads, there is no positive injection current, and the
corresponding VIN maximum must always be respected
3. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout
the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage
is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as
far as possible from the analog input pins.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive
and negative injected currents (instantaneous values). These results are based on characterization with ΣIINJ(PIN) maxi-
mum current injection on four I/O port pins of the device.
6. True open drain I/O port pins do not accept positive injection.
14.2.3 Thermal characteristics
Symbol Ratings value Unit
TSTG Storage temperature range -65 to +150 °C
TJ Maximum junction temperature: See section 15.2 on page 131 for TJmax

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14.3 Operating conditions

14.3.1 General operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VDD Operating Supply Voltage fCPU = 8 MHz 4 5 5.5
VDDA Analog reference voltage VDD VDD V
VSSA Analog reference voltage VSS VSS
fOSC = 24 MHz 8
fCPU Operating frequency MHz
fOSC = 12 MHz 4
TA Ambient temperature range 0 70 °C

Figure 51. fCPU maximum operating frequency versus VDD supply voltage

fCPU [MHz]

8
FUNCTIONALITY
GUARANTEED
FROM 4 TO 5.5 V

FUNCTIONALITY
NOT GUARANTEED 2
IN THIS AREA
0
2.5 3.0 3.5 4 4.5 5 5.5 SUPPLY VOLTAGE [V]

14.3.2 Operating conditions with Low Voltage Detector (LVD)

Subject to general operating conditions for VDD, fCPU, and TA. Refer to Figure 12 on page 24.
Symbol Parameter Conditions Min Typ Max Unit
VIT+ Low Voltage Reset Threshold (VDD rising) VDD Max. Variation 50V/ms 3.4 3.7 4.0 V
VIT- Low Voltage Reset Threshold (VDD falling) VDD Max. Variation 50V/ms 3.2 3.5 3.8 V
Vhyst Hysteresis (VIT+ - VIT-) 2) 100 175 220 mV
VtPOR VDD rise time rate 1) 0.5 50 V/ms
Notes:
1. The VDD rise time rate condition is needed to insure a correct device power-on and LVD reset. Not tested in production.
2. Guaranteed by characterization - not tested in production

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14.4 Supply current characteristics

The following current consumption specified for added (except for Halt mode for which the clock is
the ST7 functional operating modes over tempera- stopped).
ture range does not take into account the clock
source current consumption. To get the total de-
vice consumption, the two current values must be
Symbol Parameter Conditions Typ Max Unit
∆IDD(∆Ta) Supply current variation vs. temperature Constant VDD and fCPU 10 3)
%
fCPU = 4 MHz 7.5 9 1)3)
CPU Run mode I/Os in input mode mA
fCPU = 8 MHz 10.5 13 1)
fCPU = 4 MHz 6 8 3)
CPU Wait mode mA
IDD fCPU = 8 MHz 8.5 11 1)
CPU Halt mode 2) LVD disabled 25 40 3) µA
LVD disabled 100 120
USB Suspend mode 4) µA
LVD enabled 230

Notes:
1. Oscillator and watchdog running. All others peripherals disabled.
2. USB Transceiver and ADC are powered down.
3. Not tested in production, guaranteed by characterization.
4. CPU in Halt mode. Current consumption of external pull-up (1.5Kohms to USBVCC) and pull-down (15Kohms to
VSSA) not included.

Figure 52. Typ. IDD in Run at 4 and 8 MHz fCPU Figure 53. Typ. IDD in Wait at 4 and 8 MHz fCPU

Idd Run (mA) at fcpu=4 and 8MHz Idd WFI (mA) at fcpu=4 and 8MHz

12 10

10
8

8
Idd Run (mA)

Idd WFI (mA)

6
6

4
4

8MHz
8MHz 2
2
4MHz
4MHz
0 0
4 4.2 4.4 4.6 4.8 5 5.2 5.4 4 4.2 4.4 4.6 4.8 5 5.2 5.4
Vdd (V) Vdd (V)

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14.5 Clock and timing characteristics

Subject to general operating conditions for VDD, fCPU, and TA.
14.5.1 General timings
Symbol Parameter Conditions Min Typ 1) Max Unit
2 3 12 tCPU
tc(INST) Instruction cycle time fCPU=8MHz
250 375 1500 ns
2) 10 22 tCPU
Interrupt reaction time
tv(IT) fCPU=8MHz
tv(IT) = ∆tc(INST) + 10 tCPU 1.25 2.75 µs

Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish
the current instruction execution.

14.5.2 Control timing characteristics

Control timings
value
Symbol Parameter Conditions Unit
Min Typ. Max
fOSC Oscillator Frequency 24 MHz
fCPU Operating Frequency 8 MHz
External RESET
tRL 2520 ns
Input pulse Width
tPORL Internal Power Reset Duration 4096 tCPU
Watchdog or Low Voltage Reset
TDOGL 200 300 ns
Output Pulse Width
49152 3145728 tCPU
tDOG Watchdog Time-out
fcpu = 8MHz 6.144 393.216 ms
Crystal Oscillator
tOXOV 201) 30 401) ms
Start-up Time
tDDR Power up rise time from VDD = 0 to 4V 1001) ms

Note:
1. Not tested in production, guaranteed by characterization.

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Clock and timing characteristics (Cont’d)

14.5.3 External clock source
Symbol Parameter Conditions Min Typ Max Unit
VOSCINH OSCIN input pin high level voltage 0.7xVDD VDD
V
VOSCINL OSCIN input pin low level voltage VSS 0.3xVDD
tw(OSCINH)
OSCIN high or low time 1) see Figure 54 15
tw(OSCINL)
ns
tr(OSCIN)
OSCIN rise or fall time1) 15
tf(OSCIN)
IL OSCx Input leakage current VSS≤VIN≤VDD ±1 µA

Note:
1. Data based on design simulation and/or technology characteristics, not tested in production.
Figure 54. Typical application with an external clock source

90%
VOSCINH
10%

VOSCINL

tr(OSCIN) tf(OSCIN) tw(OSCINH) tw(OSCINL)

OSCOUT
Not connected internally

fOSC
EXTERNAL
IL
CLOCK SOURCE
OSCIN
ST72XXX

Figure 55. Typical application with a crystal resonator

i2

fOSC
CL1 OSCIN

RESONATOR RF
CL2
OSCOUT
ST72XXX

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14.6 Memory characteristics

Subject to general operating conditions for fCPU, and TA unless otherwise specified.
14.6.1 RAM and hardware registers
Symbol Parameter Conditions Min Typ Max Unit
VRM Data retention mode 1) Halt mode (or RESET) 2.0 V

Note:
1. Guaranteed by design. Not tested in production.

14.6.2 Flash memory

Operating Conditions: fCPU = 8 MHz.

Dual voltage Flash memory 1)

Symbol Parameter Conditions Min Typ Max Unit
Read mode 8
fCPU Operating Frequency Write / Erase mode, MHz
8
TA=25°C
VPP Programming Voltage 4.0V ≤VDD ≤ 5.5V 11.4 12.6 V
IPP VPP Current Write / Erase 30 mA
tVPP Internal VPP Stabilization Time 10 µs
tRET Data Retention TA ≤ 55°C 40 years
NRW Write Erase Cycles TA=25°C 100 cycles
Note:
1. Refer to the Flash Programming Reference Manual for the typical HDFlash programming and erase timing values.

Figure 56. Two typical applications with VPP pin1)

VPP VPP
PROGRAMMING
TOOL
10kΩ
ST72XXX ST72XXX

Note:
1. When the ICP mode is not required by the application, VPP pin must be tied to VSS.

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14.7 EMC characteristics tion environment and simplified MCU software. It

should be noted that good EMC performance is
Susceptibility tests are performed on a sample ba- highly dependent on the user application and the
sis during product characterization. software in particular.
14.7.1 Functional EMS (Electromagnetic Therefore it is recommended that the user applies
susceptibility) EMC software optimization and prequalification
Based on a simple running application on the tests in relation with the EMC level requested for
product (toggling 2 LEDs through I/O ports), the his application.
product is stressed by two electro magnetic events Software recommendations:
until a failure occurs (indicated by the LEDs).
The software flowchart must include the manage-
■ ESD: Electro-Static Discharge (positive and
ment of runaway conditions such as:
negative) is applied on all pins of the device until
a functional disturbance occurs. This test – Corrupted program counter
conforms with the IEC 1000-4-2 standard. – Unexpected reset
■ FTB: A Burst of Fast Transient voltage (positive – Critical Data corruption (control registers...)
and negative) is applied to VDD and VSS through
a 100pF capacitor, until a functional disturbance Prequalification trials:
occurs. This test conforms with the IEC 1000-4- Most of the common failures (unexpected reset
4 standard. and program counter corruption) can be repro-
A device reset allows normal operations to be re- duced by manually forcing a low state on the RE-
sumed. The test results are given in the table be- SET pin or the Oscillator pins for 1 second.
low based on the EMS levels and classes defined To complete these trials, ESD stress can be ap-
in application note AN1709. plied directly on the device, over the range of
[Link] Designing hardened software to avoid specification values. When unexpected behaviour
noise problems is detected, the software can be hardened to pre-
vent unrecoverable errors occurring (see applica-
EMC characterization and optimization are per- tion note AN1015).
formed at component level with a typical applica-
Level/
Symbol Parameter Conditions
Class
Voltage limits to be applied on any I/O pin to induce VDD=5V, TA=+25°C, fOSC=8MHz, PSDIP32
VFESD 4B
a functional disturbance conforms to IEC 1000-4-2
Fast transient voltage burst limits to be applied
VDD=5V, TA=+25°C, fOSC=8MHz, PSDIP32
VFFTB through 100pF on VDD and VDD pins to induce a 4A
conforms to IEC 1000-4-4
functional disturbance

14.7.2 Electromagnetic interference (EMI)

Based on a simple application running on the
product (toggling 2 LEDs through the I/O ports),
the product is monitored in terms of emission. This
emission test is in line with the norm SAE J 1752/
3 which specifies the board and the loading of
each pin.
Max vs.
Monitored [fOSC/
Symbol Parameter Conditions fCPU] Unit
frequency band
16/8MHz
VDD=5V, TA=+25°C, PSDIP32 package 0.1MHz to 30MHz 36
conforming to SAE J 1752/3 30MHz to 130MHz 39 dBµV
SEMI Peak level 1)
Note: Refer to Application Note AN1709 for 130MHz to 1GHz 26
data on other package types. SAE EMI Level 3.5 -
Note:
1. Data based on characterization results, not tested in production.

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EMC characteristics (Cont’d)

14.7.3 Absolute maximum ratings (electrical [Link] Electrostatic discharge (ESD)
sensitivity) Electrostatic Discharges (a positive then a nega-
Based on three different tests (ESD, LU and DLU) tive pulse separated by 1 second) are applied to
using specific measurement methods, the product the pins of each sample according to each pin
is stressed in order to determine its performance in combination. The sample size depends on the
terms of electrical sensitivity. For more details, re- number of supply pins in the device (3 parts*(n+1)
fer to the application note AN1181. supply pin). This test conforms to the JESD22-
A114A/A115A standard.
Absolute maximum ratings
Symbol Ratings Conditions Maximum value 1) Unit
Electrostatic discharge voltage
VESD(HBM) TA=+25°C 2000 V
(Human body model)

Note:
1. Data based on characterization results, not tested in production.
[Link] Static and dynamic Latch-Up ■ DLU: Electrostatic discharges (one positive
■ LU: 3 complementary static tests are required then one negative test) are applied to each pin
on 10 parts to assess the latch-up performance. of 3 samples when the micro is running to
A supply overvoltage (applied to each power assess the latch-up performance in dynamic
supply pin) and a current injection (applied to mode. Power supplies are set to the typical
each input, output and configurable I/O pin) are values, the oscillator is connected as near as
performed on each sample. This test conforms possible to the pins of the micro and the
to the EIA/JESD 78 IC latch-up standard. For component is put in reset mode. This test
more details, refer to the application note conforms to the IEC1000-4-2 and SAEJ1752/3
AN1181. standards. For more details, refer to the
application note AN1181.
Electrical sensitivities
Symbol Parameter Conditions Class 1)
LU Static latch-up class TA=+25°C A
DLU Dynamic latch-up class VDD=5.5V, fOSC=4MHz, TA=+25°C A

Note:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).

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14.8 I/O port pin characteristics

14.8.1 General characteristics
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
VIL Input low level voltage 0.3xVDD
V
VIH Input high level voltage 0.7xVDD
True open drain I/O pins 6.0
VIN Input voltage VSS V
Other I/O pins VDD
Vhys Schmitt trigger voltage hysteresis 400 mV
IL Input leakage current VSS≤VIN≤VDD ±1
Static current consumption induced µA
IS Floating input mode 400
by each floating input pin 1)
RPU Weak pull-up equivalent resistor 2) VIN=VSS VDD=5V 50 90 120 kΩ
CIO I/O pin capacitance 5 pF
tf(IO)out Output high to low level fall time CL=50pF 25
ns
tr(IO)out Output low to high level rise time Between 10% and 90% 25
tw(IT)in External interrupt pulse time 3) 1 tCPU

Notes:
1. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 57). Static peak current value taken at a fixed VIN value,
based on design simulation and technology characteristics, not tested in production. This value depends on VDD and tem-
perature values.
2. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics de-
scribed in Figure 58).
3. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.

Figure 57. Two typical applications with unused I/O pin

VDD ST72XXX
UNUSED I/O PORT
10kΩ 10kΩ
UNUSED I/O PORT
ST72XXX

Figure 58. Typ. IPU vs. VDD

Pull-up current (µA)

90

80

70
Pull-up current (µA)

60

50

40

30

20

10

0
4 4.2 4.4 4.6 4.8 5 5.2 5.4
Vdd (V)

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Figure 59. Typ. RPU vs. VDD

Rpu (KOhm)
140

120

100
Rpu (KOhm)

80

60

40

20

0
4 4.2 4.4 4.6 4.8 5 5.2 5.4
Vdd (V)

14.8.2 Output driving current

Subject to general operating condition for VDD, fCPU, and TA unless otherwise specified.
Symbol Parameter Conditions Min Max Unit
Output low level voltage for a standard I/O pin
when up to 8 pins are sunk at the same time, Port IIO=+1.6mA 0.4
A0, Port A(3:7), Port C(0:2), Port D(0:7)
Output low level voltage for a high sink I/O pin
VOL 1) when up to 4 pins are sunk at the same time, Port IIO=+10mA 1.3
VDD=5V

B(0:7) V
Output low level voltage for a very high sink I/O
pin when up to 2 pins are sunk at the same time, IIO=+25mA 1.5
Port A1, Port A2
Output high level voltage for an I/O pin IIO=-10mA VDD-1.3 3)
VOH 2)
when up to 8 pins are sourced at same time IIO=-1.6mA VDD-0.8

Notes:
1. The IIO current sunk must always respect the absolute maximum rating specified in Section 14.2 and the sum of IIO (I/
O ports and control pins) must not exceed IVSS.
2. The IIO current sourced must always respect the absolute maximum rating specified in Section 14.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVDD. True open drain I/O pins does not have VOH.
3. The minimum VOH value (with IIO=-10mA) depends on the chosen device type. For Flash devices, min = VDD - 1.3 V
and for ROM devices, min = VDD - 1.7 V

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Figure 60. VOL standard VDD=5 V Figure 61. VOL high sink VDD=5 V
Vol_2mA (mV) at Vdd=5V Vol_10mA (V) at Vdd=5V
250 1.6

1.4
200

1.2
Vol_2mA (mV)

Vol_10mA (V)
150
1

100 0.8

0.6
50
0.4

0 0.2
1 1.5 2 2.5 3 3.5 4 5 7 9 11 13 15 17 19
Iio (mA) Iio (mA)

Figure 62. VOL very high sink VDD=5 V Figure 64. VOL high sink vs. VDD
Vol_25mA (V) at Vdd=5V Vol_10mA (V) at Iio=10mA
0.6
0.95
0.59

0.58
0.85
0.57
Vol_25mA (V)

Vol_10mA (V)

0.75 0.56

0.55
0.65
0.54

0.55 0.53

0.52
0.45
0.51

0.35 0.5
15 20 25 30 35 4 4.2 4.4 4.6 4.8 5 5.2 5.4
Iio (mA) Vdd (V)

Figure 63. VOL standard vs. VDD Figure 65. VOL very high sink vs. VDD

Vol_2mA (mV) at Iio=2mA Vol_25mA (V) at Iio=25mA

130 0.8

125
0.75
Vol_25mA (V)
Vol_2mA (mV)

120
0.7

115

0.65
110

0.6
105
4 4.2 4.4 4.6 4.8 5 5.2 5.4
4 4.2 4.4 4.6 4.8 5 5.2 5.4
Vdd (V) Vdd (V)

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Figure 66. |VDD-VOH| @ VDD=5 V (low current) Figure 67. |VDD-VOH| @ VDD=5 V (high current)
|Vdd - Voh| (V) at Vdd=5V |Vdd - Voh| (V) at Vdd=5V
0.3 2

1.8
0.25
1.6

1.4
0.2
|Vdd - Voh| (V)

|Vdd - Voh| (V)

1.2

0.15 1

0.8
0.1
0.6

0.4
0.05
0.2

0 0
1 1.5 2 2.5 3 3.5 4 2 7 12 17
-Iio (mA) -Iio (mA)

Figure 68. |VDD-VOH| @ IIO=2 mA (low current) Figure

current) 69. |VDD-VOH| @ IIO=10 mA (high

|Vdd - Voh| (V) at Iio=-2mA

0.165
|Vdd - Voh| (V) at Iio=-10mA
0.9
0.16
0.8
0.155
0.7
0.15
|Vdd - Voh| (V)

0.6
|Vdd - Voh| (V)

0.145
0.5
0.14
0.4
0.135
0.3
0.13
0.2
0.125
0.1
0.12
4 4.2 4.4 4.6 4.8 5 5.2 5.4 0
Vdd (V) 4 4.2 4.4 4.6 4.8 5 5.2 5.4
Vdd (V)

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14.9 Control pin characteristics

14.9.1 Asynchronous RESET pin
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
VIH Input High Level Voltage 0.7xVDD VDD V
VIL Input Low Voltage VSS 0.3xVDD V
Vhys Schmitt trigger voltage hysteresis 1) 400 mV
IIO=5mA 0.8
VOL Output low level voltage 2) VDD=5V V
IIO=7.5mA 1.3
RON Weak pull-up equivalent resistor 3) VIN=VSS VDD=5V 50 80 100 kΩ
External pin or 6 1/fSFOSC
tw(RSTL)out Generated reset pulse duration
internal reset sources 30 µs
th(RSTL)in External reset pulse hold time 4) 5 µs

Notes:
1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
2. The IIO current sunk must always respect the absolute maximum rating specified in Section 14.2 and the sum of IIO (I/
O ports and control pins) must not exceed IVSS.
3. The RON pull-up equivalent resistor is based on a resistive transistor. This data is based on characterization results,
not tested in production.
4. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin. All short pulses applied on
RESET pin with a duration below th(RSTL)in can be ignored.

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Control pin characteristics (Cont’d)

Figure 70. RESET pin protection when LVD is enabled.1)2)3)4)

VDD ST72XXX

Required Optional RON

(note 6) INTERNAL
EXTERNAL RESET
RESET Filter

0.01µF
1MΩ WATCHDOG
PULSE
GENERATOR
LVD RESET

Figure 71. RESET pin protection when LVD is disabled.1)

Recommended for EMC VDD ST72XXX

VDD VDD

RON
USER 0.01µF 4.7kΩ INTERNAL
EXTERNAL RESET
RESET Filter
CIRCUIT
0.01µF
PULSE
WATCHDOG
GENERATOR
Required

Note 1:
– The reset network protects the device against parasitic resets.
– The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the
device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
– Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go
below the VIL max. level specified in section 14.9.1 on page 121. Otherwise the reset will not be taken into account
internally.
– Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must en-
sure that the current sunk on the RESET pin is less than the absolute maximum value specified for IINJ(RESET) in
section 14.2.2 on page 109.
Note 2: When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-down
capacitor is required to filter noise on the reset line.
Note 3: In case a capacitive power supply is used, it is recommended to connect a 1MΩ pull-down resistor to the RESET
pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will add 5µA to the power
consumption of the MCU).
Note 4: Tips when using the LVD:
– 1. Check that all recommendations related to ICCCLK and reset circuit have been applied (see notes above).
– 2. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709 and
AN2017. If this cannot be done, it is recommended to put a 100nF + 1MΩ pull-down on the RESET pin.
– 3. The capacitors connected on the RESET pin and also the power supply are key to avoid any start-up marginality.
In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace 10nF pull-down on the
RESET pin with a 5µF to 20µF capacitor.”

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14.10 Communication interface characteristics

14.10.1 USB - universal bus interface
(Operating conditions TA = 0 to +70°C, VDD = 4.0 to 5.25V unless otherwise specified)
USB DC electrical characteristics
Symbol Parameter Conditions Min. Max. Unit
VDI Differential Input Sensitivity I(D+, D-) 0.2
Differential Common mode
VCM Includes VDI range 0.8 2.5
Range
VSE Single Ended Receiver Threshold 0.8 2.0
RL 1) of 1.5K ohms to V 2)
VOL Static Output Low 0.3
3.6v
RL 1) of 15K ohms to
VOH Static Output High 2.8 3.6
VSS
USBV USBVCC: voltage level 3)
VDD=5v 3.00 3.60
Notes:
1. RL is the load connected on the USB drivers.
2. All the voltages are measured from the local ground potential.
3. To improve EMC performance (noise immunity), it is recommended to connect a 100nF capacitor to the USBVCC pin.

Figure 72. USB: data signal rise and fall time

Differential
Data Lines Crossover
points
VCRS

VSS

tf tr

Table 27. USB: low-speed electrical characteristics

Symbol Parameter Conditions Min Max Unit
Driver characteristics:
CL=50 pF 1) 75 ns
tr Rise time 1)
CL=600 pF 300 ns
CL=50 pF 1) 75 ns
tf Fall Time
CL=600 pF 1) 300 ns
trfm Rise/ Fall Time matching tr/tf 80 120 %
Output signal Crossover
VCRS 1.3 2.0 V
Voltage

Note:
1. For more detailed information, please refer to Chapter 7 (Electrical) of the USB specification (version 1.1).

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Communication interface characteristics (Cont’d)

14.10.2 SCI - serial communication interface

Subject to general operating condition for VDD, fCPU, and TA unless otherwise specified.
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (RDI
and TDO).
Conditions
Baud
Symbol Parameter Accuracy Standard Unit
fCPU Prescaler Rate
vs. standard
Conventional mode
TR (or RR)=128, PR=13 300 ~300.48
TR (or RR)= 32, PR=13 1200 ~1201.92
fTx TR (or RR)= 16, PR=13 2400 ~2403.84
Communication frequency 8MHz ~0.16% TR (or RR)= 8, PR=13 4800 ~4807.69 Hz
fRx TR (or RR)= 4, PR=13 9600 ~9615.38
TR (or RR)= 16, PR= 3 10400 ~10416.67
TR (or RR)= 2, PR=13 19200 ~19230.77
TR (or RR)= 1, PR=13 38400 ~38461.54

14.10.3 I2C - Inter IC control interface

Refer to I/O port characteristics for more details on the input/output alternate function characteristics
(SDAI and SCLI).
The ST7 I2C interface meets the requirements of the Standard I2C communication protocol described in
the following table.
(Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified)
Standard mode I2C Fast mode I2C 4)
Symbol Parameter Unit
Min 1) Max 1) Min 1) Max 1)
tw(SCLL) SCL clock low time 4.7 1.3
µs
tw(SCLH) SCL clock high time 4.0 0.6
tsu(SDA) SDA setup time 250 100
th(SDA) SDA data hold time 0 3) 0 2) 900 3)
tr(SDA) ns
SDA and SCL rise time 1000 20+0.1Cb 300
tr(SCL)
tf(SDA)
SDA and SCL fall time 300 20+0.1Cb 300
tf(SCL)
th(STA) START condition hold time 4.0 0.6
µs
tsu(STA) Repeated START condition setup time 4.7 0.6
tsu(STO) STOP condition setup time 4.0 0.6 µs
tw(STO:STA) STOP to START condition time (bus free) 4.7 1.3 µs
Cb Capacitive load for each bus line 400 400 pF

Notes:
1. Data based on standard I2C protocol requirement, not tested in production.
2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of
SCL signal.
4. At 4MHz fCPU, max.I2C speed (400kHz) is not achievable. In this case, max. I2C speed will be approximately 260KHz.

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Communication interface characteristics (Cont’d)

Figure 73. Typical application with I2C Bus and timing diagram 1)
VDD VDD

4.7kΩ 4.7kΩ 100Ω SDAI

I2C BUS 100Ω SCLI

ST72XXX
REPEATED START
START
tsu(STA) tw(STO:STA)
START
SDA

tf(SDA) tr(SDA) tsu(SDA) th(SDA) STOP

SCK

th(STA) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) tsu(STO)

Note:
1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.

The following table gives the values to be written in

the I2CCCR register to obtain the required I2C
SCL line frequency .
Table 28. SCL frequency table
I2CCCR value
fSCL fCPU=4 MHz. fCPU=8 MHz.
(kHz) VDD = 4.1 V VDD = 5 V VDD = 4.1 V VDD = 5 V
RP=3.3kΩ RP=4.7kΩ RP=3.3kΩ RP=4.7kΩ RP=3.3kΩ RP=4.7kΩ RP=3.3kΩ RP=4.7kΩ
400 NA NA NA NA 83h 83 83h 83h
300 NA NA NA NA 85h 85h 85h 85h
200 83h 83h 83h 83h 8Ah 89h 8Ah 8Ah
100 10h 10h 10h 10h 24h 23h 24h 23h
50 24h 24h 24h 24h 4Ch 4Ch 4Ch 4Ch
20 5Fh 5Fh 5Fh 5Fh FFh FFh FFh FFh

Legend:
RP = External pull-up resistance
fSCL = I2C speed
NA = Not achievable
Notes:
– For speeds around 200 kHz, achieved speed can have ±5% tolerance
– For other speed ranges, achieved speed can have ±2% tolerance
The above variations depend on the accuracy of the external components used.

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14.11 8-bit ADC characteristics

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol Parameter Conditions Min Typ 1) Max Unit
fADC ADC clock frequency 4 MHz
2)
VAIN Conversion range voltage VSSA VDDA V
RAIN External input resistor 10 3) kΩ
CADC Internal sample and hold capacitor 6 pF
4)
tSTAB Stabilization time after ADC enable 0
µs
Conversion time (Sample+Hold) 6
fCPU=8MHz, fADC=2MHz
tADC - Sample capacitor loading time 4
1/fADC
- Hold conversion time 8

Figure 74. Typical application with ADC

VDD

VT
0.6V
RAIN AINx
VAIN ADC
VT
CIO 0.6V IL
~2pF ±1µA
VDD
VDDA

0.1µF
VSSA
ST72XXX

Notes:
1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V.
2. When VDDA and VSSA pins are not available on the pinout, the ADC refer to VDD and VSS.
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
4. The stabilization time of the AD converter is masked by the first tLOAD. The first conversion after the enable is then
always valid.

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8-bit ADC characteristics (Cont’d)

ADC accuracy with VDD=5V, fCPU=8 MHz, fADC=4 MHz RAIN< 10kΩ
Symbol Parameter Typ Max 2) 3)
1) 1.5 2
|ET| Total unadjusted error
1) 0.5 1
|EO| Offset error
|EG| Gain Error 1) 0.5 1.5
|ED| Differential linearity error 1) 1 1.5
1) 1 1.5
|EL| Integral linearity error
Notes:
1. ADC Accuracy vs. Negative Injection Current:
For IINJ-=0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is a loss of 1 LSB
for each 10KΩ increase of the external analog source impedance. This effect on the ADC accuracy has been observed
under worst-case conditions for injection:
- negative injection
- injection to an Input with analog capability, adjacent to the enabled Analog Input
- at 5V VDD supply, and worst case temperature.
2. Data based on characterization results over the whole temperature range, not tested in production.
3. Data based on characterization results, to guarantee 99.73% within ± max value from 0°C to 70°C ( ± 3σ distribution
limits).

Figure 75. ADC accuracy characteristics

Digital Result ADCDR EG
(1) Example of an actual transfer curve
255
(2) The ideal transfer curve
254 V –V
DDA SSA (3) End point correlation line
1LSB = -----------------------------------------
253 IDEAL 256

(2)
ET=Total Unadjusted Error: maximum deviation
ET between the actual and the ideal transfer curves.
7 (3) EO=Offset Error: deviation between the first actual
(1) transition and the first ideal one.
6
EG=Gain Error: deviation between the last ideal
5 transition and the last actual one.
EO EL ED=Differential Linearity Error: maximum deviation
4 between actual steps and the ideal one.
3 EL=Integral Linearity Error: maximum deviation
ED between any actual transition and the end point
2 correlation line.
1 LSBIDEAL
1
Vin (LSBIDEAL)
0
1 2 3 4 5 6 7 253 254 255 256
VSSA VDDA

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15 Package characteristics
In order to meet environmental requirements, ST JESD97. The maximum ratings related to solder-
offers these devices in ECOPACK® packages. ing conditions are also marked on the inner box la-
These packages have a Lead-free second level in- bel.
terconnect. The category of second Level Inter- ECOPACK is an ST trademark. ECOPACK speci-
connect is marked on the package and on the in- fications are available at: [Link]
ner box label, in compliance with JEDEC Standard

15.1 Package mechanical data

Figure 76. 34-pin Plastic Small Outline Package, shrink 300-mil width

mm inches
Dim.
h x 45× Min Typ Max Min Typ Max
L A 2.464 2.642 0.097 0.104
A C
A1 A1 0.127 0.292 0.005 0.012
a B 0.356 0.483 0.014 0.019
B e
D C 0.231 0.318 0.009 0.013
17.72 18.05
D 0.698 0.711
9 9
E 7.417 7.595 0.292 0.299
e 1.016 0.040
10.16 10.41
E H H 0.400 0.410
0 4
h 0.635 0.737 0.025 0.029
α 0° 8° 0° 8°
L 0.610 1.016 0.024 0.040
Number of Pins
N 34

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Figure 77. 32-pin Plastic Dual In-Line Package, shrink 400-mil width

mm inches
Dim.
Min Typ Max Min Typ Max
E eC
A 3.56 3.76 5.08 0.140 0.148 0.200
A1 0.51 0.020
A2 A
A2 3.05 3.56 4.57 0.120 0.140 0.180

A1 b 0.36 0.46 0.58 0.014 0.018 0.023

L
E1 b1 0.76 1.02 1.40 0.030 0.040 0.055
C eA
b2 b e eB
C 0.20 0.25 0.36 0.008 0.010 0.014
D D 27.43 28.45 1.080 1.100 1.120
E 9.91 10.41 11.05 0.390 0.410 0.435
E1 7.62 8.89 9.40 0.300 0.350 0.370
e 1.78 0.070
eA 10.16 0.400
eB 12.70 0.500
eC 1.40 0.055
L 2.54 3.05 3.81 0.100 0.120 0.150
Number of Pins
N 32

Figure 78. 24-pin Plastic Small Outline Package, 300-mil width

mm inches
Dim.
D
h x 45× Min Typ Max Min Typ Max
L A 2.35 2.65 0.093 0.104
A
A1 C A1 0.10 0.30 0.004 0.012
a B 0.33 0.51 0.013 0.020
B e
C 0.23 0.32 0.009 0.013
D 15.20 15.60 0.599 0.614
E 7.40 7.60 0.291 0.299
e 1.27 0.050
H 10.00 10.65 0.394 0.419
h 0.25 0.75 0.010 0.030
E H α 0° 8° 0° 8°
L 0.40 1.27 0.016 0.050
Number of Pins
N 24

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Figure 79. 48-pin Low profile Quad Flat package

mm inches1)
Dim.
Min Typ Max Min Typ Max
D A A 1.60 0.063
D1 A2 A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
A1
b 0.17 0.22 0.27 0.007 0.009 0.011
b C 0.09 0.20 0.004 0.008
D 9.00 0.354
D1 7.00 0.276
E1 E e
E 9.00 0.354
E1 7.00 0.276
e 0.50 0.020
c θ 0° 3.5° 7° 0° 3.5° 7°
L1
L 0.45 0.60 0.75 0.018 0.024 0.030
L
θ L1 1.00 0.039
Number of Pins
N 48
Note 1. values in inches are converted from
mm and rounded to 3 decimal digits.

Figure 80. 40-lead Very thin Fine pitch Quad Flat No-Lead Package
A2

SEATING
A3 mm inches1)
PLANE A1 Dim.
Min Typ Max Min Typ Max
D
A 0.80 0.90 1.00 0.031 0.035 0.039
A1 0.02 0.05 0.001 0.002
A2 0.65 1.00 0.026 0.039
A3 0.20 0.008
b 0.18 0.25 0.30 0.007 0.010 0.012
D 5.85 6.00 6.15 0.230 0.236 0.242
D2
D2 2.75 2.9 3.05 0.108 0.114 0.120
E 5.85 6 6.15 0.230 0.236 0.242
E2 E E2 2.75 2.9 3.05 0.108 0.114 0.120
e 0.50 0.020
PIN #1 ID TYPE C
RADIUS L 0.30 0.40 0.50 0.012 0.016 0.020
2 Number of Pins
1 N 40
L Note 1. values in inches are converted from mm
and rounded to 3 decimal digits.
b e

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15.2 Thermal characteristics

Symbol Ratings value Unit
Package thermal resistance (junction to ambient)
SDIP32 60
SO34 75
RthJA °C/W
SO24 70
LQFP48 80
QFN40 34
PD Power dissipation 1) 500 mW
2)
TJmax Maximum junction temperature 150 °C

Notes:
1. The power dissipation is obtained from the formula PD=PINT+PPORT where PINT is the chip internal power (IDDxVDD)
and PPORT is the port power dissipation determined by the user.
2. The average chip-junction temperature can be obtained from the formula TJ = TA + PD x RthJA.

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15.3 Soldering and glueability information

Recommended soldering information given only Recommended glue for SMD plastic packages
as design guidelines in Figure 81 and Figure 82. dedicated to molding compound with silicone:
■ Heraeus: PD945, PD955

■ Loctite: 3615, 3298

Figure 81. Recommended wave soldering profile (with 37% Sn and 63% Pb)

250
COOLING PHASE
200 5 sec (ROOM TEMPERATURE)

SOLDERING
150 80°C PHASE
Temp. [°C]
100
PREHEATING
PHASE
50

0 Time [sec]
20 40 60 80 100 120 140 160

Figure 82. Recommended reflow soldering oven profile (MID JEDEC)

250
Tmax=220+/-5°C
for 25 sec
200

150 sec above 183°C

150 90 sec at 125°C
Temp. [°C]
100 ramp down natural
ramp up 2°C/sec max
50 2°C/sec for 50sec

0 Time [sec]
100 200 300 400

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16 Device configuration and ordering information

Each device is available for production in user pro- 1: Reset generation when entering Halt mode
grammable versions (High Density FLASH) as
well as in factory coded versions (FASTROM).
OPT 3 = LVD Low Voltage Detector selection
ST72P63B devices are Factory Advanced Service This option bit selects the LVD.
Technique ROM (FASTROM) versions: they are 0: LVD enabled
factory programmed FLASH devices. 1: LVD disabled
ST72F63B FLASH devices are shipped to custom- Important note: on 4K and 8K ROM devices listed
ers with a default content (FFh). below, this option bit is forced by ST to 0 (LVD
This implies that FLASH devices have to be con- always enabled):
figured by the customer using the Option Byte ST7263BK1M1, ST7263BK2M1
while the ROM devices are factory-configured. ST7263BK2B1, ST7263BK2B1

16.1 Option Byte OPT 2 = Reserved.

The Option Byte allows the hardware configuration

of the microcontroller to be selected. OPT 1 = OSC24/12 Oscillator Selection
The Option Byte has no address in the memory This option bit selects the clock divider used to
map and can be accessed only in programming drive the USB interface at 6MHz.
mode using a standard ST7 programming tool. 0: 24 MHz oscillator
The default contents of the FLASH is fixed to F7h. 1: 12 Mhz oscillator
This means that all the options have “1” as their
default value, except LVD. OPT 0 = FMP_R Flash memory Read-Out protec-
In ROM devices, the Option Byte is fixed in hard- tion
ware by the ROM code. This option indicates if the user flash memory is
Option Byte protected against Read-Out. Read-Out protection,
when selected, provides a protection against Pro-
7 0
gram Memory content extraction and against write
access to Flash memory. Erasing the option bytes
WDG WD OSC FMP_ when the FMP_R option is selected, causes the
-- -- LVD -- whole user memory to be erased first and the de-
SW HALT 24/12 R
vice can be reprogrammed. Refer to the ST7 Flash
Programming Reference Manual and section 4.2.1
OPT 7:6 = Reserved. on page 17 for more details.
0: Read-Out protection enabled
OPT 5 = WDGSW Hardware or Software Watch- 1: Read-Out protection disabled
dog
This option bit selects the watchdog type.
0: Hardware enabled
1: Software enabled

OPT 4 = WDHALT Watchdog and Halt mode

This option bit determines if a RESET is generated
when entering Halt mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode

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16.2 Device ordering information and transfer of customer code

Customer code is made up of the FASTROM con- Refer to application note AN1635 for information
tents and the list of the selected options (if any). on the counter listing returned by ST after code
The FASTROM contents are to be sent on dis- has been transferred.
kette, or by electronic means, with the hexadeci- The STMicroelectronics Sales Organization will be
mal file in .S19 format generated by the develop- pleased to provide detailed information on con-
ment tool. All unused bytes must be set to FFh. tractual points.
The selected options are communicated to STMi-
croelectronics using the correctly completed OP-
TION LIST appended. See page 138.

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Table 29. Supported part numbers

Program memory RAM
Sales Type 1) Package
(bytes) (bytes)
ST72F63BH6T1 LQFP48
ST72F63BD6U1 QFN40
ST72F63BK6M1 32K Flash 1024 SO34
ST72F63BK6B1 SDIP32
ST72F63BE6M1 SO24
ST72F63BH4T1 LQFP48
ST72F63BK4M1 SO34
16K Flash 512
ST72F63BK4B1 SDIP32
ST72F63BE4M1 SO24
ST72F63BH2T1 LQFP48
ST72F63BK2U1 QFN40
ST72F63BK2M1 8K Flash 384 SO34
ST72F63BK2B1 SDIP32
ST72F63BE2M1 SO24
ST72F63BK1M1 SO34
ST72F63BK1B1 4K Flash 384 SDIP32
ST72F63BE1M1 SO24
ST7263BH6T1/xxx LQFP48
ST7263BD6U1/xxx QFN40
ST7263BK6M1/xxx 32K ROM 1024 SO34
ST7263BK6B1/xxx SDIP32
ST7263BE6M1/xxx SO24
ST7263BH4T1/xxx LQFP48
ST7263BK4M1/xxx SO34
16K ROM 512
ST7263BK4B1/xxx SDIP32
ST7263BE4M1/xxx SO24
ST7263BH2T1/xxx LQFP48
ST7263BK2U1/xxx QFN40
ST7263BK2M1/xxx 8K ROM 384 SO34
ST7263BK2B1/xxx SDIP32
ST7263BE2M1/xxx SO24
ST7263BK1M1/xxx SO34
ST7263BK1B1/xxx 4K ROM 384 SDIP32
ST7263BE1M1/xxx SO24
ST72P63BH6T1 LQFP48
ST72P63BD6U1 QFN40
ST72P63BK6M1 32K FASTROM 1024 SO34
ST72P63BK6B1 SDIP32
ST72P63BE6M1 SO24
ST72P63BH4T1 LQFP48
ST72P63BK4M1 SO34
16K FASTROM 512
ST72P63BK4B1 SDIP32
ST72P63BE4M1 SO24

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ST72P63BH2T1 LQFP48
ST72P63BK2U1 QFN40
ST72P63BK2M1 8K FASTROM 384 SO34
ST72P63BK2B1 SDIP32
ST72P63BE2M1 SO24
ST72P63BK1M1 SO34
ST72P63BK1B1 4K FASTROM 384 SDIP32
ST72P63BE1M1 SO24
Note:
Contact ST sales office for product availability

1. /xxx stands for the ROM code name assigned by STMicroelectronics

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16.3 Development tools

Development tools for the ST7 microcontrollers in- fine-tuning of your application. The Cosmic C
clude a complete range of hardware systems and Compiler is available in a free version that outputs
software tools from STMicroelectronics and third- up to 16K of code.
party tool suppliers. The range of tools includes The range of hardware tools includes full-featured
solutions to help you evaluate microcontroller pe- ST7-EMU3 series emulators and the low-cost
ripherals, develop and debug your application, and RLink in-circuit debugger/programmer. These
program your microcontrollers. tools are supported by the ST7 Toolset from
16.3.1 Evaluation tools and starter kits STMicroelectronics, which includes the STVD7 in-
ST offers complete, affordable starter kits and tegrated development environment (IDE) with
full-featured evaluation boards that allow you to high-level language debugger, editor, project man-
evaluate microcontroller features and quickly start ager and integrated programming interface.
developing ST7 applications. Starter kits are com- 16.3.3 Programming tools
plete, affordable hardware/software tool packages During the development cycle, the ST7-EMU3 se-
that include features and samples to to help you ries emulators and the RLink provide in-circuit
quickly start developing your application. ST eval- programming capability for programming the Flash
uation boards are open-design, embedded sys- microcontroller on your application board.
tems, which are developed and documented to
serve as references for your application design. In addition ST provides dedicated programming
They include sample application software to help tools including the ST7-EPB programming
you demonstrate, learn about and implement your boards, which include all the sockets required to
ST7’s features. program any of the devices in a specific ST7 sub-
family.
16.3.2 Development and debugging tools
For production programming of ST7 devices, ST’s
Application development for ST7 is supported by third-party tool partners also provide a complete
fully optimizing C Compilers and the ST7 Assem- range of gang and automated programming solu-
bler-Linker toolchain, which are all seamlessly in- tions, which are ready to integrate into your pro-
tegrated in the ST7 integrated development envi- duction environment.
ronments in order to facilitate the debugging and
16.3.4 Order codes for ST7263B development tools
Table 30. Development tool order codes for the ST7263B family
In-circuit debugger/ Dedicated
MCU Starter kit Evaluation board Emulator
programmer programmer
ST72F63B-SK/ ST7MDTULS-
ST7263B ST7MDTU3-EMU3 STX-RLINK ST7MDTU3-EPB
RAIS EVAL

For additional ordering codes for spare parts and

accessories, refer to the online product selector at
[Link].

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ST7263B microcontroller option list

(Last update: Mar 2007)

Customer: ............................................................................
Address: ............................................................................
............................................................................
Contact: ............................................................................
Phone No: ............................................................................
Reference: ............................................................................

ROM or FASTROM code must be sent in .S19 format.

Hex extension cannot be processed.
STMicroelectronics references:

Device Type/Memory Size/Package (check only one option):

-----------------------------------------------------------------------------------------------------------------------------------------------------------
ROM DEVICE: | 4K | 8K | 16K | 32K |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
SO24: | [ ] ST7263BE1M1 | [ ] ST7263BE2M1 | [ ] ST7263BE4B1 | [ ] ST7263BE6M1 |
PSDIP32: | [ ] ST7263BK1B1 | [ ] ST7263BK2B1 | [ ] ST7263BK4B1 | [ ] ST7263BK6B1 |
SO34: | [ ] ST7263BK1M1 | [ ] ST7263BK2M1 | [ ] ST7263BK4M1 | [ ] ST7263BK6M1 |
QFN40: | | [ ] ST7263BK2U1 | | [ ] ST7263BD6U1 |
LQFP48: | | [ ] ST7263BH2T1 | [ ] ST7263BH4T1 | [ ] ST7263BH6T1 |

-----------------------------------------------------------------------------------------------------------------------------------------------------------
FASTROM: | 4K | 8K | 16K | 32K |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
SO24: | [ ] ST72P63BE1M1 | [ ] ST72P63BE2M1 | [ ] ST72P63BE4M1 | [ ] ST72P63BE6M1 |
PSDIP32: | [ ] ST72P63BK1B1 | [ ] ST72P63BK2B1 | [ ] ST72P63BK4B1 | [ ] ST72P63BK6B1 |
SO34: | [ ] ST72P63BK1M1 | [ ] ST72P63BK2M1 | [ ] ST72P63BK4M1 | [ ] ST72P63BK6M1 |
QFN40: | | [ ] ST72P63BK2U1 | | [ ] ST72P63BD6U1 |
LQFP48: | | [ ] ST72P63BH2T1 | [ ] ST72P63BH4T1 | [ ] ST72P63BH6T1 |

-----------------------------------------------------------------------------------------------------------------------------------------------------------
DIE FORM: | 4K | 8K | 16K | 32K |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
24-pin: | [ ] (as E1M1) | [ ] (as E2M1) | [ ] (as E4M1) | [ ] (as E6M1) |
32-pin: | [ ] (as K1B1) | [ ] (as K2B1) | [ ] (as K4B1) | [ ] (as K6B1) |
34-pin: | [ ] (as K1M1) | [ ] (as K2M1) | [ ] (as K4M1) | [ ] (as K6M1) |
40-pin: | | [ ] (as K2U1) | | [ ] (as D6U1) |
48-pin: | | [ ] (as H2T1) | [ ] (as H4T1) | [ ] (as H6T1) |

Conditioning (check only one option):

Packaged Product | Die Product (dice tested at 25°C only)
------------------------------------------------------------------------------------------------------------------------
[ ] Tape & Reel (SO package only) | [ ] Tape & Reel
[ ] Tube | [ ] Inked wafer
| [ ] Sawn wafer on sticky foil

Special Marking ( ROM only): [ ] No [ ] Yes "_ _ _ _ _ _ _ _ _ _ _ _ _"

Authorized characters are letters, digits, '.', '-', '/' and spaces only.
For marking, one line is possible with a maximum of 13 characters.

Watchdog Selection: [ ] Software activation [ ] Hardware activation

Halt when Watchdog on: [ ] Reset [ ] No reset
LVD Reset * [ ] Disabled* [ ] Enabled*
* LVD is forced to 0 (LVD always enabled) for 4K and 8K ROM devices
(sales types ST7263BK1B1, ST7263BK2B1, ST7263BK1M1, ST72BK2M1 only)

Oscillator Selection: [ ] 24 MHz. [ ] 12 MHz.

Read-Out Protection: [ ] Disabled [ ] Enabled

Date ............................................................................

Signature ............................................................................
Please download the latest version of this option list from: [Link]

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16.4 ST7 application notes

Table 31. ST7 application notes
IDENTIFICATION DESCRIPTION
APPLICATION EXAMPLES
AN1658 SERIAL NUMBERING IMPLEMENTATION
AN1720 MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS
AN1755 A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555
AN1756 CHOOSING A DALI IMPLEMENTATION STRATEGY WITH ST7DALI
A HIGH PRECISION, LOW COST, SINGLE SUPPLY ADC FOR POSITIVE AND NEGATIVE IN-
AN1812
PUT VOLTAGES
EXAMPLE DRIVERS
AN 969 SCI COMMUNICATION BETWEEN ST7 AND PC
AN 970 SPI COMMUNICATION BETWEEN ST7 AND EEPROM
AN 971 I²C COMMUNICATION BETWEEN ST7 AND M24CXX EEPROM
AN 972 ST7 SOFTWARE SPI MASTER COMMUNICATION
AN 973 SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER
AN 974 REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE
AN 976 DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION
AN 979 DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC
AN 980 ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE
AN1017 USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER
AN1041 USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOÏD)
AN1042 ST7 ROUTINE FOR I²C SLAVE MODE MANAGEMENT
AN1044 MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS
AN1045 ST7 S/W IMPLEMENTATION OF I²C BUS MASTER
AN1046 UART EMULATION SOFTWARE
AN1047 MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS
AN1048 ST7 SOFTWARE LCD DRIVER
AN1078 PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE
AN1082 DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERALS REGISTERS
AN1083 ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE
AN1105 ST7 PCAN PERIPHERAL DRIVER
AN1129 PWM MANAGEMENT FOR BLDC MOTOR DRIVES USING THE ST72141
AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS
AN1130
WITH THE ST72141
AN1148 USING THE ST7263 FOR DESIGNING A USB MOUSE
AN1149 HANDLING SUSPEND MODE ON A USB MOUSE
AN1180 USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD
AN1276 BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER
AN1321 USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE
AN1325 USING THE ST7 USB LOW-SPEED FIRMWARE V4.X
AN1445 EMULATED 16-BIT SLAVE SPI
AN1475 DEVELOPING AN ST7265X MASS STORAGE APPLICATION
AN1504 STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER
AN1602 16-BIT TIMING OPERATIONS USING ST7262 OR ST7263B ST7 USB MCUS
AN1633 DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION IN ST7 NON-USB APPLICATIONS
AN1712 GENERATING A HIGH RESOLUTION SINEWAVE USING ST7 PWMART
AN1713 SMBUS SLAVE DRIVER FOR ST7 I2C PERIPHERALS
AN1753 SOFTWARE UART USING 12-BIT ART

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Table 31. ST7 application notes

IDENTIFICATION DESCRIPTION
AN1947 ST7MC PMAC SINE WAVE MOTOR CONTROL SOFTWARE LIBRARY
GENERAL PURPOSE
AN1476 LOW COST POWER SUPPLY FOR HOME APPLIANCES
AN1526 ST7FLITE0 QUICK REFERENCE NOTE
AN1709 EMC DESIGN FOR ST MICROCONTROLLERS
AN1752 ST72324 QUICK REFERENCE NOTE
PRODUCT EVALUATION
AN 910 PERFORMANCE BENCHMARKING
AN 990 ST7 BENEFITS VS INDUSTRY STANDARD
AN1077 OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS
AN1086 U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING
AN1103 IMPROVED B-EMF DETECTION FOR LOW SPEED, LOW VOLTAGE WITH ST72141
AN1150 BENCHMARK ST72 VS PC16
AN1151 PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876
AN1278 LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS
PRODUCT MIGRATION
AN1131 MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324
AN1322 MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B
AN1365 GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264
AN1604 HOW TO USE ST7MDT1-TRAIN WITH ST72F264
AN2200 GUIDELINES FOR MIGRATING ST7LITE1X APPLICATIONS TO ST7FLITE1XB
PRODUCT OPTIMIZATION
AN 982 USING ST7 WITH CERAMIC RESONATOR
AN1014 HOW TO MINIMIZE THE ST7 POWER CONSUMPTION
AN1015 SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE
AN1040 MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES
AN1070 ST7 CHECKSUM SELF-CHECKING CAPABILITY
AN1181 ELECTROSTATIC DISCHARGE SENSITIVE MEASUREMENT
AN1324 CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS
AN1502 EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY
AN1529 EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY
ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCILLA-
AN1530
TOR
AN1605 USING AN ACTIVE RC TO WAKEUP THE ST7LITE0 FROM POWER SAVING MODE
AN1636 UNDERSTANDING AND MINIMIZING ADC CONVERSION ERRORS
AN1828 PIR (PASSIVE INFRARED) DETECTOR USING THE ST7FLITE05/09/SUPERLITE
AN1946 SENSORLESS BLDC MOTOR CONTROL AND BEMF SAMPLING METHODS WITH ST7MC
AN1953 PFC FOR ST7MC STARTER KIT
AN1971 ST7LITE0 MICROCONTROLLED BALLAST
PROGRAMMING AND TOOLS
AN 978 ST7 VISUAL DEVELOP SOFTWARE KEY DEBUGGING FEATURES
AN 983 KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE
AN 985 EXECUTING CODE IN ST7 RAM
AN 986 USING THE INDIRECT ADDRESSING MODE WITH ST7
AN 987 ST7 SERIAL TEST CONTROLLER PROGRAMMING
AN 988 STARTING WITH ST7 ASSEMBLY TOOL CHAIN
AN1039 ST7 MATH UTILITY ROUTINES

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Table 31. ST7 application notes

IDENTIFICATION DESCRIPTION
AN1071 HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER
AN1106 TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7
PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO-
AN1179
GRAMMING)
AN1446 USING THE ST72521 EMULATOR TO DEBUG AN ST72324 TARGET APPLICATION
AN1477 EMULATED DATA EEPROM WITH XFLASH MEMORY
AN1527 DEVELOPING A USB SMARTCARD READER WITH ST7SCR
AN1575 ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS
AN1576 IN-APPLICATION PROGRAMMING (IAP) DRIVERS FOR ST7 HDFLASH OR XFLASH MCUS
AN1577 DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION FOR ST7 USB APPLICATIONS
AN1601 SOFTWARE IMPLEMENTATION FOR ST7DALI-EVAL
AN1603 USING THE ST7 USB DEVICE FIRMWARE UPGRADE DEVELOPMENT KIT (DFU-DK)
AN1635 ST7 CUSTOMER ROM CODE RELEASE INFORMATION
AN1754 DATA LOGGING PROGRAM FOR TESTING ST7 APPLICATIONS VIA ICC
AN1796 FIELD UPDATES FOR FLASH BASED ST7 APPLICATIONS USING A PC COMM PORT
AN1900 HARDWARE IMPLEMENTATION FOR ST7DALI-EVAL
AN1904 ST7MC THREE-PHASE AC INDUCTION MOTOR CONTROL SOFTWARE LIBRARY
AN1905 ST7MC THREE-PHASE BLDC MOTOR CONTROL SOFTWARE LIBRARY
SYSTEM OPTIMIZATION
AN1711 SOFTWARE TECHNIQUES FOR COMPENSATING ST7 ADC ERRORS
AN1827 IMPLEMENTATION OF SIGMA-DELTA ADC WITH ST7FLITE05/09
AN2009 PWM MANAGEMENT FOR 3-PHASE BLDC MOTOR DRIVES USING THE ST7FMC
AN2030 BACK EMF DETECTION DURING PWM ON TIME BY ST7MC

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17 Known limitations

17.1 PA2 limitation with OCMP1 enabled On reception of the NACK, ST7 can send a re-start
and Slave address to re-initiate communication
Description
This limitation affects only Rev B Flash devices 17.5 Halt mode power consumption with ADC
(with Internal Sales Type 72F63Bxxxxx$x7); it has
been corrected in Rev W Flash devices (with Inter- on
nal Sales Type 72F63Bxxxxx$x9). Description
Note: Refer to Figure 83 on page 143 If the A/D converter is being used when Halt mode
When Output Compare 1 function (OCMP1) on pin is entered, the power consumption in Halt mode
PA6 is enabled by setting the OC1E bit in the may exceed the maximum specified in the datash-
TCR2 register, pin PA2 is also affected. eet.
In particular, PA2 is switched to its alternate func- Workaround
tion mode, SCL. As a consequence, the PA2 pin is Switch off the ADC by software (ADON=0) before
forced to be floating (steady level of I2C clock) executing a HALT instruction.
even if port configuration (PADDR+PADR) has set
it as output low. However, it can be still used as an
input or can be controlled by the I2C cell when en- 17.6 SCI wrong break duration
abled (where I2C is available). Description
A single break character is sent by setting and re-
17.2 Unexpected reset fetch setting the SBK bit in the SCICR2 register. In
Description some cases, the break character may have a long-
er duration than expected:
If an interrupt request occurs while a "POP CC" in-
struction is executed, the interrupt controller does - 20 bits instead of 10 bits if M=0
not recognise the source of the interrupt and, by - 22 bits instead of 11 bits if M=1.
default, passes the RESET vector address to the In the same way, as long as the SBK bit is set,
CPU. break characters are sent to the TDO pin. This
Workaround may generate one break more than expected.
To solve this issue, a "POP CC" instruction must Occurrence
always be preceded by a "SIM" instruction. The occurrence of the problem is random and pro-
portional to the baudrate. With a transmit frequen-
17.3 USB behavior with LVD disabled cy of 19200 baud (fCPU=8MHz and SCI-
BRR=0xC9), the wrong break duration occurrence
Description is around 1%.
On 4K and 8K ROM devices (ST7263BK1M1, Workaround
ST72BK2M1, ST7263BKB1, ST7263BK2B1 only) If this wrong duration is not compliant with the
if the LVD is disabled, the USB is disabled by hard- communication protocol in the application, soft-
ware. So, the LVD is forced by ST to 0 (LVD ena- ware can request that an Idle line be generated
bled). Refer to the ST7263B option list for details. before the break character. In this case, the break
duration is always correct assuming the applica-
17.4 I2C multimaster tion is not doing anything between the idle and the
break. This can be ensured by temporarily disa-
Description bling interrupts.
In multimaster configurations, if the ST7 I2C re- The exact sequence is:
ceives a START condition from another I2C mas-
ter after the START bit is set in the I2CCR register - Disable interrupts
and before the START condition is generated by - Reset and Set TE (IDLE request)
the ST7 I2C, it may ignore the START condition - Set and Reset SBK (Break Request)
from the other I2C master. In this case, the ST7 - Re-enable interrupts
master will receive a NACK from the other device.

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Figure 83. Identifying silicon revision from device marking and box label
The silicon revision can be identified either by Rev letter or obtained via a trace code.
Follow the procedure below:

1. Identify the silicon revision letter from either the device package or the box label.
For example, “B”, etc.
2. If the revision letter is not present, obtain the silicon revision by contacting your local ST
office with the trace code information printed on either the box label or the device package.

Silicon Rev

STMicroelectronics
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Trace code xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
ST7xxxxxxxxx
TYPE xxxxxxxxxxx$x7

Total Qty XX
Trace code XXXXXXXXX XX XX

Marking
Bulk ID
B
XXXXXXXXXX Silicon Rev
XXXXXXXXXXXX

Device package (SO34 shown)

Example box label

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18 Revision history
Date Revision Main changes
New revision created by merging 32K Flash and non-32K Flash datasheets together
Memory Map, Figure 7, expanded to handle all devices and memory sizes
Operating conditions with LVD values modified, section 14.3.2 on page 110
Supply current characteristics values and notes updated, section 14.4 on page 111
IDD Run and Wait graphs replaced, Figure 52 and Figure 53 on page 111
Control timing characteristics modified, section 14.5.2 on page 112
Flash memory table notes and tPROG typical value updated, section 14.6.2 on page 114
Notes added for I/O Port Pin characteristics table, section 14.8.1 on page 117
Note for RPU modified, removing reference to data characterization, Section 14.8.1
IPU and RPU graphs added, Figure 58 and Figure 59 on page 118
Notes updated for USB low speed electrical characteristics
Output voltage/current graphs added, Figures 60-69
27-May-05 3.0
Thermal Characteristics added for SO24 and TQFP48 packages, section 15.2 on page 131
Important note added for OPT 3 Option Byte (LVD), section 16.1 on page 133
Supported Part Numbers table updated with full sales type codes, Table 29
Option List updated with all device options, page 138
Important notes updated with ‘USB behavior with LVD disabled’, section 17.3 on page 142
Clock block diagram redrawn, Figure 18 on page 26
DFU added to title and features list, page 1
Removed unnecessary notes related to Typical values (already mentioned in section 14.1.2
on page 108) in electrical characteristic tables sections: Section 14.3.2, Section 14.4, Sec-
tion 14.6.2, Section 14.8.1, Section 14.9.1 and Section 14.11
Added note for max values in ADC Accuracy, Section 14.11
Static Latch Up (LU) class tested only for TA=25°C, section [Link] on page 116
Flash memory minimum data retention increased to 40 years, section 14.6.2 on page 114
AF bit text modified concerning SCL, I2C Chapter Section 12.5.7, "Register description"
Reference made to the Flash Programming Reference Manual for Flash timing values
19-Sep-05 4.0 Reset pulse generated by WDG changed to 30µs, section 12.1 on page 42
Modified text in section 12.3 on page 64, adding Parity error as an interrupt
Added ECOPACK information in section 15 on page 128
Modified IS value and corresponding note in section 14.8.1 on page 117
32K and 8K QFN40 Packages added
06-Apr-06 5.0 4K SO24 Package added
TQFP package renamed to LQFP
Important Notes section renamed to Known Limitations, section 17 on page 142
03-Oct-06 6.0 New PA2 limitation added, section 17 on page 142
Figure 83. on page 143 added for silicon revision identification
Root part numbers added in datasheet header and in Table 1, "Device summary".
New 16K LQFP48 package added to product family.
Note added to VOH data in section 14.8.2 on page 118
20-Aug-07 7.0
List of supported partnumber availability updated, Table 29, "Supported part numbers"
Download address updated in Section 16.3.4, "Order codes for ST7263B development
tools" and Option list.

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