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Verilog Alarm Clock Module Design

The document describes a Verilog module for an alarm clock, detailing its inputs, outputs, and functionality. It includes a clock signal, reset functionality, and the ability to set and trigger alarms based on specified hours and minutes. Additionally, a testbench is provided to simulate the alarm clock's behavior under various conditions.

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Aditya Chikkmath
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6 views5 pages

Verilog Alarm Clock Module Design

The document describes a Verilog module for an alarm clock, detailing its inputs, outputs, and functionality. It includes a clock signal, reset functionality, and the ability to set and trigger alarms based on specified hours and minutes. Additionally, a testbench is provided to simulate the alarm clock's behavior under various conditions.

Uploaded by

Aditya Chikkmath
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

module alarm_clock( );

//What are the Inputs?

input Clk;

input reset;

input M[5:0], H[4:0];

input h[4:0],m[5:0];

input IN,AL,ST;

//What are the Outputs?

output reg [5:0] seconds;

output reg [5:0] minutes;

output reg [4:0] hours;

output reg ALARM;

always @(posedge(Clk) or posedge(reset))

begin

if(reset == 1'b1)

begin //check for active high reset.

//reset the time.

seconds = 0;

minutes = 0;

hours = 0;

end

else if(Clk== 1'b1) begin //at the beginning of each second

if (IN) begin

hours<=H;
minutes<=M;

seconds = seconds + 1;

if(seconds == 60)

seconds = 0;

minutes = minutes + 1;

if(minutes == 60)

minutes = 0;

hours = hours + 1;

if(hours == 24)

hours = 0;

end

else

seconds = seconds + 1;

if(seconds == 60)

seconds = 0;

minutes = minutes + 1;

if(minutes == 60)

minutes = 0;

hours = hours + 1;

if(hours == 24)

hours = 0;

end

end

//Alarm function
always @(posedge(clk) or posedge(reset))

begin

if(reset)

AL<=0;

else

begin

if({h,m}=={H,M})

begin

if(AL)

ALARM<= 1;

end

if(ST)

Alarm <=0;

end

end

endmodule

Testbench
module alarm_clock_tb( );

reg Clk;

reg reset;

reg M[5:0],H[4:0];

reg h[4:0],m[5:0];

reg IN,AL,ST;

wire [5:0] seconds;


wire [5:0] minutes;

wire [4:0] hours;

wire ALARM;

alarm_clock uut(Clk,reset,M,H,h,m,IN,AL,ST,seconds,minutes,hours,ALARM);

// clock 10Hz

initial

begin

Clk = 0;

forever #50 clk = ~clk;

end

initial

begin

reset=1;

H=14;

M=45;

#1000

reset=0;

IN=0;

H=4;

M=25;

#1000

IN=1;

H=5;

M=15;

IN=0;

#1000

IN=1;

H=3;

M=0;

h=3;

m=0;
AL=0;

#1000

AL=1;

#1000

ST=1;

end

endmodule

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