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VHDL XOR Gate Code and Test Bench

The document contains VHDL code for an XOR gate and its corresponding test bench. The XOR gate takes two input signals and produces an output based on the XOR logic. The test bench simulates various input combinations to verify the functionality of the XOR gate.

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Mrityunjay

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0% found this document useful (0 votes)

2 views3 pages

VHDL XOR Gate Code and Test Bench

Uploaded by

Mrityunjay

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as DOCX, PDF, TXT or read online on Scribd

VHDL CODE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity xorgate is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

y : out STD_LOGIC

);

end xorgate;

architecture Behavioral of xorgate is

begin

y<= a xor b;

end Behavioral;

TEST BENCH

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY xorgate_tb IS

END xorgate_tb;

ARCHITECTURE behavior OF xorgate_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT xorgate

PORT(

a : IN std_logic;

b : IN std_logic;
y : out std_logic);

END COMPONENT;

--Inputs

signal a : std_logic := '0';

signal b : std_logic := '0';

--Outputs

signal y : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: xorgate PORT MAP (

a => a,

b => b,

y => y

);

-- Stimulus process

stim_proc: process

begin

a <= '0';

b <= '0';

wait for 100 ns;

a <= '1';

b <= '0';

wait for 100 ns;

a <= '0';

b <= '1';

wait for 100 ns;

a <= '1';

b <= '1';

wait for 100 ns;

wait;

end process;

END;

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VHDL XOR Gate Code and Test Bench

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VHDL XOR Gate Code and Test Bench

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VHDL CODE

architecture Behavioral of xorgate is

ARCHITECTURE behavior OF xorgate_tb IS

-- Component Declaration for the Unit Under Test (UUT)

signal a : std_logic := '0';

signal b : std_logic := '0';

-- Instantiate the Unit Under Test (UUT)

uut: xorgate PORT MAP (

wait for 100 ns;

wait for 100 ns;

wait for 100 ns;

wait for 100 ns;

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